JPH01235330A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01235330A JPH01235330A JP6385088A JP6385088A JPH01235330A JP H01235330 A JPH01235330 A JP H01235330A JP 6385088 A JP6385088 A JP 6385088A JP 6385088 A JP6385088 A JP 6385088A JP H01235330 A JPH01235330 A JP H01235330A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- diffusion
- type
- layer
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000012535 impurity Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、拡散抵抗層を有する半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device having a diffused resistance layer.
従来集積回路内に形成される抵抗構造の一つに拡散抵抗
がある。第３図（ａ）は従来の拡散抵抗構造を示す平面
図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図である。第
３図（ａ） 、 （ｂ）において、Ｐ型基板ｌ上に形成
された、Ｎ型エピタキシャル層２の一部をＰ型分離拡散
層３によって、電気的に分離し、この分離されたＮ型エ
ピタキシャル層２内に、他の部分で形成されるトランジ
スタ等のＰ型ベース拡散と同時に、幅Ｗ、長さβのＰ型
拡散抵抗層５を形成し、Ｐ型拡散抵抗層５０両端に、抵
抗層５を覆う絶縁膜７にコンタクト穴８を形成し、Ａ４
等の金属薄膜により電極９を形成しＰ型拡散層５を抵抗
体として使用する。この抵抗体の抵抗値Ｒは、Ｐ型拡散
層３のシート抵抗ρ８より次式で示される。One of the resistor structures conventionally formed in integrated circuits is a diffused resistor. FIG. 3(a) is a plan view showing a conventional diffused resistance structure, and FIG. 3(b) is a cross-sectional view taken along line AA in FIG. 3(a). In FIGS. 3(a) and 3(b), a part of the N-type epitaxial layer 2 formed on the P-type substrate l is electrically isolated by a P-type isolation diffusion layer 3, and the separated N In the type epitaxial layer 2, a P type diffused resistance layer 5 having a width W and a length β is formed at the same time as the P type base diffusion of transistors etc. formed in other parts, and at both ends of the P type diffused resistance layer 50, A contact hole 8 is formed in the insulating film 7 covering the resistance layer 5, and the A4
The electrode 9 is formed of a metal thin film such as the like, and the P-type diffusion layer 5 is used as a resistor. The resistance value R of this resistor is expressed by the following equation based on the sheet resistance ρ8 of the P-type diffusion layer 3.
β
Ｒ−ρ８−
〔発明が解決しようとする課題〕
上述した従来の拡散抵抗では、抵抗値は、１） Ｐ型
拡散抵抗層のシート抵抗値２） Ｐ型拡散抵抗層の幅
３） Ｐ型拡散抵抗層の長さ
の３つのパラメータにより制御されていた。しかし、１
）を変化させると、他の領域に同時に形成される機能素
子の構造定数が変化する欠点がある。β R−ρ8− [Problems to be Solved by the Invention] In the conventional diffused resistor described above, the resistance value is: 1) Sheet resistance value of the P type diffused resistance layer 2) Width of the P type diffused resistance layer 3) P type It was controlled by three parameters: the length of the diffused resistance layer. However, 1
) has the disadvantage that the structural constants of functional elements simultaneously formed in other regions change.
また、２）は、Ｐ型拡散抵抗層形成のため行われるフォ
トリソグラフィーの精度に強い影響を受け、幅Ｗの最小
寸法に限界が生じる欠点がある。更に、３）は、一般に
抵抗値制御に良く使われているが、高抵抗値を実現する
ためには、長さβを長くする必要があり、抵抗形成部の
面積を増大させる欠点がある。In addition, 2) is strongly influenced by the precision of the photolithography performed to form the P-type diffused resistance layer, and has the drawback that there is a limit to the minimum dimension of the width W. Furthermore, although method 3) is commonly used for resistance value control, in order to achieve a high resistance value, it is necessary to increase the length β, which has the disadvantage of increasing the area of the resistance forming portion.
上記問題点に対し本発明に係る拡散抵抗構造は、Ｐ型ま
たはＮ型の一導電型半導体層中に、抵抗部となる２例以
上の反対導電型拡散抵抗層が同時に形成され、かつ、隣
り合う拡散抵抗層の一部が横方向拡散により重なり合う
構造を有し、かつ、重なり合う領域の横方向抵抗が他の
横方向抵抗より高くなることにより、従来得難かった高
精度の高抵抗拡散抵抗を得ている。In order to solve the above-mentioned problems, the diffused resistance structure according to the present invention has two or more opposite conductivity type diffused resistance layers, which serve as resistance parts, formed simultaneously in a P-type or N-type semiconductor layer of one conductivity type, and which are adjacent to each other. Parts of the matching diffused resistance layers have a structure in which they overlap due to lateral diffusion, and the lateral resistance of the overlapping region is higher than the other lateral resistance, making it possible to achieve high-precision, high-resistance diffused resistance, which was previously difficult to obtain. It has gained.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図であり、同図
（ｂ）は同図（ａ）のＡ−Ａ断面図である。第１図（ａ
） 、 （ｂ）において、Ｐ型基板ｌの上層側にＮ型エ
ピタキシャル層２が形成され、Ｐ型分離拡散層３により
電気的に分離されたＮ型エピタキシャル層２内に、拡散
抵抗となるＰ型拡散層４を第１図（ａ）中耕線部のよう
に所定間隔をおいた４つの領域から形成すると、この際
、隣り合う拡散層の横方向拡散により、所定間隔の部分
は重ね合わせ領域６を形成する。この重ね合わせ領域６
の横方向抵抗が、Ｐ型拡散抵抗層４の横方向抵抗より増
加するため、高抵抗体が得られる。FIG. 1(a) is a plan view of one embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line AA in FIG. 1(a). Figure 1 (a
), (b), an N-type epitaxial layer 2 is formed on the upper layer side of a P-type substrate l, and a P layer serving as a diffusion resistance is formed in the N-type epitaxial layer 2 electrically isolated by a P-type isolation diffusion layer 3. When the mold diffusion layer 4 is formed from four regions spaced apart at a predetermined interval as shown in FIG. form 6. This overlapping area 6
Since the lateral resistance of the P-type diffused resistance layer 4 is greater than that of the P-type diffused resistance layer 4, a high resistance body is obtained.
第２図は本発明の実施例２の断面図である。第２図にお
いて、本実施例２は、実施例１で説明した構造のＰ型拡
散抵抗層４内に、重ね合わせ領域を覆う状態でＮ型拡散
層１０を形成したもので、あり、本例は第１実施例より
さらに高抵抗化する利点がある。FIG. 2 is a sectional view of Example 2 of the present invention. In FIG. 2, this embodiment 2 is one in which an N-type diffused layer 10 is formed in the P-type diffused resistance layer 4 having the structure explained in embodiment 1, covering the overlapping region. This has the advantage that the resistance is higher than that of the first embodiment.
以上説明したように本発明は、集積回路中に形成される
拡散抵抗を複数の拡散領域の横方向拡散による重ね合わ
せにより形成することにより、抵抗形成部の面積を増大
することなく、高抵抗を形成することができる。As explained above, the present invention forms a diffused resistor formed in an integrated circuit by overlapping a plurality of diffusion regions by lateral diffusion, thereby achieving high resistance without increasing the area of the resistor forming part. can be formed.
第１図（ａ）は本発明の一実施例の平面図、同図（ｂ）
は同図（ａ）のＡ−Ａ断面図、第２図は本発明の第２実
施例の断面図、第３図（ａ）は従来の半導体装置の断面
図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図である。
１・・・・・・Ｐ型基板、２・・・・・・Ｎ型エピタキ
シャル層、３・・・・・・Ｐ型分離拡散層、４・・・・
・・離散したＰ型拡散抵抗層、５・・・・・・従来のＰ
型拡散抵抗層、６・・・・・・重ね合せ領域、７・・・
・・・絶縁膜、８・・・・・・コンタクト穴、９・・・
・・・電極、ＩＯ・・・・・・Ｎ型拡散層。
代理人 弁理士 内 原 音
（’ａ、）
菊／図
／ 菊 乙ｌFIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
2 is a sectional view of the second embodiment of the present invention, FIG. 3(a) is a sectional view of a conventional semiconductor device, and FIG. 3(b) is a sectional view of the conventional semiconductor device. FIG. 3 is a sectional view taken along line A-A in FIG. 1... P type substrate, 2... N type epitaxial layer, 3... P type isolation diffusion layer, 4...
...Discrete P-type diffused resistance layer, 5...Conventional P
Type diffusion resistance layer, 6...Overlapping region, 7...
...Insulating film, 8...Contact hole, 9...
...electrode, IO...N-type diffusion layer. Agent Patent Attorney Oto Uchihara ('a,) Kiku/Diagram/ Kiku Otsul
Claims (1)
対導電型の拡散抵抗層を有する半導体装置において、前
記拡散抵抗層は、この拡散抵抗層形成の際の不純物拡散
における横方向拡散により隣り合う同士が互いに重なり
合うだけの所定間隔をおいて長さ方向に島状に離散した
形で形成されていることを特徴とする半導体装置。In a semiconductor device having a diffused resistance layer of an opposite conductivity type formed in a P-type or N-type semiconductor layer of one conductivity type, the diffused resistance layer is formed by lateral diffusion in impurity diffusion during formation of the diffused resistance layer. A semiconductor device characterized in that the semiconductor device is formed in the form of discrete islands in the length direction at predetermined intervals such that adjacent devices overlap each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6385088A JPH01235330A (en) | 1988-03-16 | 1988-03-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6385088A JPH01235330A (en) | 1988-03-16 | 1988-03-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01235330A true JPH01235330A (en) | 1989-09-20 |
Family
ID=13241219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6385088A Pending JPH01235330A (en) | 1988-03-16 | 1988-03-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01235330A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153117A (en) * | 1984-01-20 | 1985-08-12 | Matsushita Electronics Corp | Impurity diffusing method |
-
1988
- 1988-03-16 JP JP6385088A patent/JPH01235330A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153117A (en) * | 1984-01-20 | 1985-08-12 | Matsushita Electronics Corp | Impurity diffusing method |
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