JPS62179736A - Connecting terminal - Google Patents

Connecting terminal

Info

Publication number
JPS62179736A
JPS62179736A JP61023290A JP2329086A JPS62179736A JP S62179736 A JPS62179736 A JP S62179736A JP 61023290 A JP61023290 A JP 61023290A JP 2329086 A JP2329086 A JP 2329086A JP S62179736 A JPS62179736 A JP S62179736A
Authority
JP
Japan
Prior art keywords
connection
wiring
wirings
terminal
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61023290A
Other languages
Japanese (ja)
Inventor
Katsunori Hatanaka
勝則 畑中
Shunichi Uzawa
鵜澤　俊一
Katsumi Nakagawa
克己 中川
Toshiyuki Komatsu
利行 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP61023290A priority Critical patent/JPS62179736A/en
Publication of JPS62179736A publication Critical patent/JPS62179736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the yield of a connecting terminal in wiring steps by composing the terminal of a wiring connecting region and a preliminary wiring connecting region, first connecting the wirings of the wiring connecting region with external connection wirings and again connecting the wirings of the preliminary wiring connecting region with the external wirings. CONSTITUTION:A connecting terminal 1 is formed in a longitudinal shape, composed of a wiring connecting region A and a preliminary wiring connecting region B, and first connected from the region A of the terminal 1 with external connecting wirings 2 by leading wirings 3. The connecting method is, for example, a wire bonding method. When a malfunction of the connection occurs, the region B is again connected with the wirings 2 by leading wirings. In other words, the malfunction of the connection is recovered by rebonding the improper connection.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は接続端子に係り、特にチップ上に設けられた複
数個の接続端子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to connection terminals, and particularly to a plurality of connection terminals provided on a chip.

［従来技術］ ＩＣチップ等の電子回路チップの接続端子部は、素子の
高密度化に伴なって、接続端子数が増加しつつある。[Prior Art] The number of connection terminals in the connection terminal portion of an electronic circuit chip such as an IC chip is increasing as the density of elements increases.

第４図は従来の接続端子を有する電子回路チップの一例
を示す平面図である。FIG. 4 is a plan view showing an example of an electronic circuit chip having conventional connection terminals.

第４図において、半導体チップ８上の各辺には接続端子
７が並設されて設けられている。各接続端子７は略正方
形をしており、ワイヤポンディング等によって、外部接
続配線と接続される。In FIG. 4, connection terminals 7 are provided on each side of the semiconductor chip 8 in parallel. Each connection terminal 7 has a substantially square shape and is connected to external connection wiring by wire bonding or the like.

［発明が解決しようとする問題点］ しかしながら、上記の構成では一チップ上に設けられた
接続端子の一つでも接続不良があれば、チップ全体の不
良となってしまい、製造歩留が悪く、コストが高くなる
問題点があった。[Problems to be Solved by the Invention] However, in the above configuration, if there is a connection failure in even one of the connection terminals provided on one chip, the entire chip will be defective, resulting in poor manufacturing yield. There was a problem that the cost was high.

［問題点を解決するための手段］ 上記の問題点は、チップ上に設けられた複数個の接続端
子において、該接続端子を配線接続領域と予備配線接続
領域とから構成したことを特徴とする本発明の接続端子
によって解決される。[Means for Solving the Problem] The above problem is characterized in that, in a plurality of connection terminals provided on a chip, the connection terminal is composed of a wiring connection area and a preliminary wiring connection area. This problem is solved by the connecting terminal of the present invention.

［作用］ 本発明は、接続端子を配線接続領域と予備配線接続領域
とから構成し、まず配線接続領域と外部接続配線との間
で配線接続を行い、この接続が不良の場合に、予備配線
接続領域と外部接続配線との間で再度配線接続を行うも
のである。[Function] According to the present invention, a connection terminal is constructed of a wiring connection area and a preliminary wiring connection area, and a wiring connection is first made between the wiring connection area and an external connection wiring, and if this connection is defective, the preliminary wiring is This is to reconnect the wiring between the connection area and the external connection wiring.

［実施例］ 以下、本発明の実施例を図面を用いて詳細に説明する。[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図（ａ）は本発明による接続端子の一実施例を示す
平面図であり、第１図（ｂ）はそのｘ−ｘ　’縦断面図
である。FIG. 1(a) is a plan view showing an embodiment of a connecting terminal according to the present invention, and FIG. 1(b) is a longitudinal cross-sectional view taken along the line xx'.

第１図に示すように、接続端子１は長方形状をなし、配
線接続領域Ａと予備配線接続領域Ｂとからなる。まず、
接続端子１の配線接続領域Ａと外部接続配線２とが引き
出し配線３によって接続される。接続方法は例えば、ワ
イヤポンディング法によって行われる。接続不良が生じ
た場合は、予備配線接続領域Ｂと外部接続配線２との間
で再度引き出し配線によって接続を行う、すなわち本発
明の接続端子によれば、接続不良の箇所の再ポンディン
グを行うことにより再生を行うことができる。As shown in FIG. 1, the connection terminal 1 has a rectangular shape and consists of a wiring connection area A and a preliminary wiring connection area B. As shown in FIG. first,
The wiring connection area A of the connection terminal 1 and the external connection wiring 2 are connected by the lead wiring 3. The connection method is, for example, a wire bonding method. If a connection failure occurs, the connection is re-connected between the preliminary wiring connection area B and the external connection wiring 2 by lead wiring, that is, according to the connection terminal of the present invention, the connection failure point is re-ponded. This allows playback.

第２図は上記の接続端子を用いた電子回路チップの平面
図である。FIG. 2 is a plan view of an electronic circuit chip using the above connection terminals.

半導体チップ４上には、接続端子ｌが辺にそって並設さ
れている。On the semiconductor chip 4, connection terminals l are arranged in parallel along the sides.

第３図は上記の電子回路チップを用いたラインセンサの
斜視図である。FIG. 3 is a perspective view of a line sensor using the above electronic circuit chip.

第３図において、基板６上には光電変換素子等のセンサ
素子５が一列に配設されている。これらのセンサ素子５
は外部接続配線２を介して、増幅器、シフトレジスタ等
を搭載した半導体チップ４の接続端子ｌと接続されてい
る０本発明の接続端子はラインセンサ等のようにチップ
上の接続端子が多い場合には、各接続端子を再接続させ
ることができるので、歩留向上に特に有効である。In FIG. 3, sensor elements 5 such as photoelectric conversion elements are arranged in a row on a substrate 6. These sensor elements 5
is connected to the connection terminal l of the semiconductor chip 4 equipped with an amplifier, shift register, etc. via the external connection wiring 2.The connection terminal of the present invention is used when there are many connection terminals on the chip, such as in a line sensor, etc. Since each connection terminal can be reconnected, this method is particularly effective in improving yield.

［発明の効果］ 以上詳細に説明したように、本発明の接続端子によれば
、接続端子を配線接続領域と予備配線接続領域とから構
成し、まず配線接続領域と外部接続配線との間で配線接
続を行い、この接続が不良の場合に、予備配線接続領域
と外部接続配線との間で再度配線接続を行うことにより
、配線工程における歩留りを向上させ、低コストな電子
部品装置を提供するものである。[Effects of the Invention] As described above in detail, according to the connection terminal of the present invention, the connection terminal is composed of a wiring connection area and a preliminary wiring connection area, and first, the connection terminal is formed between the wiring connection area and the external connection wiring. To improve the yield in a wiring process and provide a low-cost electronic component device by making a wiring connection and, if the connection is defective, reconnecting the wiring between a preliminary wiring connection area and an external connection wiring. It is something.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による接続端子の一実施例の構造図であ
る。 第２図は上記の接続端子を用いた電子回路チップの平面
図である。 第３図は上記の電子回路チップを用いたラインセンサの
斜視図である。 第４図は従来の接続端子を有する電子回路チップの一例
を示す平面図である。 １．７・ｅ・・−・接続端子 ２・・・・・・外部接続配線 ３・・・争・Φ引き出し配線 ４．８・・・・の・半導体チップ ５・・・−拳・センサ素子 ６・・・働・・基板 代理人　　弁理士　山　下　積　子 弟　１　図 （ＣＩ） （ｂ） 第４図FIG. 1 is a structural diagram of an embodiment of a connecting terminal according to the present invention. FIG. 2 is a plan view of an electronic circuit chip using the above connection terminals. FIG. 3 is a perspective view of a line sensor using the above electronic circuit chip. FIG. 4 is a plan view showing an example of an electronic circuit chip having conventional connection terminals. 1.7・e・・・Connection terminal 2・・・External connection wiring 3・・φ Exit wiring 4.8・・・Semiconductor chip 5・・・Fist・Sensor element 6... Work... Substrate agent Patent attorney Seki Yamashita's son 1 Figure (CI) (b) Figure 4

Claims (1)

【特許請求の範囲】[Claims] チップ上に設けられた複数個の接続端子において、該接
続端子を配線接続領域と予備配線接続領域とから構成し
たことを特徴とする接続端子。A connection terminal comprising a plurality of connection terminals provided on a chip, the connection terminal comprising a wiring connection area and a preliminary wiring connection area.
JP61023290A 1986-02-04 1986-02-04 Connecting terminal Pending JPS62179736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61023290A JPS62179736A (en) 1986-02-04 1986-02-04 Connecting terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61023290A JPS62179736A (en) 1986-02-04 1986-02-04 Connecting terminal

Publications (1)

Publication Number Publication Date
JPS62179736A true JPS62179736A (en) 1987-08-06

Family

ID=12106469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61023290A Pending JPS62179736A (en) 1986-02-04 1986-02-04 Connecting terminal

Country Status (1)

Country Link
JP (1) JPS62179736A (en)

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