JPS6217777B2 - - Google Patents
Info
- Publication number
- JPS6217777B2 JPS6217777B2 JP54173791A JP17379179A JPS6217777B2 JP S6217777 B2 JPS6217777 B2 JP S6217777B2 JP 54173791 A JP54173791 A JP 54173791A JP 17379179 A JP17379179 A JP 17379179A JP S6217777 B2 JPS6217777 B2 JP S6217777B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output control
- microinstruction
- register
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17379179A JPS5697130A (en) | 1979-12-29 | 1979-12-29 | Input and output control processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17379179A JPS5697130A (en) | 1979-12-29 | 1979-12-29 | Input and output control processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5697130A JPS5697130A (en) | 1981-08-05 |
| JPS6217777B2 true JPS6217777B2 (index.php) | 1987-04-20 |
Family
ID=15967212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17379179A Granted JPS5697130A (en) | 1979-12-29 | 1979-12-29 | Input and output control processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5697130A (index.php) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04297640A (ja) * | 1991-03-26 | 1992-10-21 | Showa Denko Kk | 排水用溝等の勾配施工方法 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5945529A (ja) * | 1982-09-06 | 1984-03-14 | Nec Corp | 端末装置高速制御方式 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5179522A (ja) * | 1974-12-27 | 1976-07-10 | Nippon Electric Co | Nyushutsuryokuchanerusochi |
| JPS5624630A (en) * | 1979-08-06 | 1981-03-09 | Fujitsu Ltd | Plural input and output device control system |
-
1979
- 1979-12-29 JP JP17379179A patent/JPS5697130A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04297640A (ja) * | 1991-03-26 | 1992-10-21 | Showa Denko Kk | 排水用溝等の勾配施工方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5697130A (en) | 1981-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3898624A (en) | Data processing system with variable prefetch and replacement algorithms | |
| US5606520A (en) | Address generator with controllable modulo power of two addressing capability | |
| EP0102242B1 (en) | Data processing apparatus | |
| US5768609A (en) | Reduced area of crossbar and method of operation | |
| US5410649A (en) | Imaging computer system and network | |
| US3760369A (en) | Distributed microprogram control in an information handling system | |
| US3680058A (en) | Information processing system having free field storage for nested processes | |
| US3710349A (en) | Data transferring circuit arrangement for transferring data between memories of a computer system | |
| JPS58222363A (ja) | 共用メモリの割振装置 | |
| KR940011594B1 (ko) | 공유 제어 기억부를 가진 멀티프로세서 제어기 및 그 동기화 방법 | |
| US4837688A (en) | Multi-channel shared resource processor | |
| US5034879A (en) | Programmable data path width in a programmable unit having plural levels of subinstruction sets | |
| JPS6217777B2 (index.php) | ||
| US5687329A (en) | Information handling system including a data bus management unit, an address management unit for isolating processor buses from I/O and memory | |
| JP2680828B2 (ja) | ディジタル装置 | |
| JP2618223B2 (ja) | シングルチツプマイクロコンピユータ | |
| CA1119307A (en) | Microcomputer having separate bit and word accumulators and separate bit and word instruction sets | |
| EP0305752A2 (en) | Programmable data path width in a programmable unit having plural levels of subinstruction sets | |
| GB2138182A (en) | Digital processor | |
| JPS6226487B2 (index.php) | ||
| CA1103370A (en) | Microprocessor architecture with integrated interrupts and cycle steals prioritized channel | |
| JPS58114250A (ja) | 共有マイクロプロセツサ | |
| JPS5942331B2 (ja) | プロセツサソウチノセイギヨホウシキ | |
| EP0333235A2 (en) | Programmable data path width in a programmable unit having plural levels of subinstructions sets | |
| JPH01255037A (ja) | 電子計算機 |