JPS62177532A - Ecd driving circuit - Google Patents

Abstract

PURPOSE:To attain monolithic IC formation by connecting a collector and emitter to the output terminal side and the 2nd reference power supply respectively and providing the 3rd NPN transistor (TR) which is on/off controlled in synchronism with the 1st NPN TR. CONSTITUTION:When NPN TRs 25, 27 are turned off by a control signal SC1 and an NPN TR 26 is turned on by a control signal SC2, current is absorbed from an electrochromic display (ECD) on the output terminal 24 side into the earth through the TR 26, so that the ECD starts coloring operation. Since the TR 25 is used for delivering power supply current at the time of decoloration, a large current can be made to flow. Since the power supply current is drawn into the TR 27 side at the no load state of the ECD in case of decoloration, voltage boosting at the no load state can be suppressed at an extremely low level. Consequently, the monolithic IC formation of the ECD driving circuit can be easily attained.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention drives an ECD (electrochromic display) that displays information by utilizing the phenomenon of changes in color and light transmittance due to the application of voltage. The present invention relates to an EC drive circuit for. (Prior Art) Conventionally, there have been technologies in this field, such as those shown in FIGS. 2 and 3, for example. The configuration will be explained below.

FIG. 2 is a circuit diagram of a conventional ECU drive circuit.

This ECO drive circuit includes control terminals 1 and 2 to which control signals SCI and SG2 are respectively input, a power supply terminal 3 connected to a reference power source, and an output terminal 4 connected to an ECU (not shown). PNP l to terminals 1 to 4
- A transistor 5, an NPN h transistor and a resistor 7 are connected together. That is, PNP transistor 5
has its emitter connected to the power supply terminal 3, its collector connected to the output terminal 4, and its base connected to the control terminal l, and furthermore, a resistor 7 for leak prevention between the base of the transistor 5 and the rim. is connected. Also, NP
The Nl-transistor 6 has its collector connected to the output terminal 4, its emitter connected to the ground, and its base connected to the control terminal 2.

In the above configuration, the ECDCD special color control signal SCI
The output PNP transistor 5 is turned off, and the control signal SC2 turns on the pull-in NPN transistor 6. Then, the ECU connected to the output terminal 4 becomes ground potential, and the ECD becomes colored. When decoloring, conversely, the PNP transistor 5 is turned on and the NPN transistor 6 is turned off. As a result, the output terminal 4 side becomes the power supply voltage, and the ECO color disappears.

Although the circuit operation of this ECD drive circuit is a very general complementary output, the output current in such an ECD drive circuit is usually large.

Generally 100! Current inside and outside the IA is required. Therefore, when this type of ECD drive circuit is made into a monolithic IC, the PNP transistor 5 generally has a lateral structure, so the current amplification factor is low, and it is extremely difficult to realize a current output of about 100 mA. Suna, bchi, PN
Since the current amplification factor of the P transistor 5 is low, there is a risk that the internal current consumption will increase and the pattern in the 3JfPNP transistor 5 will become huge. Therefore, a circuit configuration as shown in FIG. 3 has been proposed as an EcD drive circuit suitable for monolithic IC.

The ECD drive circuit of FIG. 3 has a configuration in which the PHρ transistor 5 in FIG. 2 is replaced with an NPN transistor 15. In this circuit, NPN transistor 15
This makes it possible to improve the current amplification factor.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

It is extremely difficult to implement the ECD drive circuit shown in FIG. 2 as an IC. On the other hand, in the EcD drive circuit shown in Fig. 3, I
It is possible to realize a C conversion, but since the sending circuit is the emitter output of the NPN transistor 15, there is an EC
When a capacitive load like D is connected, an inrush current flows initially, and when charging is finished, no current flows.

In other words, as shown in Figure 4, which shows the current-voltage characteristics of the emitter output circuit of an NPN transistor, when a capacitive load is connected to the output terminal 4, the current trajectory starts from point a where the sending current is flowing, and the current decreases. After passing through point S where the current flows, the current changes to point C where the current does not flow. Furthermore, the life of the ECD becomes significantly shorter as the applied voltage increases, and the applied voltage range is also considerably narrower. Therefore, when the circuit shown in FIG. 3 is used, there is a problem that the voltage change between the time when the current is flowing and the time when the current is no longer flowing becomes a large value of about 0.7 to 1 V.

The present invention solves the second problem of the prior art.
EG solves the problem of the difficulty of making a monolithic IC in the one in the figure, and the large voltage change between when the sending potential is flowing and when it is no longer flowing in the one in Figure 3.
This provides an O drive circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an EGO drive circuit including at least 51 NPN transistors whose collectors are connected to a first reference power supply and whose emitters are connected to an output terminal. a second NPN transistor whose collector is connected to the output terminal and whose emitter is connected to the second reference power source; and a third NPN transistor whose collector is connected to the output terminal side and whose emitter is connected to the second reference power source. It is composed of transistors. Here, the first and third N
The PN l-transistor and the second transistor are controlled to be turned on and off in a complementary manner.

(Function) According to the present invention, since the ECD drive circuit is configured as described above, the first NPN l-transistor can send out a large current, and the third NPN l-ransistor can send out the current. It works to suppress voltage rise by sucking current when the switch is off.

Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of an ECD drive circuit showing an embodiment of the present invention.

This ECD drive circuit includes control terminals 20 and 21 to which the control signal SGI is input, a control terminal 22 to which the control signal SC2 is input, a power supply terminal 23 connected to the first S quasi-power supply, and an ECD drive circuit (not shown). Output terminal 2 connected to
4, and the first. Second
．． A third NPN transistor 25, 26.27 and a resistor 28.29 are connected.

That is, the first NPN transistor 25 has its collector connected to the power supply terminal 23 and its emitter connected to the output terminal 24.
The bases of the transistors 25 are connected to the control terminal 20, and a leakage prevention resistor 28 is connected between the base and emitter of the transistor 25.

The second NPN transistor 26 has its collector connected to the output terminal 24, its emitter connected to a second reference power supply, eg, ground, and its base connected to the control terminal 22. Further, the third NPN transistor 27 has its collector connected to the output terminal 2 through a current limiting resistor 28.
4, its collector is connected to the ground, and its base is connected to control terminal 2.
1, respectively.

Next, the operation will be explained.

(1) NPN transistors 25, 2 by control signal 53SC1 when decoloring EC[l
7 on! '+, and the NPN l transistor 26 is turned off by the control signal SC2. Then, a power supply current flows from the power supply terminal 23 to the output terminal 24,
EGD connected to the output terminal 24 is decolored. At this time, since the ECD is a capacitive load, when the load becomes a no-load state, the power supply current is drawn to the ground side through the resistor 29 and the NPN transistor 27. Then, the operating point becomes the point shown in FIG. In addition, the ECD is in the no-load state 7
It is necessary to select the value of the resistor 28 in advance so that the operating point is at the point (g).

(2) NPN transistor 25.27 by ECU coloring control signal SCI
is turned off, and the control signal SC2 turns NP into y.
N Turn on transistor 26. Then, a current is sucked from the ECD on the output terminal 24 side to the ground through the NPN transistor 26, so that the EGD shifts to a coloring operation.

The advantages of this embodiment are as follows. Since the NPN h range meter 25 is used to send out the power supply current during erasing, it is possible to flow a large current. Moreover,
When the EGO is in a no-load state during color erasure, the power supply current is drawn to the transistor 27 side, so that the voltage increase during the no-load state can be suppressed to an extremely low level. Therefore, it is possible to easily implement the ECD drive circuit into a monolithic IC.

The present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) NPN transistor 27 and resistor 29 in FIG.
Even if a switchable sink type constant current stage is used instead of zero, the same advantages as in the above embodiment can be obtained.

(ii) Instead of the feeding NPN25 in Figure 1,
For example, a Darlington circuit with two stages of NPN transistors having a large current capacity may be used. In this case, the voltage change between no-load and load becomes sharper by the base-emitter voltage of the added NPN transistor, but
Since the NPN transistor 27, resistor 29, etc. of the suction river are provided, the voltage change is suppressed.

(Effects of the Invention) As described above in detail, according to the present invention, the first NPN transistor is used for sending out current, and the third NPN transistor is used to draw current in the no-load state at the time of sending out current. Therefore, it is possible to increase the radio wave capacity and suppress the voltage rise during no-load, and it is possible to easily implement the ECD drive circuit into a monolithic IC.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an ECD drive circuit showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a conventional Eco drive circuit,
FIG. 4 is an emitter output characteristic diagram of an NPN transistor for explaining the operation of a conventional EcD drive circuit. 20.21.22... Control terminal, 23 Old...
Power terminal, 24...Output terminal -, 25, 2J2
7... 1st. Second. Third NPN transistor. Applicant's representative: Takashi Kakimoto, EC of Seigyu Research
D drive initial circuit Figure 1 Conventional 0ECD drive 17] Four routes Figure 2 Future (7) ECD drive recess voltage drop () Figure 4

Claims (1)

[Scope of Claims] A first NPN transistor having a collector connected to a first reference power supply and an emitter connected to an output terminal; a first NPN transistor having a collector connected to the output terminal and an emitter connected to a second reference power supply; a second NPN transistor that is controlled to be turned on and off in a complementary manner to the first NPN transistor; An ECD drive circuit including a third NPN transistor that is synchronously controlled to turn on and off.