JP3049712B2 - Gain control amplifier circuit - Google Patents
Gain control amplifier circuitInfo
- Publication number
- JP3049712B2 JP3049712B2 JP1191755A JP19175589A JP3049712B2 JP 3049712 B2 JP3049712 B2 JP 3049712B2 JP 1191755 A JP1191755 A JP 1191755A JP 19175589 A JP19175589 A JP 19175589A JP 3049712 B2 JP3049712 B2 JP 3049712B2
- Authority
- JP
- Japan
- Prior art keywords
- gain control
- current
- transistor
- circuit
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は利得制御増幅回路に関する。Description: TECHNICAL FIELD The present invention relates to a gain control amplifier circuit.
従来、この種の増幅回路としては第2図に示す回路が
知られている。第2図の動作を説明すると、トランジス
タQ1,Q2で構成される差動回路の出力電流IC2が負荷抵抗
R3に流れる量をトランジスタQ3,Q4の差動回路で制御し
て入力端子1からみた出力端子6の利得を変化させてい
る。利得の制御は電源10,11の電圧差を抵抗R5,R6で電流
に変換し、その電流をダイオードD1,D2で電圧に変換し
て差動回路を構成するトランジスタQ3,Q4のベースに供
給することで、電源11の変化を利得の変化にしている。Conventionally, a circuit shown in FIG. 2 has been known as this kind of amplifier circuit. The operation of FIG. 2 will be described. The output current I C2 of the differential circuit composed of the transistors Q 1 and Q 2 is the load resistance
And the amount flowing to R 3 by changing the gain of the transistor Q 3, Q output terminal 6 which is controlled to viewed from the input terminal 1 in the differential circuit 4. The gain is controlled by converting the voltage difference between the power supplies 10 and 11 into current with the resistors R 5 and R 6 , and converting the current into voltage with the diodes D 1 and D 2 to form transistors Q 3 and Q By supplying the power to the base 4 , the change of the power supply 11 is changed to the change of the gain.
上述した従来の利得制御増幅回路では,利得を上げる
と負荷抵抗R3に流れる電流IC4が多くなるため、R3の電
圧降下が大きくなり、出力信号の動作電位が下がるた
め、電源電圧が低いとトランジスタQ4のコレクターエミ
ッタ間電圧VCEが確保できなくなり、出力信号が負方向
に振れなくなるという欠点がある。In the conventional gain control amplifier circuit described above, when the gain is increased, the current I C4 flowing through the load resistor R 3 increases, so that the voltage drop of R 3 increases and the operating potential of the output signal decreases, so that the power supply voltage is low. the collector-emitter voltage V CE of the transistor Q 4 is can not be secured, there is a disadvantage that the output signal can not swing in a negative direction.
本発明の目的は、電源電圧が低い場合に利得をあげて
も出力振幅が大きくとれることが可能な利得制御増幅回
路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a gain control amplifier circuit capable of obtaining a large output amplitude even when the gain is increased when the power supply voltage is low.
本発明の利得制御増幅回路は、差動型式に接続された
第1及び第2のトランジスタと、これら第1及び第2の
トランジスタのエミッタ結合点に入力信号電流を供給す
る回路と、前記第1のトランジスタのコレクタと電源と
の間に接続された負荷と、前記第1及び第2のトランジ
スタのベース間に利得制御電圧を供給する回路と、前記
利得制御電圧の変化によって前記負荷に流れる電流が増
加するとき前記利得制御電圧に応じた電流を前記第1の
トランジスタのコレクタに供給し前記第1のトランジス
タのコレクタに流れる電流を増加させる回路とを有する
ことを特徴としている。The gain control amplifier circuit according to the present invention includes a first and a second transistor connected in a differential manner, a circuit for supplying an input signal current to an emitter coupling point of the first and the second transistor, A load connected between the collector of the transistor and a power supply, a circuit for supplying a gain control voltage between the bases of the first and second transistors, and a current flowing through the load due to a change in the gain control voltage. A circuit for supplying a current corresponding to the gain control voltage to the collector of the first transistor when increasing the current, and increasing the current flowing to the collector of the first transistor.
次に、本発明について図面を参照して説明する。第1
図は本発明の一実施例を説明するための回路図であり、
第2図で説明した従来例にトランジスタQ8,Q9からなる
カレントミラー回路,トランジスタQ10,Q11からなる差
動回路及び定電流幅5を追加したものである。Next, the present invention will be described with reference to the drawings. First
The figure is a circuit diagram for explaining an embodiment of the present invention,
A current mirror circuit including transistors Q 8 and Q 9 , a differential circuit including transistors Q 10 and Q 11 and a constant current width 5 are added to the conventional example described with reference to FIG.
追加回路の動作としては、トランジスタQ10,Q11で構
成される差動回路のベースをトランジスタQ3,Q4のベー
スに接続することでトランジスタQ3,Q4のコレクタ電流I
C3,IC4の比を検出し、トランジスタQ10のコレクタ電流
をカレントミラー回路を構成するQ8,Q9によりトランジ
スタQ4のコレクタに電流iを流し込むことにより、R3の
電圧降下を減少させている。ここで定電流源2と5の電
流値I1,I4を電源電圧、出力振幅を考慮した適正な値に
設定すれば、出力振幅を大きくとることができる。The operation of the additional circuitry, the transistors Q 10, based on the transistor Q of the differential circuit composed of Q 11 3, Q 4 of the transistor Q 3 by connecting to the base, Q 4 of the collector current I
C3, detects the ratio of I C4, by pouring a current i to the collector of the transistor Q 4 by Q 8, Q 9 constituting the current mirror circuit the collector currents of the transistors Q 10, decreases the voltage drop across R 3 ing. If the current values I 1 and I 4 of the constant current sources 2 and 5 are set to appropriate values in consideration of the power supply voltage and the output amplitude, the output amplitude can be increased.
以上説明したように本発明は、利得に応じて負荷に流
れる電流を変化させ利得を大きくした場合でも負荷によ
り生じる電圧降下を減少することができるため、電源電
圧が低い時でも、充分大きい出力振幅を得ることが可能
となる。As described above, the present invention can reduce the voltage drop caused by the load even when the current flowing to the load is changed according to the gain to increase the gain, so that even when the power supply voltage is low, the output amplitude is sufficiently large. Can be obtained.
第1図は本発明の一実施例を説明するための回路図、第
2図は従来の利得制御増幅回路を説明するための回路図
である。 1……入力端子、2〜5……定電流源、6……出力端
子、7……高位側電源端子、8……定位側電源端子、Q1
〜Q11……トランジスタ、R1〜R6……抵抗。FIG. 1 is a circuit diagram for explaining an embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining a conventional gain control amplifier circuit. 1 input terminal, 2 to 5 constant current source, 6 output terminal, 7 higher power supply terminal, 8 localization power supply terminal, Q 1
QQ 11 …… Transistor, R 1 RR 6 …… Resistance.
Claims (1)
ンジスタと、これら第1及び第2のトランジスタのエミ
ッタ結合点に入力信号電流を供給する回路と、前記第1
のトランジスタのコレクタと電源との間に接続された負
荷と、前記第1及び第2のトランジスタのベース間に利
得制御電圧を供給する回路と、前記利得制御電圧の変化
によって前記負荷に流れる電流が増加するとき前記利得
制御電圧に応じた電流を前記第1のトランジスタのコレ
クタに供給し前記第1のトランジスタのコレクタに流れ
る電流を増加させる回路とを有することを特徴とする利
得制御増幅回路。A first and second transistor connected in a differential manner, a circuit for supplying an input signal current to an emitter junction of the first and second transistors,
A load connected between the collector of the transistor and a power supply, a circuit for supplying a gain control voltage between the bases of the first and second transistors, and a current flowing through the load due to a change in the gain control voltage. A circuit for supplying a current corresponding to the gain control voltage to the collector of the first transistor when increasing the current, and increasing the current flowing to the collector of the first transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1191755A JP3049712B2 (en) | 1989-07-24 | 1989-07-24 | Gain control amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1191755A JP3049712B2 (en) | 1989-07-24 | 1989-07-24 | Gain control amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0355908A JPH0355908A (en) | 1991-03-11 |
JP3049712B2 true JP3049712B2 (en) | 2000-06-05 |
Family
ID=16279967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1191755A Expired - Lifetime JP3049712B2 (en) | 1989-07-24 | 1989-07-24 | Gain control amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3049712B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0437209A (en) * | 1990-05-31 | 1992-02-07 | Nec Home Electron Ltd | Gain control driving circuit |
JP5420182B2 (en) | 2008-03-14 | 2014-02-19 | 富士通セミコンダクター株式会社 | Cache memory system, data processing device, and storage device |
-
1989
- 1989-07-24 JP JP1191755A patent/JP3049712B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0355908A (en) | 1991-03-11 |
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