JPS62177127U - - Google Patents
Info
- Publication number
- JPS62177127U JPS62177127U JP6452786U JP6452786U JPS62177127U JP S62177127 U JPS62177127 U JP S62177127U JP 6452786 U JP6452786 U JP 6452786U JP 6452786 U JP6452786 U JP 6452786U JP S62177127 U JPS62177127 U JP S62177127U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- output
- terminal
- input terminal
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の動作を説明するためのタイミン
グチヤート、第３図および第４図はそれぞれ本考
案の他の実施例を示す説明図、第５図は従来の装
置の一例を示すブロツク図、第６図は第５図の動
作を説明するためのタイミングチヤートである。
１……データ発生器、２，７……Ｄ形フリツプ
フロツプ、３……メモリ、４……クロツク発振器
、ＤＢ……データバス。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIGS. 3 and 4 are explanatory diagrams showing other embodiments of the present invention, and FIG. 5 is a block diagram showing an example of a conventional device. FIG. 6 is a timing chart for explaining the operation of FIG. 5. 1...Data generator, 2, 7...D flip-flop, 3...Memory, 4...Clock oscillator, DB...Data bus.
Claims (1)
子に並列に加えられ、上位の一方の出力端子が順
次下位のＤ入力端子に接続されて最下位の他方の
出力端子が最上位のＤ入力端子に接続された複数
のＤ形フリツプフロツプを具備し、 これら各Ｄ形フリツプフロツプの各出力端子か
ら複数系統にクロツクに関連した信号を分配供給
することを特徴とする多相クロツク分配回路。[Claims for Utility Model Registration] A clock oscillator and an output clock of the clock oscillator are applied to each clock terminal in parallel, and one output terminal of the higher order is connected to the D input terminal of the lower order, and the output of the other lowest one is connected in turn to the lower D input terminal. A polyphase circuit comprising a plurality of D-type flip-flops whose terminals are connected to the highest-order D input terminal, and which distributes and supplies clock-related signals to multiple systems from each output terminal of each of these D-type flip-flops. Clock distribution circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6452786U JPS62177127U (en) | 1986-04-28 | 1986-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6452786U JPS62177127U (en) | 1986-04-28 | 1986-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177127U true JPS62177127U (en) | 1987-11-10 |
Family
ID=30900765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6452786U Pending JPS62177127U (en) | 1986-04-28 | 1986-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177127U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173921A (en) * | 1984-02-20 | 1985-09-07 | Toshiba Corp | Pulse generator |
| JPS61131612A (en) * | 1984-11-29 | 1986-06-19 | Fujitsu Ltd | Clock pulse generating circuit |
-
1986
- 1986-04-28 JP JP6452786U patent/JPS62177127U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173921A (en) * | 1984-02-20 | 1985-09-07 | Toshiba Corp | Pulse generator |
| JPS61131612A (en) * | 1984-11-29 | 1986-06-19 | Fujitsu Ltd | Clock pulse generating circuit |
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