JPS62176150A - Structure of ic mounting substrate - Google Patents

Structure of ic mounting substrate

Info

Publication number
JPS62176150A
JPS62176150A JP61018677A JP1867786A JPS62176150A JP S62176150 A JPS62176150 A JP S62176150A JP 61018677 A JP61018677 A JP 61018677A JP 1867786 A JP1867786 A JP 1867786A JP S62176150 A JPS62176150 A JP S62176150A
Authority
JP
Japan
Prior art keywords
mounting
guide
circuit board
wire bonding
circuit substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61018677A
Other languages
Japanese (ja)
Inventor
Hitoshi Hasegawa
仁志 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61018677A priority Critical patent/JPS62176150A/en
Publication of JPS62176150A publication Critical patent/JPS62176150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To improve the yield rate in IC mounting, to operate a wire bonding machine efficiently and to improve the level of IC mounting quality, by providing a guide in an IC spot-facing hole in a circuit substrate so that the IC is not moved. CONSTITUTION:An IC guide 5 is provided in an IC spot-facing part in a circuit substrate 1. An IC 2 is die-attached in the inside of the guide with a bonding agent. The circuit substrate and the IC are connected by using a wire bonding machine. Finally, the device is sealed with a molding agent 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣ実装の基板構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a substrate structure for IC mounting.

〔発明の概要〕[Summary of the invention]

本発明は、ＩＣ実装の基板構造において、ワイヤーボン
ディングでＩＣを実装する回路基板のＩＣザグリ穴にＩ
Ｃガイドを設け、工○を動かないようにすることにより
、ＩＣ実装の歩留りアップ、ワイヤーボンディングマシ
ンの効率的な稼動、さらには、ＩＣ実装品質のレベルア
ップをはかつたものである。In the substrate structure for IC mounting, the present invention provides an I
By providing a C guide and preventing the workpiece from moving, the yield of IC mounting is increased, the wire bonding machine is operated efficiently, and the quality of IC mounting is improved.

〔従来技術〕[Prior art]

従来のＩＣ実装の基板構造は、＃！３図の様に、回路基
板１にＩＣ１を接着剤でダイアタッチし、ワイヤーボン
ディングマシンを用いてボンディングワイヤー３で回路
基板とＩＣを接続して、最後にモールド剤４で封止した
構造であった。The conventional board structure for IC mounting is #! As shown in Figure 3, the IC 1 is die-attached to the circuit board 1 using an adhesive, the circuit board and the IC are connected using a bonding wire 3 using a wire bonding machine, and finally the IC is sealed with a molding agent 4. Ta.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前述の従来技術では、ＩＣを接着剤でダイアタ
ッチするときに、ＩＣが固定されず動いてしまうという
問題点を有する。そこで本発明はこのような問題点を解
決するもので、その目的とするところは、ＩＣ実装の歩
留りアップ、ワイヤーボンディングマシンの効率的な稼
動、ＩＣ実装品質のレベルアップを提供するところにあ
る。However, the above-mentioned conventional technology has a problem in that when the IC is die-attached using an adhesive, the IC is not fixed and moves. The present invention is intended to solve these problems, and its purpose is to improve the yield of IC mounting, efficiently operate a wire bonding machine, and improve the quality of IC mounting.

〔問題を解決するための手段〕[Means to solve the problem]

ＩＣ実装の基板構造において、回路基板ＩＣザグリ穴に
ＩＣガイドを設け、ＩＣが動かないようにしたことを特
徴とする特 〔実施例〕 第１図は本発明の基板構造の断面図であって、回路基板
１のＩＣザグリ部にＩＣガイド５を設は前記ＩＣガイド
内側にＩＣ２を接着剤でダイアタッチし、ワイヤーボン
ディングマシンを用≠てボンディング与イヤー３で回路
基板とＩＣを接続して、最後にモールド剤４で封止した
構造である。In the board structure for IC mounting, an IC guide is provided in the counterbore hole of the circuit board IC to prevent the IC from moving [Embodiment] FIG. 1 is a sectional view of the board structure of the present invention. , an IC guide 5 is installed in the IC counterbore part of the circuit board 1, an IC 2 is die-attached to the inside of the IC guide with adhesive, and the circuit board and the IC are connected with a bonding ear 3 using a wire bonding machine. The structure is finally sealed with molding agent 4.

尚、ここに挙げた実施例はあくまでも一実施例にすぎな
いものである。It should be noted that the embodiments listed here are merely examples.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、回路基板ＩＣザグリ
部にＩＣガイドを設けることにより、ＩＣダイアタッチ
のときにＩＣが動くことがなく、ＩＣ実装の歩留りアッ
プ、ワイヤーボンディングマシンの効率的稼動、さらに
ＩＣ実装品質のレベルアップができるという効果を有す
る。As described above, according to the present invention, by providing an IC guide in the IC counterbore portion of the circuit board, the IC does not move during IC die attachment, thereby increasing the yield of IC mounting and efficiently operating the wire bonding machine. Furthermore, it has the effect of improving the quality of IC mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のＩＣ実装の回路基板構造の一実施例を
示す主要断面図。 第２図は第１図の平面図。 第３図は従来のＩＣ実装の回路基板構造を示す主要断面
図。 １・・・・・・回路基板 ２　・・・・・・　工　　　０ ３・・・・・・ボンディングワイヤー ４・・・・・・モールド剤 ５・・・・・・ＩＣガイド ６・・・・・・回路パターン ７・・・・・・ＩＣザグリ部 以上FIG. 1 is a main sectional view showing an embodiment of the IC-mounted circuit board structure of the present invention. FIG. 2 is a plan view of FIG. 1. FIG. 3 is a main cross-sectional view showing the structure of a conventional IC mounting circuit board. 1... Circuit board 2... Engineering 0 3... Bonding wire 4... Molding agent 5... IC guide 6...・・Circuit pattern 7・・・・IC counterbore part or above

Claims (1)

【特許請求の範囲】[Claims] 　ＩＣ実装の基板構造において、回路基板ＩＣザグリ穴
にＩＣガイドを設け、ＩＣが動かないようにしたことを
特徴とするＩＣ実装の基板構造。A board structure for IC mounting, characterized in that an IC guide is provided in a counterbore hole of a circuit board IC to prevent the IC from moving.
JP61018677A 1986-01-30 1986-01-30 Structure of ic mounting substrate Pending JPS62176150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61018677A JPS62176150A (en) 1986-01-30 1986-01-30 Structure of ic mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61018677A JPS62176150A (en) 1986-01-30 1986-01-30 Structure of ic mounting substrate

Publications (1)

Publication Number Publication Date
JPS62176150A true JPS62176150A (en) 1987-08-01

Family

ID=11978237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61018677A Pending JPS62176150A (en) 1986-01-30 1986-01-30 Structure of ic mounting substrate

Country Status (1)

Country Link
JP (1) JPS62176150A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736792A (en) * 1995-08-30 1998-04-07 Texas Instruments Incorporated Method of protecting bond wires during molding and handling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736792A (en) * 1995-08-30 1998-04-07 Texas Instruments Incorporated Method of protecting bond wires during molding and handling

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