JPS62175041A - Block transfer system - Google Patents

Abstract

PURPOSE:To avoid very simply a case that an end horizontal checking character comes to be wholly 0 and to decrease hardly the transferring speed for the checking effect by constituting all characters between the block of the data transfer and the block of all 0 bits. CONSTITUTION:A circuit GE 16 and a circuit GF 17 are added and the OR circuits of 8 bits of a circuit GD 15 are respectively changed from a 2-input to a 3-input. When a parity bit from a circuit GC 14 is wholly 0, an output 1 from the circuit GE 16 is given through the circuit GE 17 to the circuit DG 15 and all bits of the parity character are converted to 1. When all bits of the horizontal checking character come to be 0, it can be though that the probability to generate the error is very little in which all bits of the horizontals checking character come to be 1. Thus, even when checking is not executed by the above-mentioned means, the effect of the parity checking is hardly damaged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a block transfer method, particularly a block transfer method for transferring a block composed of a plurality of characters with all 10'' bits between blocks.

[Conventional technology]

Traditionally, block transfer methods have often been used to transfer information within or between information processing systems.
At this time, all characters before and after the transfer block are “O#”
The focus is set so that each character to be transferred does not contain any 0" bits. In addition, horizontal parity checks are often performed to prevent errors in the transferred content, and by chance the horizontal check character is all '0' bits, in order to clarify whether it is a transfer block or an outside block, a character indicating the number of transfer characters should be provided at the beginning of the transfer block, or if the character is made up of 8 bits, for example. If so, those 7 bits are used as a character indicating the number of transferred characters, and when 1 bit of the horizontal check character corresponding to the remaining 1 bit also becomes 10'', both 1 bits are set to 1.
11.

[Problem that the invention seeks to solve]

However, in the conventional block transfer method that performs horizontal parity check, it is necessary to add a character indicating the number of characters that is not necessarily required to the transfer information, or it is necessary to add a horizontal parity character and then manipulate the character indicating the number of characters. However, there are problems in that it requires processing time before transfer, and furthermore, the transfer block length is limited by the number of bits of a character indicating the number of characters.

The purpose of the present invention is to eliminate the above-mentioned problems, and when all the bits of the horizontal check character at the end are 0, all the bits of this character are set to '1#, so that the It is an object of the present invention to provide a block transfer method which can easily perform processing and obtain the effect of parity check without being restricted by the transfer block length.

[Means for solving problems]

The present invention has a horizontal check character at the end, and all characters between blocks are set to ``0''.
In a block transfer method in which the block does not contain all 60# bit characters, when all horizontal check characters before transfer become 0# bits, the horizontal check character is inverted to all 60# bits. The parity addition means and the receiving side accept the received block as is.
a first horizontal parity check means for checking; a second horizontal parity check means for checking all bits as "O" when all bits of the received horizontal check character are "1"; The second horizontal parity check means is configured to include a determining means for determining that there is no error when some of the horizontal parity check means detects that there is no error.

In such a block transfer, when all the bits of the horizontal check character become 0'', it is considered that the probability of occurrence of an error in which all the bits of the horizontal check character become 1' is extremely small, so the above Even if the check is performed by the above means, the effectiveness of the parity check is hardly impaired.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the horizontal parity adding circuit of the present invention, and shows characters G to B.

The figure shows an 8-bit configuration up to 8 bits. In the figure, the first gate (hereinafter referred to as GA) opens each gate of an 8-bit parallel character when an input gate signal is applied.
11, and a second sampling signal that samples each of the 8-bit outputs of the GALL with a sampling signal synchronized with the transfer rate.
A gate circuit (hereinafter referred to as CB) 12, a register (hereinafter referred to as RA) 13 that adds each of the 8-bit outputs of GB12 modulo 2 and stores the result, and a register (hereinafter referred to as RA) 13 that stores the result, and a A third gate circuit (hereinafter referred to as GC) 14 reads the contents of the bits, and a fourth gate circuit (hereinafter referred to as GC) 14 which calculates the logical sum of the 8-bit output from GC 14 and the 8-bit output from GAII and outputs the result.
A fifth gate circuit (hereinafter referred to as GE) 16 which performs the OR of the 8-bit output of the GC 14 and outputs an inverted signal thereof; A sixth gate circuit (hereinafter referred to as CF) 17 is shown which applies this signal to each of the GDs and performs a logical sum.

The above circuit configuration differs from the conventionally used horizontal parity addition circuit in that GE16 and GF17 are added, and each of the 8-bit OR circuits in GD15 is
In Figure 1, GC
When all the parity bits from GE14 are 10", the output "l# from GE16 is sent to DG15 via GF17.
and set all bits of the parity character to ′1
” Convert to ”.

FIG. 2 is a block diagram of one embodiment of the horizontal parity check circuit of the present invention, and shows the case of an 8-bit configuration from characters g to b8, as in FIG. 1. In the figure, there is a first gate circuit (hereinafter referred to as GG) 21 that can logically OR each of the parallel 8 bits of the input character to set all input bits to '1', and this GG21.
A register (hereinafter referred to as RB) 22 that stores the result by adding modulo 2 each of the 8-bit outputs of the RB 22 and the first check pulse is ANDed with each of the 8-bit inverted outputs of this RB 22 Second gate circuit (hereinafter G
H) 23, a third gate circuit (hereinafter referred to as GJ) 24 that inverts the output of GH23, the output of this GJ24, and the second check pulse, and this output is applied to the above-mentioned GG2.
4th as each other input of the 8-bit OR
A gate circuit (hereinafter referred to as GK) 25 is shown.

The above circuit configuration differs from the conventionally used horizontal parity check circuit in that GG21, GJ24, and GK25 are provided and the second check pulse is used. If the check output 11'' is not obtained from the GA23 by applying the pulse, a second check pulse is applied and a 1 is given to each bit of the RB22 via the GG21, and the check output 11'' is again output from the GH23. is not obtained.

If this operation inverts the horizontal parity characters that were all O''' to 1'' and transfers them, this means that the horizontal parity characters are returned to "O" and a horizontal parity check is performed.

Although the embodiments shown in FIGS. 11 and 2 above have shown cases in which the means of the present invention are configured by logic circuits, it is also extremely easy to configure them by conventional program control.

Furthermore, although the above embodiments have been described in the case of parallel transfer, it is clear that the present invention can also be applied to the case of serial transfer by adding a synchronization bit to the beginning of the transfer block.

〔Effect of the invention〕

As explained in detail above, the present invention sets all characters between blocks of data transfer to "0".
In a block transfer method that consists of bits and does not contain any NOPI bit characters in the block,
It is possible to avoid the case where all the horizontal check characters at the end are '0#' in an extremely simple way, and there is also the effect that the check effect and transfer speed are hardly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the horizontal parity adding circuit of the present invention, and FIG. 2 is a block diagram of an embodiment of the horizontal parity check circuit of the present invention. 11.12,14,15,16.17,21,23,2
4.25...Gate circuit (GA, GB,
GC, GD, GE, CF, GG. GH, GJ, GK), 13.22...Register (RA, R town. Line f Figure line Do 〆

Claims (1)

[Claims] Transfer in a block transfer method that has a horizontal check character at the end, all characters between blocks are composed of all “0” bits, and no characters in the block are all “0” bits. horizontal parity adding means for inverting all the previous horizontal check characters to "1" bits when all of them become "0"bits; and first horizontal parity checking means for checking the received block as is. , a second horizontal parity check means that checks all bits of the received horizontal check character as "0" when all the bits are "1", and either of the first and second horizontal parity check means. 1. A block transfer method characterized by comprising a determining means for determining that there is no error when it is detected that there is no error.