JPS62173779A - Optical integrated circuit device - Google Patents

Optical integrated circuit device

Info

Publication number
JPS62173779A
JPS62173779A JP1510786A JP1510786A JPS62173779A JP S62173779 A JPS62173779 A JP S62173779A JP 1510786 A JP1510786 A JP 1510786A JP 1510786 A JP1510786 A JP 1510786A JP S62173779 A JPS62173779 A JP S62173779A
Authority
JP
Japan
Prior art keywords
layer
recess
substrate
integrated circuit
optical integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1510786A
Other languages
Japanese (ja)
Inventor
Shinichi Takigawa
信一 瀧川
Kunio Ito
国雄 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1510786A priority Critical patent/JPS62173779A/en
Publication of JPS62173779A publication Critical patent/JPS62173779A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To alleviate an adverse influence of a dislocation or a defect in a substrate to a laser by forming a recess at a position of the substrate to form the laser, and burying the recess with a conductive GaAs to form a buffer layer. CONSTITUTION:A recess is formed on a semi-insulating substrate 1, and the recess is buried with a P-type GaAs by an epitaxially growing method to form a buffer layer 2. The layer 2 alleviates an adverse influence of a dislocation or a defect in the substrate 1 to the layer units 2-8. The alleviating effect can be increased by deepening the recess. many FETs 20 are composed on the substrate 1 in addition to the lasers 2-8. In this case, the lasers 2-8 and the FETs 20 are formed on the same surface irrespective of the depth of the recess. Accordingly, a problem of wiring stepwise difference due to the increased thickness of the buffer layer does not occur.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、光通信における発光源等、入力電気信号によ
って、光出力を変化させる光集積回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an optical integrated circuit, such as a light emitting source in optical communication, which changes its optical output depending on an input electrical signal.

従来の技術 いわゆるBTR8型半導体レーザは、侵れた性能、高い
信頼性を持つことが知られている。そこで、導電性G 
a A s基板上にこのBTR8型半導体レーザとFE
Tを集積した光集積回路装置をすでに本出願人が提案し
た。
BACKGROUND OF THE INVENTION The so-called BTR8 type semiconductor laser is known to have excellent performance and high reliability. Therefore, conductive G
a This BTR8 type semiconductor laser and FE are mounted on the A s substrate.
The present applicant has already proposed an optical integrated circuit device that integrates T.

発明が解決しようとする問題点 しかし、FETが多数、導電性G a A s基板上に
作製される場合、半絶縁性Ga A s基板上の場合に
比べて、FET間配間知線る浮遊容量が大きくなり、そ
れによる遅延が問題となる。
Problems to be Solved by the Invention However, when a large number of FETs are fabricated on a conductive GaAs substrate, the stray wires between the FETs are more likely to occur than on a semi-insulating GaAs substrate. As the capacity increases, the resulting delay becomes a problem.

そこで本発明では、FETは半絶縁性基板の特性を生か
して、FET間配間知線遊容量を減らし、また、レーザ
は、できるだけ一般に転位、欠陥が多い半絶縁性基板の
影響を受けないようにしてレーザの特性に大きな影響を
およぼさない構造にすることにより、高性能・高信頼な
、半絶縁性基板上光集積回路を実現することを目的とす
る。
Therefore, in the present invention, the FET takes advantage of the characteristics of the semi-insulating substrate to reduce the stray wire capacitance between the FETs, and the laser is designed to avoid being affected by the semi-insulating substrate, which generally has many dislocations and defects, as much as possible. The aim is to realize a high-performance, highly reliable optical integrated circuit on a semi-insulating substrate by creating a structure that does not significantly affect the characteristics of the laser.

問題点を解決するための手段 この問題点を解決する本発明の技術的手段は、基板のレ
ーザを作製する個所に凹部を作製し、その凹部を、導電
性G a A sで埋めることである。
Means for Solving the Problem The technical means of the present invention for solving this problem is to create a recess on the substrate at the location where the laser is to be manufactured, and to fill the recess with conductive GaAs. .

作  用 この導電性G a A sは、エピタキシャル成長技術
によシ作製するので、比較的良好な結晶であり、半絶縁
性基板の転位・欠陥等、レーザへの悪影響を緩和する(
いわゆるパy)1一層)。この凹部の深さを、深くする
ことにより、バッファ一層の厚さは厚くでき、緩和効果
はよシ大きくなる。一方、レーザとFETば、凹部の深
さにかかわらず、同一面上に作製するのでバッファ一層
が厚くなることによる、配線段差の問題は生じない。
Function: This conductive GaAs is produced by epitaxial growth technology, so it is a relatively good crystal, which alleviates the adverse effects on the laser such as dislocations and defects in the semi-insulating substrate (
The so-called pie) 1 layer). By increasing the depth of this recess, the thickness of the buffer layer can be increased, and the relaxation effect can be further increased. On the other hand, since the laser and FET are fabricated on the same surface regardless of the depth of the recess, there is no problem with the wiring step difference due to the thicker buffer layer.

実施例 第1図は本発明の一実施例による光集積回路の断面図で
あり、FET活性層として、ブロッキング層成長層9を
用いた。第1図中2〜8が、前記のBTR8型半導体レ
ーザであり、p型Ga A s成長層2上に、二つのリ
ッジを有する電流ブロッキング層3があり、とのりフジ
間を通してのみ電流注入が可能である。従って、活性層
5のリッジ間直上部分に電流が集中し、低閾値でレーザ
発振が起る。p型G a A s成長層2は、半絶縁性
G a A s基板1のレーザへの転位・欠陥の影響を
緩和するバッファ一層を兼ねており、その深さを深くす
ることで、転位・欠陥の影響はより緩和される。
Embodiment FIG. 1 is a sectional view of an optical integrated circuit according to an embodiment of the present invention, in which a blocking layer growth layer 9 was used as the FET active layer. Reference numerals 2 to 8 in FIG. 1 indicate the aforementioned BTR8 type semiconductor laser, in which there is a current blocking layer 3 having two ridges on the p-type GaAs growth layer 2, and current can be injected only through the gap between the edges. It is possible. Therefore, current is concentrated in the portion directly above the ridges of the active layer 5, and laser oscillation occurs at a low threshold. The p-type GaAs growth layer 2 also serves as a buffer layer that alleviates the influence of dislocations and defects on the laser of the semi-insulating GaAs substrate 1, and by increasing its depth, dislocations and defects can be reduced. The effects of defects are more relaxed.

一方、電流ブロッキング層成長層3を、活性層9とする
FETは、ゲート電極11が金属の場合はMESFET
、p型AlGaAsの場合は、ヘテロ接合FETとなる
。p型GaAs2とp型電極13がオーミック接触、p
型電極13と、ソース電極12が金属−金属接触してい
ることにより、レーザとFETは直列に接続されている
。従って、レーザを流れる電流、およびそれによるレー
ザ出力光は、FETのゲート入力信号Sによシ変調する
ことが出来る。
On the other hand, an FET in which the current blocking layer growth layer 3 is the active layer 9 is a MESFET when the gate electrode 11 is made of metal.
, p-type AlGaAs, it becomes a heterojunction FET. The p-type GaAs2 and the p-type electrode 13 are in ohmic contact, p
Since the mold electrode 13 and the source electrode 12 are in metal-to-metal contact, the laser and the FET are connected in series. Therefore, the current flowing through the laser and the resulting laser output light can be modulated by the gate input signal S of the FET.

この光集積回路の作製法を簡単にのべる。まず半絶縁性
G a A s基板1に、凹部を化学エツチングで作製
する(第2図(a))。次に、エピタキシャル技術によ
り、p型GaAs成長層2で、凹部を埋める(同図(b
))。さらに、ホトリンフイー技術により、p型GaA
s2のメサ部にマスクを付けた後、FET炸裂個所が、
半絶縁性基板1になるまで、エツチングする(同図(C
))。次に、n型G a A sブロッキング層3の成
長を行なう。そして2本の平行なリッジ(高さ1.5μ
m9幅2011m、リッジ間の清福6μm)を形成する
。この上にp型AlGaAs第1クラッド層4(厚さ0
.4μm)、A I Ga A ts 活性層4(厚さ
0.03〜0.04μm )、n型A I GaAs第
二クラッド層5(厚さ2μm、n型G a A sキャ
ップ層7(厚さ2.5μm)を成長させる。次にFET
作製個所のみ選択エッチして、n型G a A s層9
0表面を露呈させる。次にn型GaA3ブロッキング層
とFETの活性層9をエツチングにより分離する。次に
p型電極13、n型電極10.12を蒸着により形成す
る。最後にゲート電極11を形成する。
The manufacturing method of this optical integrated circuit will be briefly described. First, a recess is formed in the semi-insulating GaAs substrate 1 by chemical etching (FIG. 2(a)). Next, by epitaxial technology, the recess is filled with a p-type GaAs growth layer 2 (see figure (b).
)). Furthermore, p-type GaA
After attaching a mask to the mesa part of s2, the FET explosion point is
Etch until the semi-insulating substrate 1 is obtained (see figure (C)
)). Next, an n-type GaAs blocking layer 3 is grown. and two parallel ridges (height 1.5μ
m9 width: 2011 m, width between ridges: 6 μm). On top of this, p-type AlGaAs first cladding layer 4 (thickness 0
.. 4 μm), A I Ga Ats active layer 4 (thickness 0.03 to 0.04 μm), n-type AI GaAs second cladding layer 5 (thickness 2 μm), n-type Ga As cap layer 7 (thickness 2.5μm).Next, FET
By selectively etching only the fabricated portion, the n-type GaAs layer 9
0 surface is exposed. Next, the n-type GaA3 blocking layer and the FET active layer 9 are separated by etching. Next, a p-type electrode 13 and an n-type electrode 10.12 are formed by vapor deposition. Finally, a gate electrode 11 is formed.

発明の効果 本発明は、半導体レーザ成長層と、半絶縁性基板の間に
、バッファ一層を入れることKよ)、その基板内の転位
や欠陥の影響を防ぎ、良好な半導体レーザを集積してい
ること、および半絶縁性基板を用いているので、多数の
FETも集積可能であること、さらに、FET活性層は
レーザの電流ブロッキング層または、第2クラッド層ま
たは、キャップ層を兼ねているため、作製が容易なこと
を特徴とする光集積回路である。また、60℃、5 m
 ’Wの寿命試験では、一般のBTR3型半導体レーザ
とほとんど変らず、またFET部の動作特性は、一般の
GaAsICと同じであった。このように、この光集積
回路が、半導体レーザと、GaAsICの集積化、およ
び、光通信関係に与える影響は犬である。
Effects of the Invention The present invention provides a buffer layer between the semiconductor laser growth layer and the semi-insulating substrate to prevent the influence of dislocations and defects in the substrate and to integrate a good semiconductor laser. Furthermore, since a semi-insulating substrate is used, a large number of FETs can be integrated, and the FET active layer also serves as the laser's current blocking layer, second cladding layer, or cap layer. , is an optical integrated circuit characterized by easy fabrication. Also, 60℃, 5 m
In the life test of 'W, there was almost no difference from a general BTR3 type semiconductor laser, and the operating characteristics of the FET section were the same as a general GaAs IC. In this way, the influence that this optical integrated circuit has on the integration of semiconductor lasers and GaAs ICs, and on optical communication relationships is significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例の光集積回路装置の断面図
、第2図(a)〜(C)は、この光集積回路装置作製工
程の一部を示す断面図である。 1・・・・・・半絶縁性G a A g基板、2・・・
・・・p型G a A sバッファ一層、3・・・・・
・n型G a A sブロツキング層、4・・・・・・
p型AlGaAs第1クラッド層、6・・・・・・AI
G a A s 活性層、6・・・・・・n型A I 
G a A g第2クラッド場、7・・・・・・n型G
aAsキャップ層、8・・・・・・n型電極、9・・・
・・・n型GaAsFET活性層、1o・・・・・・ド
レイン電極、11・・・・・・ゲート電極、12・・・
・・・ソース電極、13・・・・・・p型電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名/−
−−りき紡4’l眞A5X役 2−p %GaA31f’、、 77−!3−−−n”
4元4j 7゛口、千シク冴’−−−F’;j+1kA
s ”g I 7ランム〉看5−−1+ノG(LAsう
1a14 ’−−nLAIGa、As %zグラツレ曾7−n 9
−(xaAs hyf4 8−r+!碇極 1f−−−ゲーY′〕 12−−− =へス。 f3−−− P % m 5−−一人力イ5号
FIG. 1 is a cross-sectional view of an optical integrated circuit device according to an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views showing a part of the manufacturing process of this optical integrated circuit device. 1... Semi-insulating G a A g substrate, 2...
...p-type GaAs buffer layer 3...
・N-type GaAs blocking layer, 4...
p-type AlGaAs first cladding layer, 6...AI
G a As active layer, 6...n-type A I
G a A g second cladding field, 7...n-type G
aAs cap layer, 8...n-type electrode, 9...
... n-type GaAsFET active layer, 1o ... drain electrode, 11 ... gate electrode, 12 ...
. . . Source electrode, 13 . . . P-type electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Rikibo 4'l Makoto A5X role 2-p %GaA31f',, 77-! 3---n"
4 yuan 4j 7゛mouth, 1,000 yen'---F';j+1kA
s ”g I 7 ram〉see5--1+ノG(LAsU1a14'--nLAIGa, As %z GLATURE Z7-n 9
-(xaAs hyf4 8-r+! Ikari Goku 1f---Ge Y') 12--- = Hess.

Claims (3)

【特許請求の範囲】[Claims] (1)半絶縁性GaAs基板の表面の一部に導電性Ga
As埋込層が形成され、前記導電性GaAs埋込層の表
面に半導体レーザが前記半絶縁性GaAs基板の表面に
FETが形成されており、かつ、前記半導体レーザに流
れる電流は、前記FETにより変調されることを特徴と
する光集積回路装置。
(1) Conductive Ga on a part of the surface of the semi-insulating GaAs substrate
An As buried layer is formed, a semiconductor laser is formed on the surface of the conductive GaAs buried layer, and a FET is formed on the surface of the semi-insulating GaAs substrate, and a current flowing through the semiconductor laser is caused by the FET. An optical integrated circuit device characterized in that it is modulated.
(2)半導体レーザが、導電性GaAs埋込層上に、電
流ブロック層、第1クラッド層、活性層、第2クラッド
層およびキャップ層が順次形成されており、かつブロッ
ク層上には、二つのリッジが設けられており、両リッジ
間の間隙を通してのみ電流注入が可能な構造を有するこ
とを特徴とする特許請求の範囲第1項記載の光集積回路
装置。
(2) A semiconductor laser has a current blocking layer, a first cladding layer, an active layer, a second cladding layer, and a cap layer formed in this order on a conductive GaAs buried layer, and two layers are formed on the blocking layer. 2. The optical integrated circuit device according to claim 1, wherein the optical integrated circuit device has a structure in which two ridges are provided and current can be injected only through the gap between the two ridges.
(3)電流ブロック層、または第2クラッド層、または
キャップ層がFET活性層を構成していることを特徴と
する特許請求の範囲第2項記載の光集積回路装置。
(3) The optical integrated circuit device according to claim 2, wherein the current blocking layer, the second cladding layer, or the cap layer constitutes an FET active layer.
JP1510786A 1986-01-27 1986-01-27 Optical integrated circuit device Pending JPS62173779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1510786A JPS62173779A (en) 1986-01-27 1986-01-27 Optical integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1510786A JPS62173779A (en) 1986-01-27 1986-01-27 Optical integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62173779A true JPS62173779A (en) 1987-07-30

Family

ID=11879611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1510786A Pending JPS62173779A (en) 1986-01-27 1986-01-27 Optical integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62173779A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186385A (en) * 1983-04-06 1984-10-23 Agency Of Ind Science & Technol Semiconductor laser device
JPS60176225A (en) * 1984-02-22 1985-09-10 Matsushita Electric Ind Co Ltd Liquid-phase epitaxial crowth method
JPS618983A (en) * 1984-06-23 1986-01-16 Oki Electric Ind Co Ltd Manufacture of monolithic semiconductor laser array with two wavelengths

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186385A (en) * 1983-04-06 1984-10-23 Agency Of Ind Science & Technol Semiconductor laser device
JPS60176225A (en) * 1984-02-22 1985-09-10 Matsushita Electric Ind Co Ltd Liquid-phase epitaxial crowth method
JPS618983A (en) * 1984-06-23 1986-01-16 Oki Electric Ind Co Ltd Manufacture of monolithic semiconductor laser array with two wavelengths

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