KR900001397B1 - Gas tetero junction field elfect transistor - Google Patents

Gas tetero junction field elfect transistor Download PDF

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KR900001397B1
KR900001397B1 KR1019870012745A KR870012745A KR900001397B1 KR 900001397 B1 KR900001397 B1 KR 900001397B1 KR 1019870012745 A KR1019870012745 A KR 1019870012745A KR 870012745 A KR870012745 A KR 870012745A KR 900001397 B1 KR900001397 B1 KR 900001397B1
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gaas
type
layer
thickness
etching
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KR1019870012745A
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KR890008998A (en
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남춘우
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors

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Abstract

GaAs heterojunction FET is selectively etched as follows: (1) epitaxial growing of GaAs buffer layer of 2-3um thickness on semiinsulation GaAs substrate; (2) etching parts except the part to locate a gate electrode, after epitaxial growing of a n-type GaAs active layer of 0.5um thickness, p-type AlGaAs layer of 1.5um thickness, and p-type GaAs cap layer of 0.8um thickness, and coating them with photoresist; and (3) etching the transistor with HCl or H3PO4, using the difference of etching rate between p-type AlGaAs and p-type GaAs.

Description

갈륨 비소 이종접합 전계효과 트랜지스터Gallium Arsenide Heterojunction Field Effect Transistor

제1도는 일반적인 이종접합 전계효과 트랜지스터의 단면도.1 is a cross-sectional view of a general heterojunction field effect transistor.

제2a~d도는 본 발명 이종접합 전계효과 트랜지스터의 공정을 보인 단면도.2A to 2D are cross-sectional views showing a process of the heterojunction field effect transistor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : GaAs 기판 2 : GaAs 버퍼층1 GaAs substrate 2 GaAs buffer layer

3 : n-GaAs 활성층 4 : p-GaAs 확산층3: n-GaAs active layer 4: p-GaAs diffusion layer

5 : p-AlGaAs 층 6 : p-GaAs 캡층5: p-AlGaAs layer 6: p-GaAs cap layer

7 : 소오스/드레인 전극 8 : 게이트 전극7 source / drain electrode 8 gate electrode

본 발명은 재현성이 좋고 식각율의 차이가 현저하게 나타나는 p형 GaAs와 p형 AlGaAs의 이종접합(hetero junction)을 선택적으로 식각하여 형성된 갈륨비소 이종접합 전계효과 트랜지스터(이하 FET라 칭함)에 관한 것이다.The present invention relates to a gallium arsenide heterojunction field effect transistor (hereinafter referred to as a FET) formed by selectively etching heterojunctions of p-type GaAs and p-type AlGaAs, which are reproducible and show significant differences in etching rates. .

일반적인 FET는 쇼트키 장벽을 이용한 디플리이션형 및 엔핸스먼트형의 FET게이트 구조가 주종을 이루었으나, 쇼트키 금속의 열적 안정성이 문제가 되어 신뢰도 및 재현성이 떨어지는 경우가 많으며, 에너지 밴드갭이 아주 작은 것들은 쇼트키 접합에 적2 3 4 2 Generally, FET gate structure of deflation type and enhancement type using Schottky barrier is mainly used. However, thermal stability of Schottky metal is a problem, resulting in poor reliability and reproducibility, and energy band gap. Very small ones on the schottky junction 2 3 4 2

또한, 일반적인 이종접합 FET는 제1도에 도시한 바와 같은 n형 GaAs활성층(3)에 아연(Zn)을 확산하여 p형 GaAs확산층(4)을 형성하는 불순물 확산에 의한 PN접합을 형성 하였으나, n형 GaAs활성층(3)에서 아연(Zn)의 확산계수가 크기 때문에 SiO2-GaAs계 활성층(3)에서의 횡형 확산이 너무 커서 불순물을 원하는 부분에 정확하게 확산시키기가 어려워 재현성이 문제가 되었다.In addition, the general heterojunction FET forms a PN junction by diffusion of impurities to form a p-type GaAs diffusion layer 4 by diffusing zinc (Zn) into the n-type GaAs active layer 3 as shown in FIG. Since the diffusion coefficient of zinc (Zn) in the n-type GaAs active layer 3 is large, the lateral diffusion in the SiO 2 -GaAs-based active layer 3 is so large that it is difficult to accurately diffuse impurities in a desired portion, thereby causing reproducibility problems.

본 발명은 상기와 같은 문제점을 감안하여 재현성이 좋고 현저한 식각율의 차이를 나타내는 p형 GaAs/p형 AlGaAs이종접합을 선택적 식각하여 형성된 이종접합 FET를 제작하고자 인출한 것으로 이를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.In view of the above problems, the present invention was drawn to fabricate a heterojunction FET formed by selectively etching a p-type GaAs / p-type AlGaAs heterojunction having good reproducibility and a significant difference in etching rate. The explanation is as follows.

제2a도에 도시한 도면에 표현된 바와 같이 반 절연성 GaAs기판(1)상에 GaAs버퍼층(2)을 2-3μm두께로 에피택시하고, 상기 GaAs버퍼층(2)상에 0.5μm두께로 n형 GaAs활성층(3)과 1.5μm두께의 p형 AlGaAs층(5) 및 0.8μm두께의 p형 GaAs캡층(6)을 에피택시하여 포토레지스트를 도포한 후, 게이트 전극이 위치할 부분을 제외한 부분을 노광과 현상을 거쳐 알카리-과산화수소계의 식각용액으로 제2b도에 도시한 바와같이 식각한 다음 염산과 인산식각용액에서 선택적 식각을 하면, p형 GaAs캡층(6)은 식각률이 낮으므로 p형 AlGaAs층(5)에 대한 마스킹 역할을 하게되고, p형 AlGaAs층(5)은 측면에서부터 식각되어 제2c도와 같이 셀프얼라인 구조로 식각되며, 이와 같은 상태에서 제2d도에 도시한 바와 같이 소오스/드레인 전극(7) 및 게이트 전극(8)을 형성하면 이종접합 FET가 형성된다.As shown in FIG. 2A, the GaAs buffer layer 2 is epitaxially deposited on the semi-insulating GaAs substrate 1 with a thickness of 2-3 μm, and the n type is 0.5 μm on the GaAs buffer layer 2. After epitaxially coating the GaAs active layer 3, the p-type AlGaAs layer 5 having a thickness of 1.5 μm, and the p-type GaAs cap layer 6 having a thickness of 0.8 μm, the photoresist was applied, and the portions except for the portion where the gate electrode is to be placed were removed. After etching and developing the alkali-hydrogen peroxide-based etching solution as shown in FIG. 2b, and then selectively etching it with hydrochloric acid and phosphate etching solution, the p-type GaAs cap layer 6 has a low etching rate. It acts as a masking for the layer 5, the p-type AlGaAs layer 5 is etched from the side and etched in a self-aligned structure as shown in Figure 2c, in this state as shown in Figure 2d The heterojunction FET is formed by forming the drain electrode 7 and the gate electrode 8.

이상에서와 같은 제법에 의하여 형성된 본 발명 이종접합 FET는 식각율이 현저한 차이를 나타내는 p형 GaAs와 p형 AlGaAs를 사용하여 제작되었으므로, 쇼트키 게이트 FET 보다도 낮은 누설전류와 높은 항복전압을 얻을 수 있어 열적 안정 및 신뢰도가 높고 재현성이 좋아 GaAs마이크로 웨이브 트랜지스터등에 사용될 수 있는 것이다.Since the heterojunction FET of the present invention formed by the above-described method is manufactured using p-type GaAs and p-type AlGaAs, which show significant differences in etching rate, lower leakage current and higher breakdown voltage can be obtained than Schottky gate FET. The thermal stability, reliability and high reproducibility can be used for GaAs microwave wave transistors.

Claims (1)

반 절연성 GaAs기판(1)상에 GaAs버퍼층(2)을 2-3μm두께로 에피택시하고, 상기 GaAs버퍼층(2)상에 0.5μm두께의 n형 GaAs활성층(3)과 1.5μm두께의 p형 AlGaAs층(5) 및 0.8μm두께의 p형 GaAs 캡층(6)을 에피택시하여 포토레지스터를 도포한 후 게이트 전극(8)이 위치할 부분을 제외한 부분은 식각한 다음, 상기 p형 AlGaAs층(5) 및 p형 GaAs캡층(6)의 식각율 차이를 이용하여 염산과 인산 식각용액으로 선택적 식각한 갈륨 비소 이종접합 전계효과 트랜지스터.A epitaxial GaAs buffer layer 2 on the semi-insulating GaAs substrate 1 with a thickness of 2-3 μm, and a 0.5 μm thick n-type GaAs active layer 3 and a 1.5 μm p-type on the GaAs buffer layer 2 After epitaxially coating the AlGaAs layer 5 and the p-type GaAs cap layer 6 with a thickness of 0.8 μm, the photoresist was applied, and portions except for the portion where the gate electrode 8 is to be etched were etched, and then the p-type AlGaAs layer ( 5) and gallium arsenide heterojunction field effect transistor selectively etched with hydrochloric acid and phosphoric acid etching solution using the difference in etching rate of p-type GaAs cap layer (6).
KR1019870012745A 1987-11-12 1987-11-12 Gas tetero junction field elfect transistor KR900001397B1 (en)

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KR900001397B1 true KR900001397B1 (en) 1990-03-09

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