JPS6217317B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital audio editing device for editing audio signals recorded by a digital recording/playback device.

Conventionally, when editing analog-recorded tapes, useful parts of the recorded tapes are cut out by hand and then spliced together to form a single tape. This situation is shown in FIG. In Figure 1, 1 and 2 are parts of the recorded tape, part A of 1 is a necessary part, part B is an unnecessary part, part C of 2 is an unnecessary part, and part D is a necessary part. shall be. Desired tape 3 can be created by cutting these tapes and mechanically joining them together.
can be obtained. At this time, it was necessary to find the cutting positions of tapes 1 and 2, that is, the boundaries between A and B and C and D (hereinafter referred to as editing points), but in order to do so, the following operations were necessary. . That is, the tape recorder is put into a playback state, and while listening to the playback sound, the tape recorder is stopped at a position that appears to be an editing point. In order to find a more accurate editing point, the take-up reel and the supply reel of the tape recorder are manually rotated forward and reverse in the same direction, and the editing point is determined by listening to the reproduced sound. That is, when such fine adjustments are made and it is determined that the tape is at a desirable editing point, the position of the tape in contact with the gap portion of the playback head is set as the correct editing point, and the above-mentioned cutting is performed. The reason why the tape is cut diagonally as shown in FIG. 1 is to prevent the reproduced sound from becoming discontinuous at the editing point when the edited tape is played back. This is because the effect is that the sound of section A gradually becomes smaller (fade out) and the sound of section D gradually becomes louder (fade in). This connection process is called crossfade.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying it to digital recording and playback devices that have been put into practical use in recent years. In other words, since the recorded signal in a digital recording/playback device is a digital signal, cutting diagonally like an analog signal means that meaningless information continues for that period, and it is obvious that this will have a harmful effect on the reproduced sound. be. On the other hand, even when the tape is cut perpendicular to the direction of tape progression in order to reduce information loss as much as possible, digital recording/playback equipment usually adds error/correction codes to dozens of samples of information bits and converts them into one PCM frame. Because of recording, errors in information in one PCM frame are inevitable. Therefore, (a) apply mutating to that part, (b) skip that part and connect the information before and after.
Such operations are necessary, and in any case, the deterioration in the sound quality of the original information at that part is essentially a problem.

The present invention provides an editing device suitable for a digital recording/playback device that does not cause the above-mentioned problems.

An embodiment of the present invention will be described below based on the drawings. First, an outline of the editing method of the editing device according to the present invention will be explained. In this method, the recorded tape is not mechanically cut, but instead two digital recording and playback devices are used. The first digital recording and playback device plays the first tape before editing, and the second digital A recording/playback device records only the necessary portions of the first tape onto a second tape to create one edited tape. This will be explained with reference to FIG. That is, in FIG. 2a, 1 and 2 are different parts of a first tape attached to a first digital recording/playback device, and 3 is a different portion of a first tape attached to a second digital recording/playback device. This is the second tape. Therefore, in operation, first, one of the first tapes attached to the first digital recording/playback device is
The part 1 is played back, and the part that passes the boundary between A and B in 1 and slightly enters the area B is recorded on a second tape attached to a second digital recording/playback device. This situation is shown in FIG. 2b. Next, the first tape is played back from a distance _L1 before the boundary between C and D in 2. At the same time, the second tape is played from _L2 before the boundary between A and B. Here, L ₁ L ₂ is assumed to be the same value as the boundary between A and B of the second tape at the moment when the playback head of the first digital recording/playback device comes into contact with the boundary between C and D of the first tape. The length may be sufficient to allow the first tape and the second tape to run synchronously so that the recording head of the second digital recording/playback device comes into contact with the tape. By running the first tape and the second tape synchronously in this manner, it is possible to record D on the first tape from the boundary between A and B on the second tape. This situation is shown in FIG. 2c. At this time A and D
At the boundary, A is faded out and D is faded in by digital calculation. These operations are performed using time codes recorded on separate tracks on the tape.

The present invention realizes an editing device based on the above idea, and a detailed description of the embodiments will be given below. In Figure 3, 4 is a CPU (microcomputer) that controls this device;
5 stores the program for CPU4
ROM, 6 is a data bus (the address bus is omitted in the figure), 7 is an operation input section that gives control commands to this device, and 7' is a CPU that receives operation inputs.
4 is a control output section for outputting a display to show that it has been received or a control signal for controlling other parts of this device;
This is an interface element for interfacing with the CPU 4. On the other hand, P and R are digital signal input terminals from first and second digital recording and reproducing devices (hereinafter referred to as PCM tape recorders), respectively. 9 is a memory for writing and storing digital data from the input terminal P; 10 is a memory 9;
address counter, 11 is address counter 1
12 is a memory that similarly writes and stores digital data from the input terminal R, 13 is an address counter of the memory 12, and 14 is an interface element that interfaces the address counter 13 and the CPU 4. It is. 15, 15' are switches controlled by the output of the control output unit 7' from the CPU 4 via the interface element 8; 16 is the digital data from the first PCM tape recorder input from the input terminal P and the input terminal R; This is a crossfade processing circuit for digitally calculating the digital data from the second PCM tape recorder input from the memory 9 and the output data of the memory 12 to generate a crossfade. 17 is an interpolation circuit, which prevents the clock frequency from being mixed into the reproduced audio as noise when the memories 9 and 12 are reproduced at variable speeds and the memories are read at a clock frequency lower than the original sampling frequency. It is for the purpose of 18 is a D/A converter, 19 is a low-pass filter, 20 is an amplifier, and 21 is a monitor speaker. W is an output terminal to the second PCM tape recorder (recording tape recorder). 22 is a clock pulse generation circuit, 23 is a manual clock pulse generator, and 24 is the above-mentioned clock pulse generation circuit 22.
This is a selector switch which selects and outputs either the output of the manual clock pulse generator 23 or the output of the manual clock pulse generator 23 according to the output of the control output section 7'. The T _P terminal is an input terminal for the SMPTE time code reproduced by the first PCM tape recorder connected to the P terminal, 25 is the interface between the above time code input and CPU 4, and the T _R terminal is the second input terminal connected to the R terminal. The input terminal for the SMPTE time record played on the PCM tape recorder, 26 is the time code input above.
It is an interface with CPU4.

Next, the operation of this embodiment will be explained based on FIG. 3 as well. As a premise, the first
The tape attached to the PCM tape recorder is the first tape explained in FIG. 2, and the second PCM tape recorder connected to the R terminal is also the second tape. These are called a playback tape recorder and a recording tape recorder, respectively. First, the playback tape recorder is used to play back the part 1 (A, B part) in FIG. A second tape is made as shown in Figure 2b. Next, 2 in Figure 2 a.
Play back the parts (C and D parts), and play the parts A and B in Figure 2b.
D is recorded while performing crossfade processing from the boundary of
It is necessary to find the exact location of the boundary of B and the boundaries of C and D.

Next, the operation for determining the editing point will be explained.
First, in order to determine the boundary between C and D, part 2 of the first tape is played back by a tape recorder on the playback side and inputted to the P terminal. When PCM data is input to the P terminal, this data is cyclically recorded in the memory 9. In other words, once writing is completed to the last address of memory 9, writing starts again from the first address.As a result, if we take a certain moment, the PCM data stored in memory 9 will always be stored for a certain period of time from that moment. The previous data will be stored continuously. This memory 9
The address is controlled by an address counter 10. The clock pulses of the counter 10 are supplied with the clock pulses generated from the clock pulse generating circuit 22 by turning df of the switch 24 ON. Furthermore, switch 15 has b-c turned on, and the input PCM data is sent to crossfade processing circuit 1.
6. Pass through the interpolation circuit 17 and pass through the D/A converter 18
is converted into the original analog signal, the high-frequency component is cut by the low-pass filter 19, and the amplifier 2
The signal is amplified by 0 and supplied to the speaker 21, and the audio from the tape recorder on the playback side is monitored. Control of each of the above parts, such as the polarity of the switches 15 and 24, the crossfade processing circuit 16, and the interpolation circuit 17.
All operations such as disabling the control output section 7'
This is done by signals from. That is, a signal from an operation input unit 7 consisting of a keyboard push button, etc. is transmitted to the CPU 4 via an interface element 8 and a bus line 6, and a corresponding control signal is transmitted from the CPU 4 to a bus line 6 and an interface element 8. This signal is outputted from the control output section 7' via the control output section 7'. In FIG. 3, control lines from the control output section 7' to other parts than the switch are omitted.

The editor inputs a signal from the operation input section 7 indicating that it is the desired timing to edit while monitoring the output audio from the speaker 21. This signal is transmitted to the CPU 4 through the above-mentioned path, and the following control is performed via the control output section 7'. First, the operation continues for a certain period of time from an editing point desired by the editor, and after the certain period of time, writing to the memory 9 is stopped. Thereafter, tape running in the playback tape recorder is stopped. Tape recorder control
This is executed by an instruction from the CPU 4, but is omitted from the diagram. Now, the contents of the memory 9 at this time are as shown in FIG. Here, the specifications are assumed as follows. Audio data is 16 bits/sample, sampling frequency is 50kHz, memory is 256KW (1W = 16
In this way, the audio data stored in the memory 9 is approximately 5 seconds, as 256k÷50k≈5 seconds. Of course, in order to save memory, the data may be stored in memory every other sample (this means that the sampling frequency is halved). Alternatively, a method such as reducing the number of bits per sample using a bit compression method may be applied. Here, in order to simplify the explanation, such processing will not be performed at all. In Figure 4, a 256KW memory is simulated, and audio data is written sequentially from left to right.
If you write up to 2FFFF, you will write again from 00000, and this will be repeated. The memory address corresponding to the timing desired by the editor is represented by _XP in the figure. Then, the writing is completed at a timing corresponding to the memory address of Y _P delayed by, for example, 4 seconds within the repetition cycle as a fixed period of time. As a result, memory 9 contains (Y _P +1) → 2FFFF → 00000
This means that the audio is recorded in the order of → _YP .

Next, in order to search for the correct editing point, the contents of the memory 9 are read out, and by setting the device to the editing point search mode from the operation input section 7, the editor can send control signals to each section. becomes as follows. Switches 15 and 24 are turned on at a and c, and d and e are turned on at switches 24 and 24, respectively. Reference numeral 23 denotes a manual clock pulse generator composed of a rotary encoder, etc., and the frequency of the pulses it generates changes depending on the speed of movement, and if it is stopped, no pulses are generated at all. For example, if a rotary dial is used as the manual control means,
The higher the rotation speed, the more pulses are generated. If this pulse and information on the rotation direction are given to the address counter 10 and it operates as an up-down counter, for example, when the rotation is clockwise, the memory is input in the forward direction, that is, (Y _P +
1) Play in the order of →2FFFF→00000→ _YP . The faster the rotation, the higher the frequency of the audio being played. When it is rotated counterclockwise, it is reproduced in the order of Y _P →00000 → 2FFFF → (Y _P +1), and the sound is reproduced as if a recorded tape of a tape recorder was rotated backwards.
Naturally, the frequency of the reproduced sound changes depending on the rotation speed at this time as well. When playing back audio sampled at 50KHz and stored at a variable speed in this way, there are the following problems. That is, the playback
There is no particular problem when reproduction is performed at a clock frequency of 50KHz or more, but when reproduction is performed at a frequency lower than 50KHz, for example 10KHz, a 10KHz component is generated due to this clock frequency. However, the cutoff frequency of the low-pass filter 20 is, for example, 20 KHz, which is the optimum value when the sampling frequency is 50 KHz. Therefore, the 10 KHz component is not removed by the low-pass filter 19 and is heard as noise. In order to solve this problem, the interpolation circuit 17 is operated.

Next, its function will be explained with reference to FIG. FIG. 5a shows the audio signal stored in the memory reproduced at normal speed, that is, 50 KHz, and subjected to D/A conversion. Play the same signal at 10KHz and D/A
When converted, it becomes as shown in Fig. 5b. Here, points S in FIGS. 5a and 5b indicate the same sample. The purpose of this circuit is to smoothly interpolate the discontinuous portions of these signals at 50 KHz as shown in Figure 5c.

First, the concept of interpolation will be explained. FIG. 6 shows an enlarged view of a portion of FIGS. 5b and 5c. In FIG. 6, 31 is an input to the interpolation circuit. a and b are outputs read from the memory, and are sample values of temporally adjacent samples. T ₁₀ T ₂₀
is the timing of the manual clock pulse, and T ₂₀ is the timing of the manual clock pulse.
This is the timing one clock period after _T10 .
T ₁₀ , T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ and T ₂₀ are the timings of sampling clock pulses. 32 is the output of the interpolation circuit 17. T _1o (n=0, 1, 2,
The output L _1o of the interpolation circuit 17 in 3 and 4) is determined as follows.

L _1o = a + (b - a) · n · k ... (1) Here, k is a coefficient inversely proportional to the frequency of the output of the manual clock pulse generator 23, and if it is easily determined, for example in the case of FIG. The output of the clock pulse generator 23 is 10KHz, and the sampling frequency is
Since it is 50KHz, it is set as 1/5. In equation (1), k
It can be seen that if =1/5n=0, 1, 2, 3, 4, 32 interpolations shown in FIG. 6 can be performed. A block diagram for realizing the above functions is shown in FIG.

FIG. 7 shows a block diagram of the interpolation circuit 17.
is the 16-bit parallel signal input to the interpolation circuit, 53
is a terminal to which the output of the manual clock pulse generator 23 is input, and 54 is a sampling clock (50 KHz in this case) input terminal. 41 and 42 are latch circuits; 43 is a subtracter that subtracts the output of the latch circuit 42 from the output of the latch circuit 41; 44 is an adder;
A latch circuit 45 latches the output of the adder circuit 44 using a sampling clock. 46 is a reference clock pulse generation circuit (for example, 50KHz×
100 = generates a 5MHz clock pulse). A counter 47 is reset by the output of the manual clock pulse generator 23 and counts the output of the reference clock pulse generator 46;
a circuit 49 consisting of a ROM, which uses the output value of the counter 47 as an address and outputs the contents of the ROM corresponding to that address to generate a slope coefficient k;
are the output of the latch circuit 45 and the slope coefficient generating circuit 48
50 is a multiplication circuit 4 which multiplies the slope of the output of
An adder circuit 51 adds the output of 9 and the output of the latch circuit 42, and 51 is a circuit that latches the polarity bit of the output of the latch circuit 43 to determine the polarity of the multiplier circuit 49. 55 is the output of the interpolation circuit.

The outputs of the latch circuits 41 and 42 are the sixth
Corresponds to b and a in the figure. The output of the subtraction circuit 43 is (ba) in equation (1). Furthermore, the combination of adder circuit 44 and latch 45 yields the output (ba).times.n. Since the frequency of the output of the reference clock pulse generation circuit 46 is 5 MHz and the frequency of the output of the manual clock generator 23 is 10 KHz, the output of the counter 47 is 500. At this time, 100/500=1/5 is outputted as the output k of the slope coefficient generation circuit 48, which is constituted by a ROM, for example. That is, if the output of the counter 47 is Z, then 100/Z is k. As a result, the output of the multiplication circuit 49 is (b-
a)・n・k is obtained. Further, as the output of the adder circuit 50, a+(ba)·n·k of equation (1) is obtained. Therefore, the dotted line 32 in FIG. 6 is obtained as the output 55 of the interpolation circuit. Here a and b
The polarity bit is determined by the polarity determination circuit 51 depending on the magnitude relationship between
The sign bit of the multiplication circuit 49 is changed through the step .
In addition, in FIG. 7, the second term of equation (1) is (b−
a) The configuration is such that ×n is calculated first, but depending on the hardware, overflow may occur at this stage, so if you configure the configuration to calculate k×n first, this risk will disappear. .

As described above, the output of the interpolation circuit 17 shown in FIG.
9. The sound reproduced at variable speed from the speaker 21 via the amplifier 20 can be monitored. At this time, if you turn the dial in the forward or reverse direction, you will hear exactly the same playback sound as when you manually rotate the reel of a conventional analog tape recorder in the forward and reverse directions.

In this way, the dial is stopped at the point to be edited, and a signal indicating that the point is the editing point is given to the CPU 4. This means that the position of the boundary between C and D in FIG. 2 has been determined. In order for the CPU 4 to recognize this position, the following process is performed. First, at the editing point given by the editor, the time code input signal from the T _P terminal, which is input at the same time as the PCM data, is sent to the CPU 4 via the time code interface 25 and the bus line 6.
loads. In SMPTE time code, the minimum signal unit is a frame (1/30th of a second), so if you want to increase the editing accuracy beyond this, you need to count the audio sampling pulses within the frame and calculate the number of samples within the frame. Also includes information on whether there is
Although the CPU 4 needs to read the counter, this counter is omitted in FIG. 3 and is included in the time code interface 25. Therefore, at this point, the CPU 4 reads information on hours, minutes, seconds, frames, and samples. Next, in the edit point search mode, the counter in the time code interface 25 operates together with the address counter 10 by the output of the manual clock pulse generator 23, and the time code information of the correct manually corrected edit point and the more detailed frame unit are operated. The CPU 4 reads the sample point information within, that is, hour, minute, second, frame, and sample information. In this way,
The CPU 4 has information on the exact position of the sample point in the memory 9 and on the tape. Let the address in the memory 9 of the edit point determined at this point be X _P +N _P .

Next, determine the boundary between A and B of the second tape in FIG. 2b. The recording side tape recorder is played back, and PCM data is input to the R terminal. This data is recorded cyclically in memory 12. At this time, the memory address counter 13, switch 24, switch 15, crossfade processing circuit 16, interpolation circuit 1
7. The operations of the D/A converter 18, the low-pass filter 19, the amplifier 20, and the speaker 21 are the same as those in the reproduction side tape recorder, so a description thereof will be omitted. While monitoring the output audio from the speaker 21, the editor inputs a signal to that effect from the operation input section 7 at a timing when he wants to edit, that is, near the boundary between A and B of the second tape, as described above. Thereafter, writing continues in the memory 12 for a certain period of time, and the process is the same until it stops. However, in this case, assuming that the capacity of the memory 12 is approximately 5 seconds as in the case of the memory 9, writing to the memory 12 is stopped when, for example, 1 second has elapsed from the specified point. The state inside the memory 12 at this time is shown in FIG. X _R and Y _R correspond to X _P and Y _P in FIG. 4, respectively. Furthermore, the operation of searching for the correct editing point in the memory 12 is performed by switching the switch 15' from a' to
When c' is turned on and the dial is rotated in the positive direction, the contents of memory 12 are (Y _R +1) → 2FFFF
It is reproduced in the order of →00000→X _R , and when rotated in the opposite direction, it is reproduced in the order of X _R →00000 → 2FFFF → (Y _R +1). In this way, the audio is played back as the dial rotates, so it is possible to stop the dial at the correct position and designate this point as the editing point. The position information at this point is read into the CPU 4 by the same operation as in the case described above.
Let the address of this point on the memory be X _R +N _R .

As described above, the time code on the tape, the position information based on the PCM sample point, and the information based on the address on the memory regarding the boundaries of C and D and the boundaries of A and B in Figure 2 are stored in the register in the CPU. .

Next, the contents of the memory 12 and the memory 9 are continuously read out using the editing point determined above as a boundary point to monitor the audio in the actually edited state. At this time, crossfade processing is performed at the editing point to obtain a natural sound connection. This series of actions is called rehearsal here. At the time of rehearsal, the editor gives a rehearsal instruction to the CPU 4 from the operation input section 7. The CPU 4 controls the initial value of the address counter 13 through the address counter interface element 14 and also controls the address counter 10 through the address counter interface element 11.

The crossfade time is given from the operation input section 7. For example, 1ms, 10ms, 100ms,
This is done by selecting one of the operation buttons such as 300ms and 500ms. FIG. 9 shows the operation when the crossfade time is F seconds. Memory playback in the case of rehearsal is performed in the following order based on instructions from the CPU 4. The rehearsal starting point is Y _R +1 in the memory 12 and is played back in the order of 2FFFF→00000→X _R , but the crossfade starts from X _R +N _R -1/2Z. Here, Z is the number of memory addresses advanced in F seconds, which corresponds to 50×10 ³ (KHz)×F (seconds). Memory 12 is X _R +N _R -1/2
When Z is reached, the memory 10 starts playing back from X _P +N _P -1/2Z and a crossfade period begins.
Thereafter, the memories 9 and 12 are simultaneously reproduced for F seconds, that is, Z memory addresses, and a crossfade process is performed. Memory 12 is X _R +N _R +
The crossfade period ends when the memory 9 reaches 1/2Z and the memory 9 reaches X _P +N _P +1/2Z, and only the memory 9 is played back up to Y _P and the rehearsal ends.

Here, the above-mentioned crossfade processing will be specifically described. FIG. 10 is a detailed block diagram of the fade processing circuit 16 in FIG. 3. Fi1
is the input from switch 15' in Figure 3, Fi
2 is an input from the switch 15 as well. C.K.
is the sampling clock pulse input. 61
is a fade curve generation circuit that digitally generates crossfade curve coefficients, and is composed of a counter or a combination of an address counter and ROM. An example of the output of this circuit is shown at 66 in FIG. Here, the vertical axis is the magnitude when the above coefficient is subjected to D/A conversion. A multiplication circuit 62 digitally multiplies the output of the fade curve generation circuit 27 and the PCM audio signal input from Fi1. As a result, the output of the multiplication circuit 62 becomes the input from Fi1 faded out. 63 is a fade curve generating circuit similar to 61, and an example of its output is shown at 67 in FIG.
64 is a multiplication circuit that multiplies the input of Fi2 and the output of 63, and the output of the multiplication circuit 64 fades in the input from Fi2. Reference numeral 65 denotes an adder circuit that adds the outputs of the multiplier circuits 64 and 62, and this output FO provides a digitally crossfaded signal. In this way, a signal crossfaded at the editing point is obtained at the output of the fade processing circuit 16. Through the above process, if the rehearsal is completed and there is a problem with the connection of sounds near the editing point, repeat the process starting from the step of determining the editing point in memory, and if a suitable editing point is obtained, proceed to the next editing step. .

Editing involves recording the same signal that has been rehearsed in memory onto the actual tape, but the signal played back by the playback head that precedes the recording head of the recording tape recorder and the tape on the playback side are combined. The timing of the signals reproduced by the playback head of the recorder is adjusted by appropriate delay circuits, and the recording head of the recording tape recorder has just come into contact with the first position of the crossfade period shown in Fig. 2b. At the moment when the signal is reproduced from the first position of the A crossfade of the second tape in FIG. 2b on the recording tape recorder and the D section of the first tape in FIG. 2a on the playback tape recorder. The signal reproduced from the first position of the crossfade period is processed by the crossfade processing circuit 16 in FIG.
The signal passes through the interpolation circuit 17, is output to the W terminal, and is supplied to the recording head, thereby combining the previously recorded signal near the editing point and the newly recorded signal due to editing work. will be connected correctly. At this time, switches 15, 15'
Naturally, b-c and b'-c' are ON.

The exact edit point on the tape is determined by the CPU as described above.
4, the synchronous running of the tape, the delay amount of the delay circuit, the crossfade timing, etc. are all performed by commands from the CPU 4. Crossfade processing circuit 1
The operation in step 6 is exactly the same as in the case of rehearsal. When the above process is completed, the second tape shown in FIG. 2c is completed, and the editing work is completed.

In this way, since editing is done at the audio PCM signal stage itself, regardless of the recording format of the tape deck, information may be missing due to hand-cut editing when newly reconstructed and recorded on the recording tape recorder. It doesn't happen at all.

As detailed above, according to the present invention, (i) the editing work of the PCM tape recorder, which conventionally involved some kind of information loss, can be edited without any errors; (ii) the audio data stored in the memory can be edited. There are no negative effects caused by variable speed playback, and editing points can be determined using exactly the same operations as editing on conventional analog tape recorders. A digital audio editing device can be obtained which has the following features: (iv) editing can be performed with sampling pulse accuracy by using a time code and sampling pulse in combination;

[Brief explanation of the drawing]

Figure 1 shows the concept of conventional analog editing.
FIG. 2 is a diagram showing the concept of the system adopted in the digital audio editing device according to the present invention, FIG. 3 is a block diagram of the digital audio editing device according to the present invention, and FIG.
The figures show the writing state of the memory 9 in Fig. 3, Fig. 5 is a conceptual diagram of interpolation, Fig. 6 is an explanatory diagram of the interpolation function, Fig. 7 is a block diagram of the interpolation circuit, and Fig. 8
9 is a diagram showing the write state of the memory 12 in FIG. 3, FIG. 9 is a diagram showing the temporal correspondence of the memories in FIGS. 4 and 8, and FIG. 10 is a detailed block diagram of the crossfade processing circuit in FIG. 3. Figure, 1st
FIG. 1 is a diagram showing how the output of the fade curve generating circuit shown in FIG. 10 is subjected to D/A conversion. 4... CPU, 5... ROM, 7... operation input section, 7'... control output section, 9... first memory,
10... first memory address counter, 12...
... second memory, 13 ... address counter of second memory, 15, 15' ... first and second switching means, 16 ... crossfade processing circuit,
17...Interpolation circuit, 18...D/A converter, 21
...Speaker, 22 ...Clock generation circuit, 23
...Manual clock generator, 41, 42, 45...
Latch circuit, 46... Reference clock pulse generation circuit, 47... Counter, 45... Slope coefficient generation circuit, 49... Multiplication circuit, 50... Addition circuit, 61... Fade curve generation circuit (fade out means) , 63...Fade curve generation circuit (fade-in means).

Claims (1)

[Claims] 1. In a digital audio editing device that edits a digital recording tape recorded by a digital recording/playback device and records its output by a digital recording device to create an edited tape, the first tape to be edited is played back and converted into an audio signal. a first memory means for storing the reproduced first tape digital signal; a means for controlling writing/reading of the memory according to an external timing signal; and a first memory means for storing the reproduced first tape digital signal; means for converting and monitoring the reproduced signal into an audio signal; a second memory means for storing the digital signal of the reproduced second tape; and controlling the writing and reading of the second memory means by an external timing signal. manual clock pulse generating means for changing the frequency of the clock pulse for reading the first memory and the second memory in accordance with the speed of moving the manual operating means; and storing a specific address of the first memory. means for storing a specific address of the second memory; means for successively reading out the contents of the first memory and the second memory and converting them into audio signals based on the contents of the storage means; means for specifying and storing positions on the first and second tapes corresponding to the specific addresses of the first and second memories; The output of the second tape is digitally faded out near the position, the output of the second tape is digitally faded in near the second tape position, and a signal obtained by digitally combining them is recorded on the editing tape. Digital audio editing device.