JPS5850683A - Electronic editing device of digital sound - Google Patents

Abstract

PURPOSE:To realize the repetitive edition and monitoring and to facilitate the selection of an editing point, by inserting another signal between the reproduced signals and reading out the inserted signal after storing it once to perform the edition. CONSTITUTION:The reproduced signal of a tape 1 is fed to a terminal P1, and the tape 2 is fed to a terminal P2 at a point preceding L1. The tapes 1 and 2 are driven synchronously with each other to record the signal. The signal E of a memory incorporated into the main body of an editing device is inserted for time T from the boundary between A and B of the tape 1. The signal E is then switched to D of the tape 2 to obtain the 3rd editing tape. The signals of tapes 1 and 2 are once recorded cyclically in a memory 12 and then read out to be edited. The recording is carried out through a terminal R, and a fading process is performed at the boundary between A and E to have an addition. The same procedure is carried out at the boundary between E and D. This process is performed through a cross fade processing circuit 15 and by means of the time code signal of the tape.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital audio electronic editing device for editing a digital signal reproduced by a digital recording/playback device or the like, which eliminates signal loss at editing points, and
The purpose is to insert digital data from the built-in memory to obtain a natural audible sensation at the editing point.

Traditionally, when editing analog recorded tapes, the useful parts of the recorded tapes were manually cut and spliced together.
They have been hand-cut and edited into book tapes. This situation is shown in FIG. In Figure 1, 1/ and 2/ are different parts of the recorded tape, part A of 1' is the necessary part, part B is the unnecessary part, part 0 of 2' is the unnecessary part, and part D is the unnecessary part. The part is the necessary part. Desired tapes 3' can be obtained by cutting these tapes and mechanically connecting them at δ. At this time, the cutting positions of tape 1/, 2/, that is, A, B, and C
，! :D boundaries (hereinafter referred to as editing points) need to be found, and for this purpose the following operations were required. That is, the tape recorder is put into a playback state, and while listening to the playback sound, the tape recorder is stopped at a position that appears to be an editing point. In order to find a more accurate editing point, manually rotate the tape recorder's take-up reel and supply reel in the same direction, forward or reverse, and listen to the playback sound to judge. decide. In other words, when the tape is in contact with the gap of the playback head when it is judged to be the desired editing point after making such fine adjustments, it is set as the correct editing point. The reason why the tape is cut diagonally as shown in Figure 1 is to prevent the playback sound from becoming discontinuous at the editing point when the edited tape is played back.
This is because the effect is that the sound of the D part gradually becomes smaller (fade out) and the sound of the D part gradually becomes louder (fade in). This connection process is called 70 sphate.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying it to digital recording and playback devices that have been put into practical use in recent years. In other words, since the recorded signal in a digital recording/playback device is a digital signal, cutting diagonally like an analog signal means that meaningless information continues for that period, and it is obvious that this will have a harmful effect on the reproduced sound. be. On the other hand, in order to reduce the amount of information lost as much as possible, even when the tape is cut perpendicular to the direction of tape progression, digital recording and playback devices usually add errors and corrections to the information bits of the sample and perform IPCM. Since it is recorded as a frame, errors in the IPCM frame are unavoidable.Therefore, it is necessary to perform operations such as (a) muting that part, (b) skipping that part and connecting the preceding and succeeding information, In any case, the deterioration in the sound quality of the original information in that part is essentially a problem.

The present invention solves the above-mentioned conventional drawbacks, and eliminates signal dropouts and discontinuities at editing points to achieve accurate editing, and also enables the creation of a third digital data that is different from the two digital data that should be originally connected. To provide a digital audio electronic editing device that can insert data into editing points and edit audibly natural and smooth connections.

An embodiment of the present invention will be described below based on the drawings. First, an outline of the editing method of the digital audio electronic editing apparatus of the present invention will be explained. In this method, the recorded tape is not mechanically cut, but three digital recording and playback devices are used, and the digital signal played by the first digital recording and playback device is played back up to the editing point, and then a certain signal is The edited tape is then switched to the reproduced digital signal of the second digital recording/reproducing device and recorded on the third digital recording/reproducing device. This will be explained with reference to FIG.

That is, in FIG. 2, (a) is the first tape 1 attached to the first digital recording/playback device, and (b)
) is the second tape 2 mounted on the second digital recording/playback device. (C) is data 3 stored in the memory built into this device. (d) is a third tape for recording the edited digital signal, and is attached to a third digital recording/playback device. First, the first tape loaded in the first digital recording/playback device is rewound a little more than the starting point 4 of the necessary portion A, and at the same time, the second tape 2 loaded in the second digital recording/playback device is rewound. is rewound L2 +T before the boundary between C and LD. Then, when the first tape 1 is played back and reaches the starting point 4 of A, the third tape attached to the third digital recording/playback device is put into the recording state, and the first tape 1 is played back.
Record part A of and the first tape 1 is A and B
The second tape 2
Play. Here, T is the second tape inserted between the boundary between A and B of the first tape 1 and the boundary between C and D of the second tape 2.
This is the time of data E in Figure (C). Ll and L2 are the CI! of the second tape 2 at the moment when the playback head of the first digital recording/playback device comes into contact with the boundary between A and B of the first tape 1. : Sufficient length to run the first tape 1 and the second tape 2 synchronously so that the playback of the second digital recording and playback device comes into contact with the position one hour before the boundary of D. That's fine. Here, it is assumed that ==L2.

Next, the data is switched from the boundary between A and B of the first tape 1 to data 3 in the memory built into the apparatus, and this data is recorded on the sth tape for one hour.

One hour after switching to said memory, i.e. the 29th
The second tape runs for one hour on the reproducing head of the digital recording/reproducing apparatus, and the boundary between C and D in FIG. 2(b) is in contact with the reproducing head. Therefore, at this time, the input of the third digital recording/reproducing device is switched, and thereafter, the portion D of the second tape is recorded on the third tape.

That is, the first tape and the second tape are run synchronously, and the digital signal to be recorded on the third tape is transferred from the boundary between A and B of the first tape to the digital signal (second By inserting E) in Figure (C) for one hour and then switching to tape D in tube 2, a third edited tape as shown in Figure 2(d) can be created.
At this time, at the boundary between A and E, A is faded out and E is faded in by digital calculation, and the faded signals are added. Similarly, at the boundary between E and D, cross-fade processing is performed at 0, that is, the signal switching point, where E is faded out, D is faded in by 7, and the faded signals are added. Furthermore, these operations are performed using a time code signal recorded on another track on the tape.The present invention realizes a digital audio electronic editing device based on the above-mentioned idea, and the embodiments will be described below. Give a detailed explanation. In FIG. 3, 6 is a CPU (microcomputer) that controls this device;
ROM in which the program of CPU 6 is stored, 7 is C
RAM that stores data required by PU5, 8 is data storage (address male is omitted in the diagram)
, 9 is an operation input section for giving control commands to this device, 9
' is a control output unit for outputting a display to show that the CPU has received an operation input or a control signal to control other parts of this device;
This is an interface element for interfacing the CPU 5 with the CPU 5. On the other hand, Pl and P2 are the first
and a PCM data input terminal from a second digital recording/reproducing device (hereinafter referred to as a PCM tape recorder).

11 is a switch controlled by the output of the control output section 9' from the CPt 15 via the interface element 10;
2 is a memory for writing and storing PCM data via the switch 11; 13 is an address counter for the memory 12;
4 is an interface element that interfaces the address counter 13 and the CPU 5; 15 is an input terminal P; PCM data of the first PCM tape recorder input from the input terminal P2; PCM data of the second PCM tape recorder input from the input terminal P2; This is a cross-fade processing circuit for generating a cross-fade by digitally calculating the PCM data in the built-in memory. Reference numeral 16 denotes an interpolation circuit for preventing the clock frequency from being mixed into the reproduced audio as noise when the memory is read at a clock frequency lower than the original sampling frequency. 17 is a switch for switching either the output of the cross-fade processing circuit 16 or the interpolation circuit 16 according to the output of the control section 9; 18 is a D/A converter; 19 is a low frequency filter; 20 is an amplifier; 21 is a monitor speaker. R is an output terminal to the third PCM tape recorder (recording side tape recorder). 22 is a reference clock pulse generation circuit, 23 is a manual clock pulse generator,
A switch 24 selects and switches between the outputs of the reference clock pulse generator 22 and the manual clock pulse generator 23 according to the output of the control output section 9'.

The TP1 terminal is an input terminal for the SMPTE time code reproduced by the first PCM tape recorder connected to the Pl terminal, 25 is an interface circuit that interfaces the time code input with the CPU 6, and the TP2 terminal is the P2
An input terminal for the SMPTE time code reproduced by the second PCM tape recorder connected to the terminal, and 26 is a time code-interface circuit that interfaces the above-mentioned time code input and the CPU 6.

Next, the operation of this embodiment will be explained based on FIG. 3 as well.

As a premise, the tape attached to the first PCM tape recorder connected to the Pl terminal is the first tape explained in Fig. 2, and the second PCM tape recorder connected to the P2 terminal is attached to the same second tape. The third PCM tape recorder connected to the R terminal is also assumed to be the third tape. and a first playback side tape recorder,
They will be referred to as a second playback tape recorder and a recording tape recorder. To create the third tape shown in FIG. 2(d), first the edit point, that is, A of the first tape shown in FIG. 2(a) is created.
It is necessary to find the exact position of the starting point 4 of the second tape C9D and the boundary of the second tape C9D shown in FIG.

Next, the operation for determining the editing point will be explained.

First, in order to determine the starting point 4 of A, the first reproducing side tape recorder reproduces the portion of the first tape before point 4 and inputs it to the P1 terminal. At this time, the switch 11 has gh turned on, and when PCM data is input to the P1 terminal, this data is transferred to the memory 12 via the switch 11.
recorded cyclically. In other words, once writing is completed to the last address in the memory 12, writing starts again from the first address.As a result, if we take a certain moment, the PCM data stored in the memory 12 will always be stored for a certain period of time from that moment. The previous data will be stored continuously. The address of this memory 12 is controlled by an address counter 13. This counter 1
As the clock pulse No. 3, the clock pulse generated from the reference clock pulse generation circuit 22 is supplied by turning on the switches 24 e to d.

Furthermore, the switches a and b of the switch 17 are turned on, and the input PCM data passes through the cross-fade processing circuit 15 and is converted into the original analog signal by the D/A3 converter 18 via the switch 17. The high-frequency components are cut by the low-pass filter 19, and the amplifier 20
The signal is amplified and supplied to the speaker 21, and the audio from the first playback tape recorder is monitored.

Control of each of the above parts, for example, switches 11, 17.　　.

The polarity of 24, disabling of cross-fade processing circuit 15, etc. are all controlled by signals from control output section 91. That is, signals from the operation input unit 9, which is composed of keyboard push buttons, etc., are transmitted to the interface element 10.
．． It is transmitted to the CPU 5 via the pass line 8, and a corresponding control signal is output from the CPU 5 via the pass line 6 and the interface element 1o from the control output section 9', and the control is performed using this signal. In FIG. 3, control lines other than the switches from the control output section 9' are omitted. The editor sends a signal from the operation input section 9 indicating that it is the timing to edit while monitoring the output audio from the speaker 21. The input 0 signal is transmitted to the CPUts via the above-mentioned path, and the following control is performed via the control output section 49'. First, the operation continues for a certain period of time from an editing point desired by the editor, and after the certain period of time, writing to the memory 12 is stopped.

Thereafter, the tape running of the tape recorder on the reproduction side of tube 1 is stopped. Control of the tape recorder is carried out by instructions from the CPU 6, but all are omitted in the figure. Now, the contents of the memory 12 at this time are as shown in FIG. Here, the specifications are assumed as follows. Audio data is 16 bits/sample, sampling frequency is 50KHz, memory is 256
KW (IW = 16 Pinot), if you do this, memory 1
The audio data stored in 2 is 256/6ox=es
This is about 6 seconds from the second. Of course, in order to save memory, data may be stored in the memory every other sample (this means that the sampling frequency is halved). Alternatively, a method such as reducing the number of bits per sample using a bit compression method may be applied.

In this case, to simplify the explanation, such processing will not be performed at all. In Figure 4, a memory of 26616 KW is simulated, and audio data is written sequentially from left to right, and when it is written up to 2FFFF, it is oo again.
Writing starts from ooo, and this is repeated.

The memory address corresponding to the timing desired by the editor is represented by an X in the figure. Then, writing is completed at a timing corresponding to the Y memory address delayed by, for example, 4 seconds within the repetition cycle as a fixed period of time. As a result, the memory 12 stores (Y+1) →2FFFF →00000.
This means that the audio is recorded in the order of -Y.

Next, in order to search for the correct editing point, the contents of the memory 12 are read out, and by setting the device to the editing point search mode from the operation input section 9, the editor can send control signals to each section. becomes as follows. In the switch 17, a-c is turned on, and in the switch 24, d-f is turned on. Reference numeral 23 denotes a manual clock pulse generator composed of a rotary encoder or the like, and the frequency of the pulses generated changes depending on the speed of movement, and if it is stopped, no pulses are generated at all. If a rotary dial, for example, is used as the manual control means, the higher the rotation speed, the more pulses will be generated. If this pulse and information on the rotation direction are given to the address counter 13 and it operates as an up/down counter, for example, when the rotation is clockwise, the memory is moved in the forward direction, that is, x
Addresses are set in the order of -Y and the contents of the memory 12 are read out.

The read PCM data is interpolated by the interpolation circuit 16, converted to the original analog signal by the D/A converter 18 via the switch 17, and the high-frequency component is cut by the low-pass filter 19. The output signal is amplified by an amplifier 2o, and supplied to a speaker 2°, where the editor monitors the sound. The faster the rotary dial is rotated, the higher the frequency of the audio to be reproduced becomes. When rotating counterclockwise, X-0000-2F F F
The sound is played back in the order of F-(Y+1), and the sound is played back as if it had been recorded -1 and the arp of a tape recorder was turned in reverse. At this time as well, it is natural that the frequency of the re-tonic changes depending on the rotational speed. In the case of variable speed reproduction of audio sampled at 50 KHz and stored in memory, the following problems arise.

That is, there is no particular problem when reproduction is performed at a clock frequency of 50 KHz or more, but when reproduction is performed at a frequency lower than 50 KHz, for example 10 KHz, the clock frequency is 10. A KHz component is generated. However, the cutoff frequency of the low-pass filter 19 is, for example, 20KH.
This is the optimum value when the sampling frequency is 50 KHz. Therefore, the 10 KHz component is not removed by the low-pass filter 19 and is heard as noise. In order to solve this problem, the interpolation circuit 16 is operated.

Next, the function of the interpolation circuit 160 will be explained with reference to FIG. FIG. 5 (-) shows the audio signal stored in the memory reproduced at normal speed, that is, 50 KHz, and subjected to D/A conversion. When the same signal is reproduced at 10 KHz and subjected to D/A conversion, the result is as shown in FIG. 5(b). Here, Fig. 6(a)
, 8 points in (b) indicate the same sample. The purpose of this circuit is to smoothly correct the discontinuous portions of these signals by 5QKMz as shown in FIG. 6(c).

First, the concept of interpolation will be explained. Figure 5(b),
An enlarged view of a part of (C) is shown in FIG. In FIG. 6, 31 is an input to the interpolation circuit. a and b are outputs read from the memory, and are sample values of temporally adjacent samples 0T1o.

T2O is the timing of the manual clock pulse, and T2° is the timing one clock period after T1°.

T101 T111 ”121 T131 T141
T20 is the timing of seven pulling clock pulses. 32 is the output of the interpolation circuit 16. Tln(n-0
, 1゜2.3.4), the output of the interpolation circuit 16 "In
can be determined as follows.

L1n=a+(ba-a)on@k −・===(1
) Here, k is a coefficient (slope coefficient) that is inversely proportional to the frequency of the output of the manual clock pulse generator 23. For example, if it is simply determined in the case of FIG.
output is 10KHz, sampling frequency is 50KHz
Therefore, it is set to 115'. (In equation 1, k=1/
It can be seen that if s, n = 6.1, 2, 3 degrees 19 4, 32 interpolations in FIG. 6 can be performed.

A block diagram for realizing the above functions is shown in FIG.

FIG. 7 shows a block diagram of the interpolation circuit 16. Reference numeral 52 is a 16-pit parallel signal input to the interpolation circuit, terminal is a terminal to which the output of the manual clock pulse generator 23 is input, and 54 is a sampling clock (50 KHz in this case) input. It is a terminal. 41.42 is a latch circuit, 43 is a latte circuit 4
1 is a subtraction circuit that subtracts the output of the latch circuit 42 from the output of 1, 44 is an adder circuit, and 45 is a latch circuit that latches the output of the adder circuit 44 using a sampling clock. 46 is a reference clock pulse generation circuit (for example, 50KH
z x 100 = 5 MHz clock pulse). 47 is manual clock pulse generator 2
A counter 48 counts the output of the reference clock pulse generation circuit 46;
49 is a circuit that uses the output value of the counter 47 as an address and outputs the contents of the ROM corresponding to that address to generate a slope coefficient k. A circuit that multiplies the slope,
5o is an adder circuit that adds the output of the multiplier circuit 49 and the output of the latte circuit 42, and 61 is a polarity determining circuit that latches the polarity bit of the output of the latte circuit 43 and determines the polarity of the multiplier circuit 4e. 65 is the output of the interpolation circuit.

The outputs of the latch circuits 41 and 42 correspond to a and a in FIG. 6, respectively. The output of the subtraction circuit 43 is (1)
(ba) in the formula. Furthermore, the output (ba)Xn is obtained by the combination of the adder circuit 44 and the latch circuit 45. Since the frequency of the output of the reference clock pulse generation circuit 46 is 5 MHz and the frequency of the output of the manual clock generator 23 is 10 KH2, the output of the counter 47 is 6 MHz.
It becomes 00.

At this time, 1001500=1/cs is outputted as the output of the slope coefficient generation circuit 48 constituted by a ROM, for example. That is, if the output of the counter 47 is Z, then -7- is k. As a result, the output of the multiplier circuit 49 is (ba)・
nφk is obtained. Furthermore, as the output of the adder circuit 50, 0)
The formula a + (b - a )·n·k is obtained. Therefore, the dotted line 32 in FIG. 6 is obtained as the output 65 of the interpolation circuit.

Here, depending on the magnitude relationship between a and b, the polarity bit passes through the polarity determining circuit 61 and changes the sign focus of the multiplication circuit 49.

In addition, in FIG. 7, the second term of equation (1) is (ba)
Although the configuration is such that Xn is calculated first, depending on the hardware, overflow may occur at this stage, so if the configuration is configured to calculate kxn first, this risk will be eliminated.

As described above, the output of the interpolation circuit 16 shown in FIG. 3 is obtained, and the sound reproduced at variable speed from the speaker 21 via the D/A converter 18, the low-pass filter 19, and the amplifier 20 can be monitored. At this time, if you turn the rotary dial in the forward or reverse direction, you will hear exactly the same playback sound as when you manually rotate the reel of a conventional analog tape recorder in the forward and reverse directions.

In this way, the rotary dial is stopped at the point to be edited, and a signal indicating that the point is the editing point is given to the CPLJs. This means that the position of the starting point 4 of A in FIG. 2 has been determined. In order for the CPU 5 to recognize this position, the following process is performed. First, the time code input signal from the TP1 terminal, which is input at the same time as the timing PCM data that is the editing point given by the editor, is sent to the time code interface 26 and the pass line s'&H to cpt.
J5 reads it and saves it to RAM7. Here SMPT
In the E-time code, the minimum signal unit is a frame (1/30 second), so to increase the editing accuracy beyond this, it is necessary to count the audio sampling pulses within the frame and calculate the number of samples within the frame. It is also necessary to read this information by the CPU and store it in the RAM 7, but this counter is omitted in FIG. 3 and is included in the time code interface circuit 26. Therefore, at this point, the CPU 5 reads information on hours ψ minutes, seconds, frames, and samples. Next, in the edit point search mode, the address counter 13 and the time code interface 25 are activated by the output of the manual clock pulse generator 23.
23 The CPUs will read the manually corrected time code information of the correct edit point and the sample information in finer frame units, that is, the hour, minute, second e-frame sample information. . (Not shown) Let this information be SPl. In this way, the location in memory 12 of the exact sample point,
The boundary between the first tapes A and B in FIG. 2(a) is determined at the zeroth order in which the CPUs have information about the position on the tape. In the same way as described above, the editor inputs a signal to that effect from the operation input section 9 at the timing when he wants to edit, that is, near the boundary between A and H of the first tape, while monitoring the output audio from the speaker 21. . After that, writing continues in the memory 12 for a certain period of time, and the process is the same until it stops. However, in this case, if the capacity of the memory 12 is approximately 5 seconds, the time from the designated point is shorter than half of the 6 seconds. When time elapses, for example, one second, writing to the memory 12 is stopped. Notes from when I was at home 1) Figure 8 shows the inside of 12, where x and Y correspond to xPl and YPl, respectively. The operation of searching for the correct editing point in the memory 12 is the same as described above, with the switch 17 turning a-b ON, the switch 24 turning d-f ON, and when the dial is rotated in the forward direction, the contents of the memory 12 become XPl. -Plays in the order of YPl, and when rotated in the opposite direction, xPl-ooooo-
It is reproduced in the order of 2FFFFF-(Yp1+1). In this way, the audio is played back as the rotary dial rotates, so it is possible to stop the rotary dial at the correct position and designate this point as an editing point. The position information of this point is read into the CPUs and stored in the RAM 7 by the same operation as in the above case. Let the address of this point on the memory be XP1+NP1. Also, as described above, the time code information and sample point information of the manually corrected accurate editing point are set as EPl.

Next, the edit point set above (address XP in memory)
1+NP1) is correct or not, the contents of the memory 12 are continuously read out and monitored using the reference clock for the specified number of down passes. By setting to monitor mode, each part is controlled as follows. The switch 17 has a-c set to O.
Then, the switch 24 turns d-e ON. Also C,
P U 5 presets address counter information YP1 stored in RAM 7 as an initial value in address counter 13 via data bus 8 and interface element 14 .

A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 changes the address in the order of YP1 → 2FFFF → ooOoO-Xp, +Np1 based on the instructions from the CPU 6 and reads out the memory 12, and at the same time, this address is input to the cpucs via the interface element 14. The digital signal read out from the memory 12 passes through the interpolation circuit 16 and then passes through the switch 17 .

The signal passes through a D/A converter 18, a low-pass filter 19, and an amplification unit 0, and is then monitored by a speaker 21 as a continuous audio signal.

In the edit point memory/pre-monitor mode described above, if there is a problem with fish collection, repeat the process starting from the process of determining the edit point in memory, and if a suitable edit point is obtained, proceed to the next step.

Next, in order to determine the boundary between the second tapes C and D in FIG. 2(b), the second tape recorder plays back part 2 of the second tape and inputs it to the P2 terminal. At this time, q-1 of the switch 11 is ON, and when PCM data is input to the P2 terminal, this data is cyclically recorded in the memory 12 via the switch 11.

Since the subsequent steps are the same as those for determining the starting point 4 of the first tape shown in FIG. 2(a), the explanation will be omitted. The X and Y in Figure 4 set here are xP2 and YF3, respectively.
and the address 'iil- in the memory 12 at the editing point is
xP2 + NP2 + time code information and sample points.

Let the information be EP2.

Next, the edit point set above (address XP in memory)
2+NP2) is correct or not, the contents of the memory 12 are continuously read and monitored for the specified addresses using the reference clock, but the editor 27 enters the editing point memory pre-monitor mode from the operation input section 9. With these settings, each part will be controlled as follows. Switch 17 a-C is turned on,
As for the switch 24, de is turned on. In addition, the CPU 5 is
Address counter information YP stored in RAM7
2+1, data bus 8. The address counter 13 is preset as an initial value via the interface element 14.

A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 reads Y P 2 + 1-2 F F F F → ooooo based on the instruction from the CPU 5.
At the same time as reading out the memory 12 by changing the address in the order of o→xP2+NP2, this address is input to the CPU 6 via the interface element 14. The digital signal read out from the memory 12 is sent to the interpolation circuit 16.
, and switch 17. D/A converter 1.8. The signal passes through a low-pass filter 19° and an amplifier 20 and is monitored as a continuous audio signal from a speaker 21.

If there is a problem with the edit point in the above edit point memory pre-monitor, the process starting from the process of determining the edit point in the memory is repeated, and if a suitable edit point is obtained, proceed to the next step.

Here, before setting each editing point mentioned above, insert (c) between the first tape A and the second tape D in Fig. 2.
The PCM data of E is stored in the built-in memory of this device.

Here, the PCM data E is preferably low-level continuous sound such as natural background noise or random noise.

FIG. 9 is a detailed block diagram of the cross-fade processing circuit 16 in FIG. 3. Fil is P1 in Figure 3
PCM data input from terminal.

Fi2 is PCM data input from the P2 terminal as well. CK is a PCM data clock and is input to a 66 address counter and other circuits.

The address counter 66 is a counter that sets the address of the memory 67, and 66 is a switch that switches the PCM data input from Fil and Fi2 and inputs it to the memory 67. Therefore, the editor inputs an input from the operation input section 9 to the CPU 5 to play the first playback tape recorder or the second playback tape recorder stored in the book and store it in the memory 67 via the switch 65. do. Here, the CPU 5 controls the polarity of the switch 66 and controls the address counter 6 in the direction in which the PCM data is input.
A start signal of 6 and a write mode signal of memory 67 are outputted from the control output section 9'. By performing the above operations, the necessary data in the memory 67 (Fig. 2(c)
) is stored and completely written into the memory 67 for one hour, the CPU 5 stops the writing state of the memory 67 via the control output section 9'.

Next, without recording on the actual tape, the first and second reproduction side tape recorders are run to perform a tape pre-monitoring operation. When the editor sets this device to tape pre-monitor mode from the operation input section 9,
In response to a command from the CPUes, the first tape recorder on the playback side rewinds the tape by the amount of time necessary for the editing point (for example, L1 in FIG. 2). In addition, the second playback side tape recorder selects the edit point EP.
From 2, rewind T time + time required for monitoring time required for molecular synchronization travel control (for example, L2 + T in Figure 2), set it to playback state, and set the PCM data 1 hour before the edit points EP1 and EP2 found above to be the same. Each tape is synchronously controlled so that it is input to the P1 terminal and P2 terminal in FIG. 3 at the same time, and the timing is adjusted by an appropriate delay circuit. First, only the signal A in FIG. 2 (-) is passed through the cross-fade processing circuit 15.

Next, when the editing point of the first tape in FIG. 2(a) is reached, a cross-fade is performed, and the cross-fade process will be specifically described here.

Reference numeral 61 in FIG. 9 is a fade curve generating circuit that generates a fade out curve, and its output is input to a multiplication circuit 62.
The multiplication circuit 62 receives PCM data input from Fil,
0 or 70, which performs digital calculations on the output of the fade curve generating circuit 61 to fade out the PCM data from the filter and input it to the adding circuit 63, is a fade curve generating circuit 69 that generates a fade-in curve, and a fade curve generating circuit 69 that generates a fade-out curve. This is a switch that switches the signal of the curve generation circuit 71 and inputs it to the multiplication circuit 68. The multiplier circuit 68 performs a digital operation on either the PCM data stored in the memory 67 or the output of the fade curve generating circuit 69.71, fades in or out the PCM data from the memory 67, and outputs the PCM data from the memory 67 to the adder circuit 6.
Enter 3. The adder circuit 63 digitally adds the two faded inputs and inputs the result to the adder circuit 64. Reference numeral 72 denotes a fade curve generation circuit that generates a fade-in curve, and its output is input to a multiplication circuit 73. The multiplication circuit 73 digitally operates the PCM data input from Fi2 and the output of the fade curve generation circuit 72. 1 calculation is performed and the PCM data from Fi2 is faded in and input to the adder circuit e4. The adder circuit 64 digitally adds the output of the adder circuit 63 and the output of the multiplier circuit 73 to obtain an output F0. This F. is input to switch 17 in FIG.

Now, here, CPU5 is the PC input to P1&, J child.
The M data is passed through the cross-fade processing circuit 15 shown in FIG. 3 until the information input from the interface circuit 26 to the time code becomes the same as the edit point "Pl" obtained above, but the above-mentioned respective pieces of information match. Then, the ninth
A start signal is output to the fade curve generating circuit 61 from the control output section 9'. Then, the 7-work curve generation circuit 61
generates a digital signal consisting of a fade-out curve. The multiplication circuit 62 is connected to the fade curve generation circuit 61 and Fi
The PCM data inputted from I, that is, A, is calculated, and the PCM data A is faded out.

The CPU 5 also controls the switch 7° from the control output section 9'.
bKON outputs a start signal to the address counter 66 and fade curve generation circuit 69, and also outputs a start signal to the memory 67.
is in the read state, and only the signal input from the adder circuit 63 is input to the adder circuit 64. 3 Set to output state. The multiplication circuit 68 receives the PCM data E stored in the memory 67 by the address counter 66.
(background noise, etc.) and a digital signal consisting of a fade-in curve of the fade curve generating circuit 69 obtained via a-b of the switch 70, and fade-in the PCM data E. The added circuit 63 adds the faded out A and the faded in PCM data E. The added PCM data is added to the adder circuit 64.
It passes through and outputs to Fo.

Therefore, here, the A reproduced by the first reproducing side tape recorder and the PCM data E read from the memory 67 are cross-faded. Next, when the cross-fade is completed, CPtJs sets the multiplication circuit 68 from the control output section 9' to a state where the signal input from the memory 67 passes through,
The adder circuit 63 is brought into a state in which only the signal input from the multiplier circuit 68 is allowed to pass through. Therefore, the PCM data E (background noise, etc.) read from the memory 67 is outputted to Fo via the multiplication circuit 68° and addition circuits 63 and 64.

Next, after reading the memory 67 for one hour, the CPU 5 turns on the switch 70 from the control output section 9 to a to c.

Further, the adder circuit 64 is set to add the signal input from the adder circuit 63 and the signal input from the multiplier circuit 73, and the multiplier circuit 68 is set to add the signal input from the memory 67' and the signal input via the switch 7o. The state is set in which the signal is calculated. Furthermore, a fade start signal is output to lines 71 and 72 for the fade track. Then, the multiplier circuit 68 operates on a digital signal consisting of the PCM0M del read out from the memory 67 and the fade-out curve of the fade curve generating circuit 71 obtained through the a-c of the switch 70, and fades out the PCM data E.

This signal then passes through the adder circuit 63 and passes through the adder circuit 64.
is input.

~ side Fi2 contains the PCM data C, ! in Fig. 2 Φ) reproduced from the second reproduction side tape recorder. :D boundary PC
M data D is input. The multiplication circuit 73 is connected to the PC
A digital signal consisting of the M data and the fade curve obtained from the fade curve generating circuit 72 is operated, and the PCM data D is faded in and inputted to the adder circuit 64. The adder circuit 64 adds the faded-out PCM data E and the faded-in PCM data D. Output to.

Therefore, the PCM data E (background noise, etc.) read from the memory 67 and the PCM data D reproduced from the second reproduction side tape recorder are cross-faded.

Next, when the cross-fade is completed, the CPU 5 controls the multiplication circuit 73 from the control output section 9' so that the PCM data inputted from Fi2 passes through, and also controls the addition circuit 64 so that only the signal inputted from the multiplication circuit 73 passes through it. By controlling the PCM data D input from Fi2, the multiplication circuit 73. F passes through the adder circuit 64.

is output to.

10 shows the level waveform of the digital signal processed by each circuit in FIG.
Figure 0 Φ) is a waveform obtained by fading in and out the PCM data E (background noise, etc.) in Figure 2 (C) read out from the memory 67 by the multiplication circuit 68, and Figure 10 (C) is the waveform of the multiplication circuit. 73, the waveform of D in FIG. 2(b) is faded in, and FIG. 10(a) is the waveform shown in FIG.
Output F obtained by adding the waveforms of (b) and (C) by the adder circuit 64. This is the waveform of

In this way, by the cross-fade processing circuit 15, each PC
M data A-, crossfade A and E → E, E and D
Switch to crossfade-D and send the crossfaded signal to switch 17. D/A converter, low pass filter 19.
The output audio of the speaker 21 is monitored via the amplifier 20.0 Since the exact editing point on the tape is stored in the RAM 7 as described above, the synchronized running of the tape, the amount of delay of the delay circuit, and the timing of the crossfade are etc. are all CPU
This is done by command from 6.

Through the above process, the tape pre-monitor operation is completed. If an editing point is obtained in the connection of sounds near the editing point, the process proceeds to the next editing step.

In the editing work, the operation near each editing point is the same as that of the tape pre-monitor, but the editing work is performed by playing back the necessary parts of the first tape and the second tape in Figure 2 and then playing the third tape. Therefore, the first playback tape recorder must be set to A of the first tape in Figure 2 (-).
Rewind to just before the starting point 4. In addition, the second playback side tape recorder is connected to C and D of the second tape in Fig. 2(b).
Boundary editing Rewind by L 2 + T time from AEP2. Then, the first playback side tape recorder is played back, and the PCM at the starting point 4 of A in FIG.
When data is input, the recording side tape recorder connected to the R terminal is put into a recording state.

Thereafter, by performing the same operations as those of the tape pre-monitor, the data is edited on the recording side tape recorder connected to the R terminal as shown in FIG. 2(d).

According to the above embodiment, since editing is performed at the stage of the reproduced digital 8 signal, there is no possibility of missing information or discontinuity unlike when cutting and splicing a recording tape. Furthermore, since the output of the tape recorder on the playback side is temporarily stored in a memory, and editing is performed while reading and monitoring this memory, it is possible to read the memory many times to check and select editing points. In particular, the readout from the memory can be made manually variable at a variable speed, and since it is also provided with an interpolation circuit, it is possible to play back and listen at a slow speed, and to easily select editing points. Since the positional information of the selected editing point is stored by using a time code and a sampling pulse, it is possible to improve the accuracy of the positional information to the level of sampling.

Background noise generated by the built-in memory is generated between the first playback signal and the second playback signal to be further edited.

A continuous low-level digital signal such as random noise is inserted, and in addition, this inserted digital signal and the first . By performing cross-fade processing on each joint with the second reproduced signal, it is possible to obtain a natural connection to the sense of hearing. Further, as described above, this insertion and cross-fade processing can be repeatedly read out from the memory, corrected and monitored many times, making the actual editing work extremely easy and accurate.

As described above, according to the present invention, by inserting and editing the third digital signal between the first and second reproduced digital signals, an audibly natural connection can be realized at the editing point, Furthermore, by storing each of the above digital signals in memory and editing using the signals read out from this memory, editing and monitoring can be repeated many times, making it easier to select editing points. This allows for accurate and appropriate editing. Furthermore, if the third digital signal to be inserted is a natural low-level noise type, by crossfading this with the previous and subsequent signals, it is possible to obtain an extremely natural connection at the editing point. This makes editing records accurate and easy.

[Brief explanation of the drawing]

Fig. 1' is an explanatory diagram showing the concept of analog editing, Fig. 2 is an explanatory diagram showing the concept of the editing method adopted in the digital audio electronic editing device of the present invention, and Fig. 3 is an explanatory diagram showing the concept of the editing method adopted in the digital audio electronic editing device of the present invention. FIG. 4 is an explanatory diagram showing the write state of the memory 12, FIG. 6 is a waveform diagram explaining the concept of interpolation, and FIG. 6 is a waveform diagram explaining the interpolation function of this embodiment. 7 is a block diagram showing the configuration of the interpolation circuit, FIG. 8 is an explanatory diagram showing the write state of the memory 12, FIG. 9 is a block diagram showing the configuration of the cross-fade processing circuit, and FIG. FIG. 3 is a diagram showing level waveforms at various parts in the figure. 5...CPU e...ROM 7
...... RAM 9... Operation input section, 9'... Control output section, 12... Memory, 13... Address counter 16 ......Interpolation circuit, 18...D/A converter, 22...Reference clock generation circuit, 23.
...Manual clock generator, 61, 69, 71.7
2...Fade curve generation circuit, 62, 68.7
3...Multiplication circuit, 63, 64...Addition circuit, 67...Memory, 66...Address counter, 66...Switch means . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 5 Figure 16

Claims (4)

[Claims] (1) Between the first digital signal and the second digital signal reproduced from a sound source such as a tape or a disk, a third
1. A digital audio electronic editing device which inserts a digital signal and stores it in a storage device. (2) First. The digital audio electronic editing device according to claim 1, further comprising a memory in which the second digital signal is stored and a memory in which the third digital signal is stored. (3) The digital audio electronic editing device according to claim 1 or 2, wherein the third digital signal is background noise or random noise. (4) A means for adding a fade-in characteristic and a means for adding a fade-out characteristic to an input digital signal, and adding these by fading out a first digital signal and simultaneously fading in a third digital signal. Match, number? 2. The digital audio electronic editing apparatus according to claim 1, wherein said digital audio signal is faded out, said second digital signal is faded in at the same time, and said digital signals are added together.