JPH0118519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal editing device for editing digital signals played by a digital recording/playback device, etc., and is capable of smoothly connecting digital signals by performing crossfade processing using a single manual fader. The object of the present invention is to provide a digital signal editing device that can realize accurate editing with easy configuration and operation.

Conventionally, when editing analog-recorded tapes, useful parts of the recorded tapes are cut out by hand and then spliced together to form a single tape. The situation is shown in Figure 1. In Figure 1, 1' and 2' are parts of different recorded tapes, part A of 1' is the necessary part, and part B of 1' is the necessary part.
Part C is an unnecessary part, part C of 2' is an unnecessary part, and part D is a necessary part. A desired tape 3 can be obtained by cutting these tapes and mechanically joining them together. At this time, the cutting positions of tapes 1' and 2', that is, A, B, and C.
It is necessary to find the boundary between and D (hereinafter referred to as the editing point), but for this purpose the following work is required. That is, the tape recorder is put into a playback state, and while listening to the playback sound, the tape recorder is stopped at a position that appears to be an editing point. In order to find a more accurate editing point, the take-up reel and the supply reel of the tape recorder are manually rotated forward or backward in the same direction, and the editing point is determined by listening to the reproduced sound. That is, when such fine adjustments are made and a desired editing point is determined, the position of the tape in contact with the gap portion of the playback head is set as the correct editing point, and the above-mentioned cutting is performed. The reason why the tape is cut diagonally as shown in FIG. 1 is to prevent the reproduced sound from becoming discontinuous at the editing point when the edited tape is played back. This is because the effect is that the sound of section A gradually becomes smaller (fade out) and the sound of section D gradually becomes louder (fade in). This processing of continuous parts is called crossfade.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying it to digital recording and playback devices that have been put into practical use in recent years. In other words, since the recorded signal in a digital recording/playback device is a digital signal, cutting diagonally like an analog signal means that meaningless information continues for that period, and it is obvious that this will have a harmful effect on the reproduced sound. be. On the other hand, even when the tape is cut perpendicular to the direction of tape progression in order to reduce information loss as much as possible, digital recording/playback equipment usually adds error and correction codes to dozens of samples of information bits and converts them into one PCM frame. Due to recording, errors of 1 PCM frame are inevitable. Therefore, it is necessary to perform operations such as (a) mutating that part, or (b) skipping that part and connecting the information before and after it, but in any case, the sound quality of the original information at that part will not deteriorate. This is essentially a problem.

The present invention solves the above-mentioned conventional drawbacks, and provides a new digital signal editing device that enables smooth editing without signal loss or discontinuity at editing points, and enables crossfade processing with a single manual fader. It provides:

An embodiment of the present invention will be described below based on the drawings. First, an outline of the editing method of the digital signal editing device of the present invention will be explained. In this method, the recorded tape is not cut mechanically, but instead three digital recording and playback devices are used, the first digital recording and playback device plays back the digital signal up to the editing point, and then the second digital Switching to the reproduced digital signal of the recording/reproducing device, the third digital recording/reproducing device records the signal to create an edited tape. This will be explained with reference to FIG. That is, in FIG. 2, a is the first tape attached to the first digital recording/playback device, b is the second tape attached to the second digital recording/playback device, and c is the editing tape. This is a third tape for recording the digital signals that have been recorded, and is attached to a third digital recording/playback device. First, the first tape loaded in the first digital recording/playback device is rewound a little more than the starting point 4 of the necessary portion A, and at the same time, the second tape loaded in the second digital recording/playback device is rewound. Rewind L ₂ from the boundary between C and D. Then, the first tape is played back, and when the starting point 4 of A is reached, the third tape attached to the third digital recording/playback device is put into the recording state, and the part A of the first tape is recorded. When the second tape is _L1 minute before the boundary between the first tapes A and B, the second tape is played back. where L ₁
Let L ₂ be the value of A and B of the first tape.
C of the second tape at the moment when the playback head of the first digital recording and playback device comes into contact with the boundary of C,
The first tape and the second tape are placed so that the playback head of the second digital recording and playback device contacts the boundary
It is sufficient that the length is sufficient to allow two tapes to run synchronously.

In this way, by running the first tape and the second tape synchronously and switching the digital signal recorded on the third tape from the boundary between A and B of the first tape to D of the second tape, A third edited tape such as C can be created. At this time, at the boundary between A and D, digital calculation is performed using the digital signal of A and the fader digital signal related to the manual fader that controls this signal, and the signal is faded out. Further, digital calculation is performed using the D digital signal and the fader digital signal related to the manual fader to perform a fade-in. And fade out,
The faded-in digital signals are added together.

The present invention realizes a digital signal editing device based on the above-mentioned idea, and a detailed description of the embodiments will be given below. In Figure 3,
5 is a CPU (microcomputer) that controls this device, 6 is a ROM that stores the program of the CPU 5, 7 is a RAM that stores data required by the CPU 5, and 8 is a data bus (the address bus is not shown in the figure). (omitted), 9 is an operation input unit for giving control commands to this device, 9' is a display to show that the CPU 5 has received the operation input,
Alternatively, a control output section 10 is used to output control signals to control other parts of the device, and 10 is an interface element for interfacing the above-mentioned 9 and 9' with the CPU 5. On the other hand, P ₁ and P ₂ are PCM data input terminals from first and second digital recording and reproducing devices (hereinafter referred to as PCM tape recorders), respectively. 11 is a switch controlled by the output of the control output unit 9' from the CPU 5 via the interface element 10; 12 is the switch 1;
1 is a memory for writing and storing PCM data via 1; 13 is an address counter for the memory 12; 14;
15 is an interface element that interfaces the address counter 13 and the CPU 5, and 15 is the PCM data of the first PCM tape recorder inputted from the input terminal _P1 and the second PCM data inputted from the input terminal _P2 .
This is a crossfade processing circuit for digitally calculating PCM data of a PCM tape recorder to generate a crossfade. 16 is an interpolation circuit which prevents the clock frequency from being mixed into the reproduced audio as noise when the memory 12 is reproduced at a variable speed and the memory is read at a clock frequency lower than the original sampling frequency. belongs to. 17 is a switch that switches either the output of the crossfade processing circuit 15 or the interpolation circuit 16 according to the output of the control section 9'; 18 is a D/A converter; 19 is a low-pass filter;
20 is an amplifier, and 21 is a monitor speaker. R is an output terminal to the third PCM tape recorder (recording tape recorder). Reference numeral 22 indicates a reference clock pulse generation circuit, 23 indicates a manual clock pulse generator, and 24 indicates an output of either the reference clock pulse generation circuit 22 or the manual clock pulse generator 23, selected by the output of the control output section 9'. This is a selector switch. T _P1 terminal is
Input terminal for SMPTE time code played on the first PCM tape recorder connected to P ₁ terminal, 2
5 is a time code interface circuit that interfaces the above time code input with the CPU 5, the T _P2 terminal is an input terminal for the SMPTE time code played by the second PCM tape recorder connected to the P ₂ terminal, and 26 is the above time code Input and CPU
This is a time code interface circuit that interfaces 5.

Next, the operation of this embodiment will be explained based on FIG. 3 as well. As a premise, the first terminal connected to _P1 terminal
The second tape is attached to the PCM tape recorder.
The first tape explained in the figure is connected to the second PCM tape recorder connected to the _P2 terminal.
and the third PCM connected to the R terminal.
The tape recorder is also used as the third tape. These are respectively called a playback tape recorder 1, a playback tape recorder 2, and a recording tape recorder. To make the third tape shown in Figure 2c, first the editing points, i.e. the starting point 4 of A of the first tape shown in Figure 2a and the boundary between A and B, and the second tape shown in b.
It is necessary to find the exact position of the boundary between C and D of the tape.

Next, the operation for determining the editing point will be explained.
First, in order to determine the starting point 4 of A, the reproduction tape recorder 1 reproduces the portion of the first tape before point 4 and inputs it to the _P1 terminal. At this time, switch 11 has g-h turned on, and the _P1 terminal
When PCM data is input, this data is cyclically recorded in memory 12 via switch 11. In other words, once writing has been completed to the last address in the memory 12, writing starts again from the first address.As a result, if you take a certain moment, the PCM data stored in the memory 12 will always be stored for a certain period of time from that moment. The previous data will be stored continuously. The address of this memory 12 is controlled by an address counter 13. The clock pulses of this counter 13 are supplied with the clock pulses generated from the reference clock pulse generation circuit 22 by turning on the switch 24 ed. Furthermore, switch 17 has switches a and b turned ON, and the input PCM data passes through crossfade processing circuit 15 and is converted to the original analog signal by D/A converter 18 via switch 17, and the input PCM data is converted to the original analog signal by D/A converter 18. A high frequency component is cut by a frequency filter 19, amplified by an amplifier 20, and supplied to a speaker 21, where the audio from the tape recorder 1 on the playback side is monitored.

Control of each of the above parts, for example, switches 11 and 1
The polarity of signals 7 and 24, disabling of the crossfade processing circuit 15, etc. are all controlled by signals from the control output section 9'. That is, a signal from an operation input unit 9 consisting of a keyboard pushbutton, etc. is transmitted to the CPU 5 via an interface element 10 and a bus line 8, and a corresponding control signal is transmitted from the CPU 5 to a bus line 6 and an interface element 10. This signal is output from the control output section 9' via the control output section 9'. In FIG. 3, control lines other than the switch from the control output section 9' are omitted.

The editor inputs a signal from the operation input section 9 indicating that it is the desired timing to edit while monitoring the output audio from the speaker 21. This signal is transmitted to the CPU 5 through the above-mentioned path, and the following control is performed via the control output section 9'. First, the operation continues for a certain period of time from an editing point desired by the editor, and after the certain period of time, writing to the memory 12 is stopped. Thereafter, the tape running of the first playback tape recorder is stopped. Control of the tape recorder is carried out by instructions from the CPU 5, but all are omitted in the figure. Now, the contents of the memory 12 at this time are as shown in FIG. Here, the specifications are assumed as follows. Audio data is 16 bits/sample, sampling frequency is 50KHz, memory is
256KW (1W = 16 bits), in this way the audio data stored in the memory 12 will be 256÷50K≒5
It is about 5 seconds from the second. Of course, in order to save memory, the data may be stored in memory every other sample (this means that the sampling frequency is halved). Alternatively, a method such as reducing the number of pits per sample using a pit compression method may be applied. Here, in order to simplify the explanation, such processing will not be performed at all. In FIG. 4, a 256KW memory is simulated, and audio data is sequentially written from left to right, and when it reaches 2FFFF, it is written again from 00000, and this process is repeated. The memory address corresponding to the timing desired by the editor is represented by an x in the figure. Then, writing is completed at a timing corresponding to the Y memory address delayed by, for example, 4 seconds within the repetition cycle as a fixed period of time.
As a result, memory 12 has (Y+1) → 2FFFF →
The audio is recorded in the order of 00000→Y.

Next, in order to search for the correct editing point, the contents of the memory 12 are read out, and by setting the device to the editing point search mode from the operation input section 9, the editor can send control signals to each section. becomes as follows. Switches 17 a to c are turned on, and switches 24 d to f are turned on. Reference numeral 23 denotes a manual clock pulse generator composed of a rotary encoder, etc., and the frequency of the pulses it generates changes depending on the speed of movement, and if it is stopped, no pulses are generated at all. If a rotary dial, for example, is employed as the manual control means, the greater the rotation speed, the more pulses will be generated. If this pulse and information on the rotation direction are given to the address counter 13 and it operates as an up-down counter, for example, when the rotation is clockwise, the memory is transferred in the forward direction, that is, from X to Y.
Set the address in this order and read the contents of the memory.
This read PCM data is processed by the interpolation circuit 16.
interpolates the data, converts it to the original analog signal by the D/A converter 18 via the switch 17, cuts the high frequency component by the low-pass filter 19, amplifies it by the amplifier 20, and outputs it to the speaker 20.
The editor monitors the sound. The faster the rotary dial is rotated, the higher the frequency of the audio to be reproduced becomes. When rotated counterclockwise, X→0000→2FFFF→
The audio is played back in the order of (Y+1), and the sound is played back as if the recorded tape of a tape recorder was rotated backwards. Naturally, the frequency of the reproduced sound changes depending on the rotation speed at this time as well. in this way
When playing back audio sampled at 50KHz and stored in memory at variable speed, there are the following problems. That is, when reproduction is performed at a clock frequency of 50 KHz or more, there is no particular problem, but when reproduction is performed at a frequency lower than 50 KHz, for example, 10 KHz, a 10 KHz component is generated due to this clock frequency. However, the cutoff frequency of the low-pass filter 19 is, for example, 20K.
Hz and the optimum value is when the sampling frequency is 50KHz. Therefore, the 10 KHz component is not removed by the low-pass filter 19 and is heard as noise. In order to solve this problem, the interpolation circuit 16 is operated.

Next, the function of the interpolation circuit 16 will be explained with reference to FIG. In Figure 5a, the audio signal stored in the memory is played back at the normal speed, that is, 50KHz, and the D/
This is the A conversion. If the same signal is reproduced at 10KHz and D/A converted, the result will be as shown in Figure 5b. Here, points S in FIGS. 5a and 5b indicate the same sample. The purpose of this circuit is to smoothly interpolate the discontinuous portions of these signals at 50 KHz as shown in Figure 5c.

First, the concept of interpolation will be explained. FIG. 6 shows an enlarged view of a portion of FIGS. 5b and 5c. In FIG. 6, 31 is an input to the interpolation circuit. a and b are outputs read from the memory, and are sample values of temporally adjacent samples. _T10 ,
T ₂₀ is the timing of the manual clock pulse; T ₂₀
is the timing one clock period after _T10 .
T ₁₀ , T ₁₁ , T ₁₂ , T ₁₃ , T ₁₄ and T ₂₀ are the timings of sampling clock pulses. 32 is the output of the interpolation circuit 16. T _1o (n=0, 1, 2,
The output L _1o of the interpolation circuit 16 in 3 and 4) is determined as follows.

L _1o = a + (ba - a) · n · k ... (1) Here, k is a coefficient (slope coefficient) that is inversely proportional to the frequency of the output of the manual clock pulse generator 23. For example, in the case of Fig. 6, it can be easily If this is determined, the output of the manual clock pulse generator 23 is 10KHz and the sampling frequency is 50KHz, so it is set to 1/5. It can be seen that in equation (1), if k=1/5 and n=0, 1, 2, 3, and 4, 32 interpolations shown in FIG. 6 can be performed.

The block diagram for realizing the above functions is shown in Figure 7.
As shown in the figure.

FIG. 7 shows a block diagram of the interpolation circuit 16.
is the 16-bit parallel signal input to the interpolation circuit, 53
is a terminal to which the output of the manual clock pulse generator 23 is input, and 54 is a sampling clock (50 KHz in this case) input terminal. 41 and 42 are latch circuits, 43 is a subtraction circuit that subtracts the output of the latch circuit 42 from the output of the latch circuit 41, 44 is an addition circuit, and 45 is a sampling clock, which is the addition circuit 44.
This is a latch circuit that latches the output of . 46 is a reference clock pulse generation circuit (for example, 50K
Hz) x 100 = generates a 5MHz clock pulse)
It is. 47 is a counter that is reset by the output of the manual clock pulse generator 23 and counts the output of the reference clock pulse generator 46;
48 consists of a ROM, which uses the output value of the counter 47 as an address and corresponds to that address.
A circuit 49 multiplies the output of the latch circuit 45 by the slope of the output of the rolling coefficient generation circuit 48, and 50 multiplies the output of the multiplication circuit 49 and the output of the latch circuit 42. An adder circuit 51 for adding the outputs is a polarity determining circuit that latches the polarity bit of the output of the latch circuit 43 and determines the polarity of the multiplier circuit 49. 55 is the output of the interpolation circuit.

The outputs of the latch circuits 41 and 42 are the sixth
Corresponds to b and a in the figure. The output of the subtraction circuit 43 is (ba) in equation (1). Further, by combining the adder circuit 44 and the latch circuit 45, the output (ba).times.n is obtained. Since the frequency of the output of the reference clock pulse generation circuit 46 is 5 MHz and the frequency of the output of the manual clock generator 23 is 10 KHz, the output of the counter 47 is 500. At this time, 100/=500=1/5 is output as the output k of the slope coefficient generating circuit 48, which is constituted by, for example, a ROM. In other words, if the output of the counter 47 is Z, then 10
Let 0/Z be k. As a result, the output of the multiplication circuit 49 is (ba)·n·k. Furthermore, an addition circuit 50
As the output, a+(ba)·n·k of equation (1) is obtained. Therefore, as the output 55 of the interpolation circuit, the sixth
This results in the dotted line 32 in the figure. Here, depending on the magnitude relationship between a and b, the polarity bit is determined by the polarity determining circuit 5.
1 to change the sign bit of the multiplier circuit 49. In addition, in Fig. 7, the second term of equation (1) is (b
-a)×n is calculated first, but
Depending on the hardware, overflow may occur at this stage, so if k×n is calculated first, this risk will be eliminated.

As described above, the output of the interpolation circuit 16 shown in FIG.
9. The sound reproduced at variable speed from the speaker 21 via the amplifier 20 can be monitored. At this time, if you turn the rotary dial in the forward or reverse direction, you will hear exactly the same playback sound as when you manually rotate the reel of a conventional analog tape recorder in the forward and reverse directions.

In this way, you can stop the rotary dial at the point you want to edit, and send a signal to the CPU5 that that point is the editing point.
give to This means that the position of the starting point 4 of A in FIG. 2 has been determined. CPU5 at this position
The following process is required for recognition. First, T _P1 is input at the same time as the PCM data at the editing point given by the editor.
The time code input signal from the terminal is sent to the CPU via the time code interface 25 and bus line 8.
5 reads it and saves it to RAM7. here
In SMPTE timecode, frames (1/30
Since the minimum unit of the signal is in units of seconds (seconds), in order to increase the editing precision beyond this, the CPU 5 must count the audio sampling pulses within the frame and read in the information about the number of samples within the frame. Although it is necessary to store it in the RAM 7, this counter is omitted in FIG. 3 and is included in the time code interface circuit 25. Therefore, at this point, the CPU 5 reads information on hours, minutes, seconds, frames, and samples. Next, in the edit point search mode, the manual clock pulse generator 23
The counter in the time code interface 25 operates together with the address counter 13 by the output of , and the time code information of the manually corrected accurate editing point and the sample point information in the finer frame unit, that is, hours, minutes, seconds, etc. The CPU 5 will read the information of the frame sample. (Not shown) Let this information be S _P1 . In this way, the CPU 5 has information on the exact position of the sample point in the memory 12 and on the tape.

Next, the boundary between A and B of the first tape in FIG. 2a is determined. In the same way as above, the editor
While monitoring the output audio from the first tape, a signal to that effect is inputted from the operation input section 9 at the timing at which editing is desired, that is, near the boundary between A and B of the first tape, as described above. Thereafter, writing continues in the memory 12 for a certain period of time, and the process is the same until it stops. However, in this case, the capacity of memory 12 is approximately 5
If there are seconds, writing to the memory 12 is stopped when a time shorter than half of five seconds, for example one second, has elapsed from the specified point. The state inside the memory 12 at this time is shown in FIG. 8, and X and Y are respectively
The operation of searching for the correct edit point in the memory 12 corresponding to X _P1 and Y _P1 is the same as described above, and the switch 17 is
-b is ON, switch 24 is d-f is ON,
When the dial is rotated in the forward direction, memory 12
The content of is played in the order of X _P1 → Y _P1 , and when rotated in the opposite direction, X _P1 → 00000 → 2FFFF → (Y _P1 +
1) are played in the order shown. In this way, the audio is played back as the rotary dial rotates, so it is possible to stop the rotary dial at the correct position and designate this point as an editing point. The position information of this point can be obtained from the CPU 5 using the same operation as in the previous case.
and save it to RAM7. Let the memory address of this point be X _P1 +N _P1 . Also, as described above, the manually corrected accurate time code information and sample point information of the editing point are set as E _P1 .

Next, the contents of the memory 12 are read out continuously using the reference clock to check whether the edit point set above (address X _P1 + N _P1 in the memory) is correct. This device inputs the edit point memory from the operation input section 9.
By setting it to pre-monitor mode, the controls for each part are as follows. switch 1
7, a-c is ON, switch 24 is d-e.
It becomes ON. Further, the CPU 5 presets the address counter information Y _P1 stored in the RAM 7 into the address counter 13 via the data bus 8 and the interface element 14 as an initial value. A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 is
Based on CPU5 instructions Y _P1 →2FFFF→00000→
Memory 1 by changing the address in the order of X _P1 +N _P1
At the same time as reading 2, this address is input to the CPU 5 via the interface element 14. The digital signal read out from the memory 12 passes through the interpolation circuit 16 and is sent to the switch 17,
D/A converter 18, low pass filter 19, amplifier 2
0 and then monitored as a continuous audio signal from the speaker 21.

If there is a problem with the edit point in the above edit point memory/pre-monitor mode, repeat the process starting from the process of determining the edit point in memory, and if a suitable edit point is obtained, proceed to the next step.

Next, in order to determine the boundary between C and D of the second tape in FIG. 2b, part 2 of the second tape is played back by the second playback tape recorder and inputted to the _P2 terminal. At this time, switch 11 turns on g-i.
When PCM data is input to the _P2 terminal, this data is cyclically recorded in the memory 12 via the switch 11.

Since the subsequent steps are the same as those for determining the starting point 4 of the first tape shown in FIG. 2a, the explanation will be omitted. The X and Y of Figure 4 set here are respectively
Let X _P2 and Y _P2 be the address in the memory 12 at the editing point, and let _{E P2} be _the time code information and sample point information.

Next, the editor reads out the contents of the memory 12 continuously using the reference clock and monitors whether the edit point set above (address X _P2 + N _P2 in the memory) is correct. By setting this device to the edit point memory/pre-monitor mode from the operation input section 9, the control of each section is as follows. switch 17
, a-c are ON, switch 24 is d-e is ON
becomes. Further, the CPU 5 presets address counter information Y _P2 +1 stored in the RAM 7 into the address counter 13 via the data bus 8 and the interface element 14 as an initial value.
A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 is
Based on CPU5 instructions Y _P2 +1→2FFFF→
At the same time as writing the memory 12 by changing the address in the order of 00000→X _P2 +N _P2 , this address becomes
It is input to the CPU 5 via the interface element 14. The digital signal read from the memory 12 passes through the interpolation circuit 16 and is sent to the switch 1.
7, a D/A converter 18, a low-pass filter 19, and an amplifier 20, and then monitored by a speaker 21 as a continuous audio signal. If there is a problem with the edit point in the above edit point memory/pre-monitor mode, repeat the process starting from the process of determining the edit point in memory.
Once a suitable editing point is obtained, proceed to the next step.

Next, like the tapes in Day 3 of Figure 2c, A and D
Set the fade characteristics to crossfade as follows.

the first and second without recording on the actual tape.
The playback side tape recorder is run to perform the first tape pre-monitoring operation. When the editor sets this device to the tape pre-monitor mode using the operation input section 9, the CPU 5 instructs the first and second playback tape recorders to move from the respective editing points E _P1 and E _P2 . The time required for monitoring is sufficient, and the time required for synchronized travel control is
(For example, L ₁ and L ₂ in Fig. 2) Rewind and rewind each tape so that the respective editing points E _P1 and E _P2 obtained above are input to P ₁ and P ₂ in Fig. 3 at the same time. are synchronously controlled and the timing is adjusted using an appropriate delay circuit. First, only the signal A in FIG. 2A is passed through the crossfade processing circuit 15.

Next, near the editing point of the first tape shown in FIG. 2a, a crossfade is performed, and the crossfade processing will now be specifically described. FIG. 9 is a detailed block diagram of the crossfade processing circuit 15 in FIG. 3. Fi1 is in Figure 3.
PCM data input from P ₁ , Fi2 is also PCM data input from P ₂ .

When the editor sets this device to the manual fader setting mode from the operation input section 9, the control signals to each section are as follows. Switch 67 turns on a and b. 61 is a manual feeder consisting of variable resistors, etc.
2 is a fader interface for connecting the manual fader 61 and the circuit; 63 is an A/D conversion circuit consisting of a sampling/holding circuit;
4 is a memory that stores the fader digital signals of the 63 A/D conversion circuit, 65 is an address counter that sets the address of the memory 64 according to the clock signal of the 66 clock generation circuit, and 67 is an A/D converter circuit.
A fader digital signal of the D conversion circuit 63,
A switch for switching between the fader digital signal read from the memory 64, and a multiplication circuit 68 for calculating the PCM data input from Fi1 and the fader digital signal from the switch 67;
69 is an inverter that inverts the fader digital signal from switch 7; 70 is a multiplication circuit that calculates the PCM data input from Fi2 and the fader digital signal from inverter 69;
1 is an adder circuit that adds the outputs of the multiplier circuits 68 and 70. When the editor operates the resistance value of the manual fader 61 from infinity to zero, the fader interface 62 converts the change in resistance value into a DC voltage change. This DC voltage is applied to a clock generation circuit 66 by an A/D conversion circuit 63.
The signal is sampled by the clock and converted into a digital signal. This characteristic is shown in FIG. 10 72. The converted fader digital signal is then cleared externally (control output section 9' in FIG. 3) and stored in the memory 64 whose address is set from zero by the address counter 65 started by the clock of the clock generator 66. At the same time, the signal is input to the multiplication circuit 68 via switches a and b of the switch 67. The multiplication circuit 68 receives the input from Fi1.
It calculates the PCM data and the fader digital signal input via the switch 67, and fades out the PCM data input from Fi1.

Further, the fader digital signal passed through the switch 67 is inverted by the inverter 69 and input to the multiplication circuit 70. The multiplication circuit 70 calculates the PCM data inputted from Fi2 and the fader digital signal inputted by the inverter 69, and fades in the PCM data inputted from Fi2. Further, the adder circuit 71 adds the PCM data faded out by the multiplier circuit 68 and the PCM data faded in by the multiplier circuit 70 to obtain a crossfaded Fo output. This Fo is input to the switch 17 in FIG.

Here, the specifications are assumed as follows. DC voltage from manual fader is 8 bits/sample,
Sampling frequency 30Hz, memory 300W (1W
= 8 bits), in this way the memory 64,
The data stored in 71 is 10 seconds each, as 300÷30=10.

Therefore, the editor inputs the PCM data signal of the crossfade processing circuit 15 shown in FIG.
While monitoring via the D/A converter 18, low-pass filter 19, amplifier 20, and speaker 21,
By operating the manual fader 61, a unique crossfade characteristic (for example, the characteristic shown in FIG. 10) can be obtained.

Note that in the above configuration, since the fader digital signals inputted to the multiplier circuits 68 and 70 are complementary to each other, there is an advantage that the crossfade output signal of the adder circuit 71 is not saturated.

Here, when the aforementioned editor sets the manual fader setting mode, that is, when the address counter 65 starts, the CPU
5 is played back from the first and second playback side tape recorders (input from T _P 1 and T _P 2)
A time code signal is input to the RAM 7 via time code interface circuits 25 and 26. The time code at this time is FT1.

Next, when the crossfade time ends (after 10 seconds in the above example), the crossfade processing circuit 15
allows only the signal input from _P2 to pass and stops writing to the memory 64.

The exact edit point on the tape is determined by RAM as described above.
7, the synchronized running of the tape, the delay amount of the delay circuit, the crossfade timing, etc. are all performed by commands from the CPU 5.

Through the above process, the first tape pre-monitor is completed, and the crossfade characteristics near the editing point are stored in the built-in memory 64.

Next, a second tape pre-monitor is performed to check whether editing is performed according to the crossfade characteristics set in the first time. The second tape pre-monitor performs the same operations and controls as the first tape pre-monitor, but the CPU 5 uses the time code signal input from the T _P 1 via the time code interface circuit 25. , when it becomes the same as the time code value ET1 set above, switches a to c of the switches 67 in FIG. 9 are turned on, and the address counter 65
Clear and start. (The address counter is started from zero.) The address counter 65 reads the memory 64 in which manual fader information (fader digital signal) is stored for 10 seconds. This read fader digital signal is input to a multiplication circuit 68 via a switch 67. The multiplication circuit 68 performs an operation on the PCM data inputted from the Fi1 terminal and the fader digital signal read out from the memory 64, and fades out. Further, the fader digital signal inverted by the inverter 69 is input to the multiplier circuit 70 via the switch 67 . The multiplication circuit 70 performs an operation on the PCM data inputted from the Fi2 terminal and the fader digital signal inputted by the inverter 69, and performs a fade-in.

The adder circuit 71 adds the PCM data faded out by the multiplier circuit 68 and the PCM data faded in by the multiplier circuit 75 to obtain a crossfaded Fo output. As described above, the crossfade characteristics set during the first tape pre-monitor mode described above can be reproduced by using the memory 64.

Through the above process, tape pre-monitoring ends. If there is a problem with the crossfade characteristics near the editing point, the first tape pre-monitoring operation is repeated and the fader digital signal in the memory 64 is re-stored. Once a suitable crossfade characteristic is obtained, proceed to the next editing process.

In the editing process, the operation near each editing point is the same as the second tape pre-monitor, but the editing process involves playing back the necessary parts of the first and second tapes in Figure 2. Therefore, the first reproducing tape recorder is rewound to a point slightly before the beginning of point A of the first tape in FIG. 2a. Further, the second reproducing side tape recorder is rewound by a length of time _L2 from the editing point E _P2 of C and D of the second tape in FIG. 2b. Then, the first playback side tape recorder is played back, and the third playback side tape recorder is played back.
When the starting point 4 of A in FIG _{. 2A} is input as a digital signal to the P1 terminal in the figure, it passes through the crossfade processing circuit 15 and is outputted to the R terminal via the switch 17. A recording side tape recorder is connected to the R terminal, and this tape recorder is put into a recording state.

Next, when the first playback tape recorder plays up to _L1 before the crossfade part A in Figure 2a, the second playback tape recorder plays back the edit points E _P1 and E obtained above. Each tape is synchronously controlled so that _P2 is input to _P1 and _P2 in FIG. 3 at the same time, and the timing is adjusted by an appropriate delay circuit. Thereafter, by performing the same operation as the second tape pre-monitor operation, the data is edited on the recording side tape recorder connected to the R terminal as shown in FIG. 2c.

According to the above embodiment, since the editing is done at the stage of the audio PCM signal itself, regardless of the recording format of the tape deck, there may be problems caused by hand-cut editing when newly reconfiguring and recording on the recording side tape recorder. There is no lack of information at all.

Furthermore, since the output of the tape recorder on the playback side is stored in a memory, and this memory is read out for monitoring and editing, accuracy is high and editing points can be easily selected. In particular, by providing an interpolation circuit, it is possible to manually read out the memory at a variable speed, and editing points can be easily selected in the same way as in the case of analog signal tape. Furthermore, when performing crossfade processing near the editing point, it is now possible to create fade-out characteristics and fade-in characteristics using a single manual fader.
This can be achieved with a very simple configuration as described above. Furthermore, since one fade characteristic is created by inverting the other fade characteristic, saturation does not occur when the signals processed for each characteristic are added together, which is a useful feature in practice. The above fade characteristics are stored in memory, and the playback signal is also stored in another memory as described above, so these memories can be read and rehearsed, and the contents of each memory can be easily rewritten. Being able to rehearse again has a great effect on increasing practicality.

As described above, according to the present invention, one of the fade-in and fade-out characteristics of a reproduced digital signal can be set by a single manual means, and the obtained characteristic is stored in a memory, and is stored when the memory is read. On the other hand, the fade characteristics and
Since the other fade characteristics formed using this can be obtained simultaneously, editing with cross-fade processing can be performed with a very simple configuration and easy operation.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of analog editing, FIG. 2 is an explanatory diagram showing the concept of the editing method adopted in the digital signal editing device of the present invention, and FIG. 3 is an implementation of the digital signal editing device of the present invention. 4 is an explanatory diagram showing the write state of the memory 12, FIG. 5 is a waveform diagram explaining the concept of interpolation, and FIG. 6 is a waveform diagram explaining the interpolation function of this embodiment. Figure 7 is a block diagram showing the configuration of the interpolation circuit.
FIG. 8 is an explanatory diagram showing the write state of the memory 12, FIG. 9 is a block diagram showing the configuration of the crossfade processing circuit, and FIG. 10 is a characteristic curve diagram showing the fade curve set by the manual fader. 5...CPU, 6...ROM, 7...RAM, 9
...Operation input section, 9'...Control output section, 12...
Memory, 13... Address counter, 15... Crossfade processing circuit, 16... Interpolation circuit, 18
...D/A converter, 22...Reference clock generation circuit, 23...Manual clock generator, 61...Manual fader, 63...A/D conversion circuit, 6
4...Memory, 65...Address counter, 66
... Clock generation circuit, 68, 70 ... Multiplication circuit, 69 ... Inverter, 71 ... Addition circuit.

Claims (1)

[Claims] 1. A fade characteristic setting means for manually variably setting the level change characteristics of a digital signal reproduced from a sound source such as a tape or a disk, a memory for storing the level change characteristics set by the fade characteristic setting means, and A first means for controlling the level of the reproduced digital signal by the read output of the memory, and another level change characteristic created from the read output of the memory to control the level of the other reproduced digital signal. 1. A digital signal editing device comprising: second means for controlling the output signal; and means for recording a cross-faded and continuous output signal by combining the outputs of the first and second means.