JPS5850685A - Editing device of digital signal - Google Patents

Abstract

PURPOSE:To realize the editing with a fading process carried out with a simple constitution and an easy operation, by setting either the fade-in or fade-out characteristics with a single manual varying means to store and obtaining both characteristics at the same time in the reading mode. CONSTITUTION:The resistance change of a fader 61 is converted into a DC voltage change through a fader interface 62, and the DC voltage is converted into a digital signal. This fader digital signal is stored in a memory 64 and at the same time fed to a multiplier circuit 68. The circuit 68 performs an operation for the PCM data Fi1 and the fader signal then fades out the PCM data. This fader signal is inverted by an inverter 69 and fed to a multiplier circuit 70. The circuit 70 operations for the data Fi1 and the fader signal and fades in the PCM data Fi2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal editing device for editing digital signals reproduced by a digital recording and reproducing device, etc., and is capable of smoothly connecting digital signals by performing crossfate processing on a single manual fader. The present invention provides a digital signal editing device that can realize precise editing with easy configuration and operation.

Traditionally, when editing analog recorded tapes, the useful parts of the recorded tapes were manually cut and spliced together.
They have been hand-cut and edited into book tapes. This situation is shown in FIG. In Figure 1, 1' and 2' are parts of different recorded tapes, part A of 1' is a necessary part, part B is an unnecessary part, part 0 of '2 is an unnecessary part, D The part is the necessary part. A desired tape 3 can be obtained by cutting these tapes and mechanically joining them together. At this time, tape 1'.

It is necessary to find the cutting position of 2', that is, the boundaries between A and B and C and D (hereinafter referred to as editing points); for this purpose, the following operations were necessary. In other words, put the tape recorder in the playback mode, and while listening to the playback sound, stop the tape recorder at a position that appears to be the editing point. In order to find a more accurate editing point, it is best to manually rotate the wheels in the same direction, forward or reverse, and listen to the playback sound to make a judgment. That is, when such fine adjustments are made and it is determined that the tape is at a desirable editing point, the position of the tape in contact with the gap portion of the reproducing head is set as the correct editing point, and the above-mentioned cutting is performed. The reason why the take is cut diagonally as shown in FIG. 1 is to prevent the reproduced sound from becoming discontinuous at the editing point when the edited tape is played back.

This is because the effect is that the sound of section A gradually becomes smaller (fade out) and the sound of section p gradually becomes louder (fade in). The effect of this connection is called a crossfade.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying it to digital sound recording playback devices that have been put into practical use in recent years. That is, in a digital recording/playback device, the recorded signal is a digital story, meaning that meaningless information continues for a period of time, and it is obvious that this has a detrimental effect on the reproduced sound. On the other hand, in order to reduce the amount of information lost as much as possible, even when the tape is cut perpendicular to the direction in which it travels, digital recording and playback equipment usually adds error codes and correction codes to dozens of samples of information pids.
Since it is recorded as an M frame, errors in the IPCM frame are unavoidable. Therefore, it is necessary to perform operations such as (a) placing a meeting on that part, or (b) skipping that part and connecting the information before and after it, and in any case, the sound quality of the original information at that part will deteriorate. is essentially a problem.

The present invention solves the above-mentioned conventional drawbacks, and provides a novel method that enables smooth editing without signal loss or discontinuity at editing points, and enables cyclone fade processing with a single manual fader. A digital signal editing device is provided.

An embodiment of the present invention will be described below based on the drawings. First, an outline of the editing method of the digital signal editing device of the present invention will be explained. In this method, the recorded tape is not cut mechanically, but instead three digital recording and playback devices are used, the first digital recording and playback device plays back the digital signal up to the editing point, and then the second digital The recording and playback device switches to a playback digital signal and records it on a third digital recording and playback device to create an edited tape. This will be explained using Town Map 2. That is, in Figure 2, (
a) is the first digital recording/playback device attached to the first digital recording/playback device;
-) is the second tape attached to the second digital recording/playback device, and (C) is the third tape for recording the edited digital signal.
It is attached to digital recording and playback equipment. First of all
At the same time, the first tape loaded in the digital recording/playback device is rewound a little more than the starting point 4 of the necessary portion A, and at the same time, the second tape loaded in the second digital recording/playback device is rewound.
Rewind the tape L2 before the boundary between C and D.

Then, when the first tape is played back and reaches the starting point 4 of A, the third tape attached to the third digital recording and playback device is
The first tape is set to a recording state, and part A of the first tape is recorded. Then, when the distance L1 comes before the boundary between the first tapes A and B, the second tape is played back. Here L1
%L2, but this value means that at the moment when the playback head of the first digital recording/playback device comes into contact with the boundary between A and B of the tape in Tower 1, the second The length of the first tape and the second tape can be moved in this way so that the playback head of the digital recording and playback device comes into contact with the first tape and the second tape, as long as the length is sufficient to run the tapes synchronously. A third edited tape such as C can be recorded by running the digital signal synchronously and switching the digital signal recorded on the third tape from the boundary between A and B of the first tape to D of the second tape. can be created.

At this time, at the boundary between A and D, digital calculation is performed using the digital signal of A and the fader digital signal related to the manual fader that controls this signal, and the signal is faded out. Further, digital calculation is performed using the D gain signal and a fader digital signal related to the manual fader to perform a fade-in. Then, the fade-out and fade-in digital signals are added together.

The present invention realizes a digital signal editing device based on the above-mentioned idea, and a detailed description of the embodiments will be given below. In FIG. 3, 6 is a CPU (microcomputer) that controls this device, and 6 is a CPU 5.
7 is a RAM that stores the data required by the CPU 5, and s is a data bus (
(The address bus is omitted in the figure), 9 is an operation input unit that gives control commands to this device, and 9' is a display that shows that the CPU 5 has received the operation input, or controls other parts of this device. Output a control signal for! The control output section of c and 10 connects the above 9 and 9' to CP.
This is an interface element for interfacing with the Ues. On the other hand, P+.

P2 are PCM data input terminals from first and second digital recording and reproducing devices (hereinafter referred to as PCM tape recorders), respectively. 11 is a switch controlled by the output of the control output section 9' from the CPU 5 via the interface element 1o; 12 is a memory for writing and storing PCM data via the switch 11; 13 is an address counter for the memory 12; 14 is an address counter. 13th CPU5
An interface element 16 interfaces with the first PCM tape inputted from the input terminal P1.

This is a cross-fade processing circuit for digitally calculating the PCM data of the recorder and the PCM data of the second PCM tape recorder input from the input terminal P2 to generate a cross-fade. Reference numeral 16 is an interpolation circuit, and when the memory 12 is reproduced at a variable speed, when the memory is read at a clock frequency lower than the original sampling frequency, that clock frequency is mixed into the reproduced audio as a q sound. There is no way to prevent this.

17 is the cross-fade processing circuit 16 and the interpolation circuit 16
18 is a D/A converter, 19 is a low-pass filter, 2o is an amplifier, and 21 is a monitor speaker. R is an output terminal and child to the third PCM tape recorder (recording side tape recorder). 22 is a reference clock pulse generation circuit, 23 is a manual clock pulse generator, '2
Reference numeral 4 denotes a changeover switch which selects and outputs either the output of the reference clock pulse generation circuit 22 or the manual clock pulse generator 23 according to the output of the control output section q. The TP+ terminal is an input terminal for the SMPTE time code reproduced by the first PCM tape recorder connected to the P1 terminal, 26 is a time code interface circuit that interfaces the above time code input and the CPU 5, and the TP2 terminal is connected to the P2 terminal. 26 is an input terminal for the SMPTE time code reproduced by the 20th PCM tape recorder, and 26 is a time code interface circuit that interfaces the above time code input with the CPU 6.
Ru.

Next, the operation of this embodiment will be explained based on FIG. 3 as well.

The premise is that the tape attached to the 100th PCM tape recorder connected to the P1 terminal is the first tape explained in Figure 2, and the second PCM tape recorder connected to the P2 terminal is the same second tape. , the third PCM tape recorder connected to the R terminals is also referred to as the third tape. These are respectively referred to as a playback tape recorder 1, a playback tape recorder 2, and a recording tape recorder.

To create the third tape shown in Figure 2 (C1), first the editing points, i.e. the starting point 4 of A of the first tape shown in Figure 2 (a3 and the boundary between A, B and ff (shown in bl) It is necessary to find the exact position of the boundary between C and D of tape No. 2.

Next, the operation for determining the editing point will be explained.

First, in order to determine the starting point 4 of A, the playback tape recorder 1 plays back the portion of the first tape 4 steps earlier, and
Input to 1 terminal. At this time, switch 11 turns g-h ON.
When PCM data is input to the P1 terminal, this data is cyclically recorded in the memory 12 via the switch 11.

In other words, once the writing to the last address of the memory 12 is completed, writing starts again from the first address.As a result, if we take a certain moment, the PCM data stored in the memory 12 will always be the same from that moment. Data up to a certain time ago is stored continuously. The address of this memory 12 is controlled by an address counter 13. The clock pulses of the counter 13 are supplied with the clock pulses generated from the reference clock pulse generation circuit 2 by turning on the switches 24 e-d.

Furthermore, the switches a and b of the switch 17 are turned on, and the input PCM data passes through the cross-fade processing circuit 16 and is converted to the original analog signal by the D/A converter 18 via the switch 17. High-frequency components are cut by a low-pass filter 19, amplified by an amplifier 20, and supplied to a speaker 21, where the audio from the reproduction side table recorder 1 is monitored.

The control of each section described above, such as the polarity of the switches 11, 17, 24, and disabling of the cross-fade processing circuit 16, are all performed by signals from the control output section 9'. That is, signals from the operation input section 9, which is composed of keyboard push buttons, etc., are transmitted to the interface element 10. It is transmitted to the CPU 5 via the pass line 8, and a corresponding control signal is output from the CPU 5 via the pass line 6 and the interface element 1o from the control output section σ, and the control is performed using this signal. In addition, in FIG. 3, the control output portion 9'
The control lines other than the switches from 1 to 2 are omitted.

The editor inputs a signal from the operation input section 9 indicating that it is the desired timing to edit while monitoring the output audio from the speaker 21. This signal is sent to the CPU via the above route.
5, and the following control is performed via the control output section σ. First, the operation continues for a certain period of time from an editing point desired by the editor, and after the certain period of time, writing to the memory 12 is stopped. Thereafter, the tape running of the first playback tape recorder is stopped. Control of the tape recorder is carried out by instructions from the CPU 5, but these are all omitted in the figure. Now, the contents of the memory 12 at this time are as shown in FIG. Here, the specifications are assumed as follows. Audio data is 16 bits/sample, sampling frequency 50
KHz, the memory is 256KW (IW = 16 bits), and in this way the audio data stored in the memory 12 is 2
Since 66÷5oK=6 seconds, it is about 6 seconds. Of course, in order to save memory, the data may be stored in the memory every other sample (the sampling frequency will be reduced and the data will be smaller). Alternatively, a method such as reducing the number of pits per sample using a pit compression method may be applied. Here, in order to simplify the explanation, such processing will not be performed at all. In Figure 4, 256K
This is a simulated representation of W's memory, but the audio data is written sequentially from left to right, and when it is written up to 2FFFF, it becomes ooo again.
Writing starts from oo, and this is repeated. The memory address corresponding to the timing desired by the editor is represented by an x in the figure. Then, writing is completed at a timing corresponding to the Y memory address delayed by, for example, 4 seconds within the repetition cycle as a fixed period of time. This result memory 1
2 has (Y+1)-+2FFFF-+ooooo-+Y
The audio will be recorded in this order.

Next, in order to search for the correct edit point, the contents of the memory 12 are read out, but the editor can set the device to the edit point search mode from the operation input section 9 to control each section. The control signals are as follows. switch 17
, a-c are turned on, and d-f of the switch 24 is turned on. Reference numeral 23 denotes a manual clock pulse generator composed of a rotary encoder or the like, and the frequency of the pulses it generates changes depending on the speed of movement, and if it is stopped, no pulses are generated at all. If a rotary dial, for example, is employed as the manual control means, the greater the rotation speed, the more pulses will be generated. If the pulse and rotational direction information are used for operation, for example, when rotating clockwise -, addresses are set in the memory in the forward direction, that is, in the order of X-+Y, and the contents of the memory are read out. This read PCM data is stored in the interpolation circuit 1.
6 to interpolate the data, and switch 17 to D/
It is converted into the original analog signal by the A converter 18, the high frequency component is cut by the low pass filter 19, and the signal is sent to the amplifier 2o.
The sound is amplified and supplied to the speaker 20, and the editor monitors the sound. The faster the rotary dial is rotated, the higher the frequency of the audio to be reproduced becomes. When rotated counterclockwise, X40000+2
The sound is played back in the order of F F F F -+(Y+1), and the sound is played back as if the tape was recorded on a tape recorder and rotated backwards. Naturally, the frequency of the reproduced sound changes depending on the rotation speed at this time as well. 50 like this
When audio sampled at KHz and stored in memory is played back at variable speed, there are the following problems.

That is, there is no particular problem when reproduction is performed at a clock frequency of 50 KHz or more, but when reproduction is performed at a frequency lower than 50 KHz, for example 10 KHz, a 10 KHz component is generated due to this clock frequency. However, the cutoff frequency of the low-pass filter 19 is at the optimal value. Therefore, the 10 KHz component is often heard as noise without being removed by the low-pass filter 19. In order to solve this problem, the interpolation circuit 16 is operated.

Next, the function of the interpolation circuit 16 will be explained with reference to FIG. 6i. No. 61) is the one in which the audio signal stored in the memory is reproduced at normal speed, that is, at 50 x 2, and subjected to D/A conversion. When the same signal is reproduced at 10 KHz and subjected to D/A conversion, the result is as shown in FIG. 6(b).

Here, it is shown that the 8 points in Figure 6(al) and (b) are the same sample.This can be achieved by smoothly interpolating the discontinuous portions of these signals at 50KHz as shown in Figure 6(C). This is the purpose of the circuit.

First, the concept of interpolation will be explained. Figure 6(b)
, (An enlarged view of part of C1 is shown in Fig. 6. In Fig. 6, 31 is the input of the interpolation circuit board. A and b are the outputs read from the memory, respectively, and they are the outputs of temporally adjacent samples. This is the sample value. T10 m "20 is the timing of the manual clock pulse, and T20 is the timing one clock period after T10." joyTH* T12
* "+5 e T14 + "20 is the timing of the sampling clock pulse. 32 is interpolation circuit 1
This is the output of 6. The output L1n of the interpolation circuit 16 at TIH (n: 0, 1.2, 3°4) is as follows: L1n=a
(b-a)・n-k......O) Here, k is a coefficient (slope coefficient) that is inversely proportional to the frequency of the output of the manual clock pulse generator 23, for example, In the case of Fig. 6, the output of the manual clock pulse generator 23 is 10Kllz, and the sampling frequency is 60Kllz.
So let's take a look. In equation (1), k 2% m
It can be seen that if n '' O* 1 + 2 t 3 + 4, 32 interpolations shown in FIG. 6 can be performed.

A block diagram for realizing the above functions is shown in FIG.

FIG. 7 shows a block diagram of the interpolation circuit 16. 62 is a 16-bit parallel signal input to the interpolation circuit, 5a is a terminal to which the output of the manual clock pulse generator 23 is input, and 54 is a sampling clock (50 KHz in this case) input. It is a terminal. 41.42 is a latch circuit, 43 is a latch circuit 41
a subtraction circuit that subtracts the output of the latch circuit 42 from the output of the
44 is an adder circuit, and 46 is a latch circuit that latches the output of the adder circuit 44 using a sampling clock. 46 is a reference clock pulse generation circuit (for example, 6°KBz
A clock pulse of X 100 :5 Mn2 is generated). 47 is a counter that is reset by the output of the manual clock pulse generator 23 and counts the output of the reference clock pulse generation circuit 46, and 48 is a ROM, which uses the output value of the counter 47 as an address and stores the ROM corresponding to the address. Output the contents of and calculate the slope coefficient k
49 is a circuit that multiplies the slope of the output of the latch circuit 46 and the output of the rolling coefficient generation circuit 48. 6o is an adder circuit that adds the output of the multiplier circuit 4e and the output of the latch circuit 42. 61 is a latch. This is a polarity determining circuit that latches the polarity bit of the output of the circuit 43 and determines the polarity of the multiplication circuit 49. 66 is the output of the interpolation circuit.

This corresponds to s and a in the figure. The output of the subtraction circuit 43 is (
(, bL7a) in equation 1). Furthermore, addition circuit 4
4 and the latch circuit 45, the output (b-a
) to obtain Xn. Reference clock pulse generation circuit 4
The frequency of the output of 6 is 5MHz, manual clock generator 23
Since the frequency of the output of is 10KHz, the counter 47
The output will be 600.

At this time, 100/5' OO=Akira is output as the output of the slope coefficient generating circuit 48, which is constituted by a ROM, for example. That is, if the output of the counter 47 is 2, then 10
Let 0 be k. As a result, the output of the multiplication circuit 49 is (b-
a)・nk is obtained. Further, a −1−′(b −a )·n·k of equation O) is obtained as the output of the adder circuit 6o. Therefore, the dotted line 32 in FIG. 6 is obtained as the output 66 of the interpolation circuit. Here, the sign bit of the multiplication circuit 49 is changed via the polarity determining circuit 61 based on the magnitude relationship between a and b. In addition, in FIG. 7, the second term of equation (1) is configured to calculate (ba)Xn first, which may cause a barflow, so kX
If the configuration is such that n is calculated first, this concern will disappear.

As described above, the output of the interpolation circuit 16 shown in FIG. If you turn the dial forward or backward, you can hear exactly the same sound as when you manually rotate the reel of a conventional analog tape recorder.

In this way, the rotary dial is stopped at the point to be edited, and a signal indicating that the point is the editing point is given to the CPU 5. This means that the position of the starting point 4 of *A in FIG. 2 has been determined. In order for the CPU 5 to recognize this position, the following process is performed. First, at the timing of the editing point given by the editor, the time code input signal from the TP1 terminal, which is input simultaneously to the PCM 7', is sent to the C through the time code interface 26 and the pass line 8.
PU6 reads it and saves it to RAM y, here S
In MPTE time code, the minimum signal unit is a frame (1/30th of a second), so if you want to increase the editing accuracy beyond this, you need to count 3 audio samples within a frame and calculate the number of samples within the frame. CP also includes information on whether there is
Although it is necessary for U5 to read the counter and store it in the RAM 7, this counter is omitted in FIG. 3 and is included in the time code interface circuit 26. Therefore, at this point, the CPU 5 reads information on hours, minutes, seconds, frames, and samples. Next, in the edit point search mode, the counter in the time code interface 26 operates together with the address counter 13 by the output of the manual clock pulse generator 23, and the time code information of the manually corrected accurate one edit point and the more detailed frame unit are operated. The CPU 5 reads the sample point information, that is, the hour, minute, second, frame, and sample information (not shown). This information is designated as Spl. In this way, the accurate sample point in the memory 12 is read by the CPU 5. CP position and position information on the tape
U5 will have it.

Next, the boundaries between A and H of the first tape in FIG. 2(a) are determined. In the same way as described above, the editor inputs a signal to that effect from the operation input section 9 at the timing when he wants to edit, that is, near the boundary between A and H of the first tape, while monitoring the output audio from the speaker 21. . Thereafter, writing continues in the memory 12 for a certain period of time, and the process is the same until it stops.

However, in this case, assuming that the capacity of the memory 12 is approximately 6 seconds, writing to the memory 12 is stopped when a time shorter than half of 5 seconds, for example 1 second, has elapsed from the designated point. The state inside the memory 12 at this time is shown in FIG. 8, where X and Y are each xPl.

The operation of searching for the correct edit point in the memory 12 corresponding to YPl is the same as described above, with switch 17 a-b turned on, switch 24 d-f turned on, and the dial rotated in the forward direction. Sometimes the contents of the memory 12 are played back in the order of XP1 → YP+, and when rotated Δ in the opposite direction, the contents of the memory 12 are played back in the order of XP1 → YP+.
000-'p2 F F 'F F -+(YP1+1
) will be played in this order. In this way, the sound is played back as the rotary dial rotates, so the rotary dial can be stopped at a correct position and this point can be designated as an editing point.

The position information of this point can be obtained from CPU6 using the same operation as in the above case.
Read it to RAM 7 and save it to RAM 7. Let the address of this point on the memory be Xp1+Np1. Also, as described above, the time code information and sample point information kEpl of the correct edit point are manually corrected.

Next, the edit point set above (address xP in memory)
1+NP1) is correct or not, the contents of the memory 12 are read out continuously at the specified address using the reference clock, and the editor monitors the contents of the memory 12 by using the operation input section 9 to set the device to edit point memory/pre-monitor mode. By setting this, the control for each part will be as follows.

Switch 17 is a-a ONL, switch 24 is d-e
becomes ON. The cpus also presets the address counter 13 as an initial value via the address counter information Yp+; stored in the RA, M7, the data bus 8, and the interface element 14.

A clock signal generated by the reference clock generation circuit 22 is input to the address counter 13 via the switch 24. The address counter 13 reads YP, -j2 F F F F-+0OOOo-+ based on the instruction from the CPU 5.
Memory 12 by changing the address in the order of xP1+NP1
At the same time as reading , this address is input via the interface element 14 to CP, U 5. The digital signal read out from the memory 12 is sent to the interpolation circuit 1.
6, a switch 17, a D/A converter 18, a low-pass filter 19, an amplifier 20, and a speaker 21 where the signal is monitored as a continuous audio signal.

If there is a problem with the edit point in the above edit point memory/pre-monitor mode, repeat the process starting from the process of determining the edit point in memory, and if a suitable edit point is obtained, proceed to the next step.

Next, in order to determine the boundary between C and D of the second tape in FIG. 2(b), part 2 of the second tape is played back by the second playback tape recorder and inputted to the P2 terminal. At this time, the g-i of the switch 11 is ON, and when PCM data is input to the P2 terminal, this data is cyclically recorded in the memory 12 via the switch 11.

The following explanation is omitted as it is the same as the content of determining the starting point 4 of the first tape shown in FIG. 2 (al).
2, and the address in memory 12 at the edit point is Xp 2
+ NP 2, set the time code information and sample point information to EP noon.

Next, the edit point set above (address xp in memory)
2+Np2) is correct or not, the contents of the memory 12 are continuously read and monitored for the specified addresses using the reference clock, but the editor enters the edit point memory/pre-monitor mode from the operation input section 9. With these settings, each part will be controlled as follows. The switches a-C of the switch 17 are turned on, and the switches d-e of the switch 24 are turned on. In addition, the CPU 5 inputs address counter information YP2+1 stored in the RAM 7 and data buzz 8.
, and preset the address counter 13 as an initial value via the interface element 14.

The signal is input to the address counter 13 via the switch 24. The address counter 13 reads YP2+1→2FFFF→000oO→Xp' based on the instruction from the CPU 6.
Change the address in the order of 2 +Np 2 and store it in the memory 12.
At the same time as the address is written, this address is input to the CPU 5 via the interface element 14. memory 12
The digital signal read out passes through the interpolation circuit 16, passes through the switch 17, the D/A converter 18, the low-pass filter 19, the amplifier Masuda, and is then monitored by the speaker 21 as a continuous audio signal. If there is a problem with the edit point in the edit point memory/pre-monitor mode described above, the process after the edit point determination process in memory is repeated, and if a suitable edit point is obtained, the process proceeds to the next step.

Next, set the fade characteristics for cross-fading A and D at the end of the tape on day 3 in Figure 2 (C) as follows: Without recording on the actual tape, The first tape pre-monitor operation is performed by running the playback tape recorder No. 227. When the editor sets the one mode, the CPU 5 commands the first and second playback side tape recorders from their respective edit points EP j + EP 2 to control the time required for monitoring and synchronized running control. (for example, L+ in Figure 2,
L2) When rewinding and playing, the respective edit points EP and EP2 obtained above are set to P1 and P in Figure 3 at the same time.
The respective tapes are synchronously controlled so that they are input into the tapes 2, and the timing is adjusted using an appropriate delay circuit. First, Figure 2 (
Only the signal A in a) is passed through the cross-fade processing circuit 16.

Next, near the editing point of the first tape in FIG. 2(a), a cross-fade is performed.Here, the cross-fade process will be specifically described. FIG. 9 is a detailed block diagram of the cross-fade processing circuit 15 in FIG. 3. Fi 1 is the PCM data input from P in FIG. 3, and Fi 2 is the PCM data input from P2.

When the editor sets this apparatus to the manual fader setting mode from the operation input section 9, the control signals to each section are as follows. Switches a and b of the switch 67 are turned on. 61 is a manual fader consisting of variable resistors, etc.; 62 is a fader interface that connects the manual fader 61 and the circuit; 63 is an A/D conversion circuit consisting of a sampling/holding circuit;
4 is a memory that stores the fader digital signals of the 63 A/D conversion circuit, e5 is an address counter that sets the address of the memory 64 according to the clock signal of the 66 clock generation circuit, and 67 is a fader of the A/D conversion circuit 63. a switch 6 for switching between the digital signal and the fader digital signal read out from the memory 64;
B is a multiplier circuit that calculates the PCM data input from Fil and the fader digital signal from switch 67; 69 is an inverter that inverts the fader digital signal from switch 7; And inverter 69?
71 is an adder circuit that adds the outputs of the multiplier circuits 68 and 70. When the editor operates the resistance value of the manual fader 61 from infinity to zero, the fader interface 62 converts the resistance value change into a DC voltage change. This DC voltage is sampled by the A/D conversion circuit 63 using the clock of the clock generation circuit 66 and converted into a digital signal. This characteristic is shown in FIG. 10 72. Then, the converted fader digital signal is cleared by the outside (third control output section), and the address is set by the address counter 06 starting from zero with the clock of the clock generation circuit e26.
4 is stored, it is simultaneously input to the multiplication circuit 68 via a-b of 7. The multiplication circuit 68 operates on the fader digital signal input from Fi 1 and fades out the PCM data input from Fi 1.

0 Further, the fader digital signal passed through the switch 67 is inverted by the inverter 69 and input to the multiplication circuit 70. The multiplication circuit 70 calculates the PCM data input from Fi2 and the fader digital signal input from the inverter 69, and calculates the PCM data input from Fi2.
Fade in data. Furthermore, the adder circuit 71 adds the PCM data faded out by the multiplier circuit 68 and the PCM data faded in by the multiplier circuit 70 to obtain a cyclosifted FO output. This Fo
is input to switch 17 in FIG.

Here, the specifications are assumed as follows. DC voltage from manual fader is 8 bits/sample.

Sampling frequency 30Hz, memory 300W
(1W=8 bits), if you do this, the memory 64.
The data stored in 71 is 10 seconds each since 300÷30=10.

Therefore, the editor should use the cross-fade processing circuit 16 shown in FIG.
0PCM data signal, switch 17, D/A converter 1
8. Low range fi! Letter 19, amplifier 2o, speaker 21
manual 7eder 61 while monitoring via
A unique cross-fade characteristic (for example, the characteristic shown in FIG. 10) can be obtained by manipulating the .

In the above configuration, since the fader digital signals input to the multiplier circuits 68 and 70 are complementary to each other, there is an advantage that the cross-fade output signal of the adder circuit 71 is not saturated.

Here, when the above-mentioned editor has set the manual fader setting mode, that is, the address counter 66
When the CPU 6 starts, the CPU 6 in FIG.
(Tpl and T
The time code signal (input from P2) is input to RAMy via time code interface circuits 25 and 26.

The time code at this time is assumed to be FTl.

Next, when the cross-fade time ends (in the above case, after 10 seconds have elapsed), the cross-fade processing circuit 15 passes only the signal input from P2 and stops writing to the memory 64.

As mentioned above, the exact editing point on the tape, the delay amount of the RAM memory delay circuit, the cross-fade timing, etc. are all determined by instructions from the CPU 5.

Through the above process, the first tape pre-monitor is completed, and the cross-fade characteristics near the editing point are stored in the built-in memory 64.

Next, a second tape pre-monitor is performed to check whether the cross-fade characteristics set in the first time are edited in the opposite way. The second tape pre-monitor performs the same operations and controls as the first tape pre-monitor, but
When the time code signal input as many times as Tpl through the two time code interface circuits becomes the same as the time code value ET1 set above, the CPUts
Clear the map and start. (The address counter is started from zero.) The address counter 66 reads out the memory 64 in which manual fader information (7E3 digital signals) is stored for 10 seconds. This read fader digital signal is input to a multiplication circuit 68 via a switch 67. The multiplier circuit 68 performs an operation on the PCM data input from one terminal and the fader digital signal read out from the memory 64, and fades out the signal. Further, via the switch 67, the fader digital signal inverted by the inverter 69 is input to the multiplier circuit To. The multiplication circuit 7o performs an operation on the PCM data inputted from the Fi2 terminal and the fader digital signal inputted to the inverter 69, and fades in the signal.

The adder circuit 71 adds the PCM data faded out by the multiplier circuit 68 and the PCM data shifted in by the multiplier circuit 75 to obtain a cross-faded Fo output. As mentioned above, the characteristics of the crossfade set during the first tape pre-monitor mode described above are
It can be reproduced by using the memory 64.

4 Complete. If there is a problem with the cross-fade characteristics near the editing point, the first tape pre-monitor operation is repeated and the fader digital signal is stored in the memory 640 again. If a suitable Δ cross-fade characteristic is obtained, proceed to the next editing operation.

In the editing process, the operation near each editing point is the same as the second tape pre-monitor, but the editing process involves playing back the necessary parts of the first and second tapes in Figure 2. Therefore, the first playback tape recorder must be set to the first tape recorder in Figure 2 (al.
Rewind the tape to just before the beginning of A. Also, the second playback side tape recorder is rewound by a length of time L2 from the editing point EP2 of C and D of the second tape in FIG. 2(b).

Then, when the first playback side tape recorder is played back and the starting point 4 of A in FIG. 2(a) is input as a digital signal to the P1 terminal in FIG. , and output to the R terminal via the switch 17. The R terminal is connected to a recording tape recorder.

Next, when the first playback tape recorder plays back up to L1° before the crossfade part of A in FIG. The respective tapes are synchronously controlled so that Ep2 and Ep2 are input to P1 and P2 in Fig. 3 at the same time, and the timing is adjusted using an appropriate delay circuit.After that, the operation is exactly the same as the second tape pre-monitor. By performing the operation, the data is edited in the recording side chip recorder connected to the R terminal as shown in FIG. 2 (C1).

According to the above embodiment, because the editing is done at the stage of the audio PCM signal itself, regardless of the recording format of the tape deck, the errors that occur during manual editing when newly reconfigured and recorded on the recording tape recorder. There is no lack of information at all.

Furthermore, since the output of the tape recorder on the playback side is temporarily stored in a memory, and this memory is read out for monitoring and editing, accuracy is high and editing points can be easily selected. In particular, by providing an interpolation circuit, it is possible to manually read the memory at a variable speed and select a sample that can be output easily in the same way as in the case of an analog signal tape. Furthermore, when performing cross-fade processing near the editing point, it is possible to create fade-out characteristics and fade-in characteristics using a single manual fader, and this can be done with the very simple configuration described above. realizable. Furthermore, since one fade characteristic is created by inverting the other fade characteristic, saturation does not occur when the signals processed for each characteristic are added together, which is a useful feature in practice. The above fade characteristics are stored in memory, and the 10000000 signal is also stored in another memory as described above, so it is possible to read these memories and rehearse.
Furthermore, the ability to easily rewrite the entire memory contents and rehearse them again has a great effect on increasing practicality.

As described above, according to the present invention, one of the fade-in and fade-out characteristics 3γ of a reproduced digital signal can be set by a single manual variable means, and the obtained characteristic is stored in a memory and read out from this memory. Is it possible to simultaneously obtain one 7-ade characteristic stored at the time and the other fade characteristic formed using this?
Therefore, editing with cross-fade processing is possible with a very simple configuration and easy operation.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of analog editing, FIG. 2 is an explanatory diagram showing the concept of the editing method adopted in the digital signal editing device of the present invention, and FIG. 3 is an implementation of the digital signal editing device of the present invention. A block diagram showing an example, FIG. 4 is a memory 12
FIG. 6 is a waveform diagram illustrating the concept of interpolation. FIG. 6 is a waveform diagram illustrating the interpolation function of this embodiment. FIG. 8 is a block diagram showing the configuration of the circuit. FIG. 9 is an explanatory diagram showing the write state of the memory 12. FIG.
FIG. 0 is a characteristic curve diagram showing a fade curve set by a manual fader. 9...Operation input section, 9'...Control output section, 12...Memory, 13...Address counter, 16...Cross Fade processing circuit, 16... Interpolation circuit, 18... D/A
Converter, 22...Reference clock generation circuit, 23
......Manual clock generator, 61...Manual fader-163...A/D conversion circuit, 64...Memory, 66...Address Counter, 66...Clock generation circuit, 68,
7-0...Multiplication circuit, 69...Inverter, 71...Addition circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 5 Figure 16

Claims (1)

[Claims] A fade characteristic setting means for manually variably setting the level change characteristic of a digital signal reproduced from a sound source such as a tape or a disk, a memory for storing the level change characteristic set by the fade characteristic setting means, and this memory. a first means for controlling the level of the reproduced digital signal by the readout output of the memory; and controlling the level of the other reproduced digital signal using another level change characteristic created from the readout output of the memory. a second means; and the first means. A digital signal editing device comprising: means for synthesizing the outputs of the second means and recording a cross-faded continuous output signal.