JPH01220284A - Editing device for pcm signal - Google Patents

Abstract

PURPOSE:To efficiently and surely perform editing work for piano music with fast touch, etc., by providing a cross fade control means to perform the variable control of a cross fade time corresponding to the readout speed of data by a readout control means. CONSTITUTION:An edit processing part 4 to which a reproducing PCM signal (PBDVR) obtained at the reproducing output terminal of a DVR1 is supplied and also, a reproducing PCM signal (PBDAT) obtained at the reproducing output terminal of a DAT2 is supplied via a decoder 3 is provided, and an edit output PCM signal (EDDVR) is supplied to the recording input terminal of the DVR1 via an encoder 5. And the data of each PCM signal in the neighborhood of an edit point written on each memory in the edit processing part is read out from each memory at speed set freely in a state where the edit points coincide, and a cross fade processing is performed by a cross fade processing means in which the variable control of the cross fade time is performed corresponding to the readout speed of the data. In such a way, it is possible to perform the editing work efficiently and surely by deciding the edit point for the piano music with fast touch, etc., accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a first PCM reproduced from a first recording medium.
Regarding a PCM signal editing device that records a signal on a second recording medium on which a second PCM signal is recorded, in particular, so-called electronic editing that stores data of each PCM signal near an editing point in a memory and performs editing processing. The present invention relates to an editing device having a processing function.

B. Summary of the Invention The present invention provides a first PCM reproduced from a first recording medium.
In a PCM signal editing device that performs so-called electronic editing processing by storing each data near an editing point of a second PCM signal reproduced from a second recording medium in a memory, each PCM signal near the editing point is stored in a memory. By reading the data from the memory at an arbitrary speed and performing cross-fade processing on each data with a cross-fade time corresponding to the read speed, the editing situation near the editing point of each PCM signal can be accurately perceived audibly. This allows editing work to be performed efficiently and reliably.

C. Conventional technology Conventionally, for example, a new PCM signal is inserted into a magnetic tape on which a PCM signal obtained by PCM modulating an audio signal is recorded, or it is recorded continuously to the original PCM signal. For example, in a digital audio/PCM signal editing device that performs editing work,
As disclosed in Publication No. 163672, etc., data in the vicinity of the editing point of each PCM signal to be edited is written in advance in memory, and the corresponding PCM signal is stored based on input data indicating the editing point.
There is a so-called electronic editing process in which CM signal data is read out from memory and edited.
JP-A-54-58013 and JP-A-55-1058
PCM to be edited as disclosed in Publication No. 71 etc.
By subjecting the signal data to cross-fade processing at the editing points, data is created that is audibly smooth and continuous.

D. Problems to be Solved by the Invention By the way, as mentioned above, in an editing device that has an electronic editing processing function that stores PCM signals in the vicinity of an editing point in a memory in advance and performs editing work, it is necessary to read out and monitor the data stored in the memory. By doing this, you can set editing points relatively easily and accurately using the so-called memory rehearsal that recognizes the editing status using F11, but when editing piano pieces that have a quick touch, etc. Even with the above-mentioned memory rehearsal, there are problems in that it is extremely difficult to accurately determine the edit point, and it is also impossible to accurately grasp the status of cross-fade processing of the PCM signal at the edit point.

- Therefore, in view of the above-mentioned conventional problems, the present invention has been proposed.
The first PCM signal reproduced from the first recording medium is transferred to the second
P to be recorded on the second recording medium on which the PCM signal of
The purpose of the CM signal editing device is to efficiently and reliably perform editing work on fast-touch piano pieces, etc., by storing PCM signals near the editing point in advance in memory and electronically editing them. To do this, read the data of each PCM signal near the editing point from the memory at an arbitrary speed, apply cross-fade processing to each data with a cross-fade time corresponding to the read speed, and perform memory rehearsal at an arbitrary speed. The purpose of the present invention is to provide a PCM signal editing device with a new configuration that enables the following.

E Means for Solving the Problems In order to achieve the above-mentioned object, the present invention converts a first PCM signal reproduced from a first recording medium into a second recording medium on which a second PCM signal is recorded. In an editing device for a PCM signal recorded in a PCM signal, the first memory stores data in the vicinity of an editing point of a first PCM signal reproduced from the first recording medium; The second P
a second memory for storing data in the vicinity of the edit point of the CM signal; and a write control means for receiving input data indicating the edit point and controlling writing of data of each PCM signal in the vicinity of the edit point in the corresponding memory. , a read control means for controlling the data of each PCM signal near the edit point written in each of the above-mentioned memories to be read out at an arbitrarily settable speed with the edit points coincident; and a cross-fade processing means with a variable cross-fade time that performs cross-fade processing on each data near the editing point of the second PCM signal, and a cross-fade processing means according to the reading speed of the data by the read-out control means,
The present invention is characterized in that a cross-fade control means for variable control of the cross-fade time is provided.

F. Function In the PCM signal editing device according to the present invention, the data of each PCM signal in the vicinity of the editing point written in each memory is read out from each of the memories at an arbitrarily settable speed with the editing points coincident. A cross-fade processing means whose cross-fade time is variably controlled according to the read speed of the data performs cross-fade processing on the data of each PCM signal near the edit point read from each of the memories at the edit point. be done.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The embodiment shown in the block diagram of FIG. 1 is a helical scan digital video tape recorder (DVR).
1 is used on the recording side, and a fixed head type digital
The present invention is applied to a PCM signal editing device using an audio tape recorder (DAT) 2 on the playback side.

In the editing device of this embodiment, a reproduced PCM signal (PBov*) obtained at the reproduction output terminal of the DVR 1 is supplied, and a reproduction PC signal obtained at the reproduction output terminal of the DAT 2 is supplied.
An editing processing section 4 is provided to which the M signal (PRIIAA) is supplied via a decoder 3, and an editing output PCM signal (EDov++) from the editing processing section 4 is supplied via an encoder 5 to the recording input terminal of the DVR 1. It looks like this. This editing device also includes a reproduced PCM signal (PBDVR') output from the DVR 1, a reproduced PCM signal (PBIIAT) output from the DAT 2, and an edited output PCM signal (EDIIV) output from the editing processing section 4.
R) is provided with a digital-to-analog (D/A) converter 7 through a changeover switch 6;
/A converter 7 converts the various PCM signals (PBov
An audio signal obtained by analogizing ++), (PBIIAT), and (EDDVII) is supplied to a monitor speaker 9 via an audio amplifier 8. Note that the edit output PCM signal (1!Dnv*) output from the edit processing section 4 is passed through a delay circuit lO having a delay time equal to the sum of the data processing times of the decoder 3 and encoder 5. The signal is supplied to the switch 6 mentioned above.

Furthermore, the editing apparatus of this embodiment further includes a fader operation input section 11. A control unit 14 that receives operation input data from the key operation input unit 12, the Jeddah dial operation input unit 13, etc.
and a display section 15 controlled by the control section 14, and the control section 14 remotely controls the DVR 1 and DAT 2, the editing processing section 4 and the changeover switch 6.
, the display of the display section 15, and the like.

The editing processing section 4 in this embodiment is configured as shown in the block diagram of FIG.
is supplied to the first memory 41 and the clock generation circuit 42.

The clock generation circuit 42 generates the reproduced PCM signal (P
Bov*), and this sampling clock FS is supplied from a changeover switch 43 to an address counter 45 via a programmable frequency divider 44. The address counter 45 forms address data for the first memory 41 by counting the clocks supplied from the frequency divider 44, and supplies the address data to the first memory 41. , latch circuit 46
and the first and second data comparators 47 and 48.

The editing processing unit 4 also includes a clock generation circuit 49 controlled by the control unit 14, and the clock generated by the clock generation circuit 49 is transmitted from the changeover switch 43 to the address counter 45 via the programmable frequency divider 44. It is designed to be supplied to

Said changeover switch 43. Programmable frequency divider 44
and the address counter 45 are controlled by the control unit 14, and the playback P output from the DVR 1.
In the operation mode in which data near the edit point of the CM signal (PRIlv*) is written to the first memory 41, the changeover switch 43 selects the clock generation circuit 42, and the frequency division ratio of the programmable frequency divider 44 is changed. (1/
N) is set to 1, and the data of the reproduced PCM signal (PB, □) is set to 1 in accordance with the address data formed by the address counter 45 based on the sampling clock FS generated by the clock generation circuit 42. 1
The information is sequentially written into the memory 41 of.

In the write operation mode, the control unit 14 inputs an edit point (Pop) from the key operation input unit 12.
), the address data (ADR(11)) at that timing is fetched via the latch circuit 46, and the address data by the address counter 45 becomes the address data (ADRe+
), when the address data advances by 1/2 of the storage capacity of the first memory 41, the operation mode is canceled and the write operation to the first memory 41 is completed.

When the control unit 14 cancels the write operation mode, the control unit 14 outputs address data (AD) indicating the edit point (Pop).
Ro+) is preset in the address counter 45, the changeover switch 43 is controlled to select the clock generation circuit 49, and the key operation input section 1
Address data indicating the editing point (Pot) is generated by supplying clock pulses of the number of pulses from the clock generation circuit 49 to the address counter 45 according to the input data obtained by operating the input section 2 or the Jeddah dial operation input section 13. (ADRo+) modification is accepted.

Further, when an operation mode for reading data of the reproduced PCM signal (PBDv, l) near the editing point written in the first memory 41 as described above is specified, the control unit 14 generates the clock signal. A predetermined frequency (
f3) sampling clock FS is output, and based on the sampling clock FS, the reproduced PCM signal (PB□
control to read out the data. The reproduced PCM signal (P
The data of BD□) is supplied to a multiplier 61 for cross-fade processing via an interpolation circuit 50, and the multiplier 61 receives control coefficient data given from the cross-fade control circuit 63 based on the timing (to) of the editing point. By multiplying the signal by (α), the signal is subjected to cross-fade processing as shown in A in FIG. 3 before being supplied to the data adder 65.

Here, in the assemble editing mode where there is one editing point, the control section 14 only accepts the import of address data (ADRo+) indicating the editing point (PH1) and its modification, but when there are two editing points, In the case of the insert editing mode, the address data (ADRs+) indicating the editing start point (P!+) is loaded within the storage capacity of the memory 41 in the recording operation mode described above, and the recording operation mode is canceled. Address data (ADR1+) indicating the editing end point (p!+) is taken in from , and corrections to each of the address data (ADRs+) and (ADRt+) are accepted individually.

Note that the control unit 14 generates address data (^DR) indicating an edit point (Pop) in the assemble edit mode.
o+), or address data (ADR
s+) and the address data (
ADR1□) is applied to each of the data comparators 47 and 48.

Each of the data comparators 47 and 48 determines the timing of the edit point by comparing the address data formed by the address counter 45 and the address data indicating the edit point given by the control section 14. The signals are respectively formed and the timing signals are supplied to the crossfader control section 63.

Further, the editing processing section 4 in this embodiment is configured to output a reproduced PCM signal (
PBoAt) is the second memory 51 and clock generation circuit 5.
2.

The clock generation circuit 52 generates a sampling clock FS for the reproduced PC, M signals (PBDAT), and supplies this sampling clock FS from a changeover switch 53 to an address counter 55 via a programmable frequency divider 54. It looks like this. The address counter 55 forms address data for the second memory 51 by counting the clocks supplied from the programmable frequency divider 54, and supplies the address data to the second memory 51. At the same time, it is supplied to the latch circuit 56.

The editing processing unit 4 also includes a clock generation circuit 59 controlled by the control unit 14, and the clock generated by the clock generation circuit 59 is transmitted from the changeover switch 53 to the address counter 55 via the programmable frequency divider 54. It is designed to be supplied to

Said changeover switch 53. Programmable frequency divider 54
The address counter 55 is controlled by the control unit 14, and when in the operation mode in which data near the edit point of the reproduced PCM signal (PBoay) outputted from the DAT 2 is written into the second memory 51, the address counter 55 is The changeover switch 53 selects the clock generation circuit 52 and sets the frequency division ratio (1/1) of the programmable frequency divider 54.
N) is set to 1, and the data of the reproduced PCM signal (PB++at) is set to 1 in accordance with the address data formed by the address counter 55 based on the sampling clock FS generated by the clock generation circuit 52. The information is sequentially written into the memory 51.

In the write operation mode, the control unit 14 inputs the edit point (log
), the address data (ADRoz) at that timing is sent to the latch circuit 5.
6, the address data by the address counter 55 becomes the address data (ADRoz).
When the address data advances by 1/2 of the storage capacity of the second memory 51, the operation mode is canceled and the write operation to the second memory 51 is completed. .

When the control unit 14 cancels the write operation mode, the control unit 14 outputs address data (AD) indicating the edit point (pot).
Roz) in the address counter 55, the changeover switch 53 is controlled to select the clock generation circuit 59, and the key operation input section 1
Address data indicating the edit point (pot) is generated by supplying clock pulses of a number of pulses from the clock generation circuit 59 to the address counter 55 according to the input data obtained by operating the input section 2 or the Jeddah dial operation input section 13. Accepts corrections to (ADRoz).

Here, in the assemble editing mode where there is one editing point, the control section 14 only accepts the import of address data (ADRoz) indicating the editing point (f'oz) and its modification, but when there are two editing points, In the case of insert editing mode, if the address data (ADRsz) indicating the editing start point (ps□) is captured in the above-mentioned recording operation mode within the storage capacity of the memory 51, the above-mentioned recording operation mode is canceled. Then, based on the address difference between the editing start point (P□) and the editing start point (P□) of the data of the reproduced PCM signal (PR+□) near the editing point previously written in the first memory 41, Then, address data (ADRxz) indicating the editing end point (hz) is automatically calculated, and modifications to each of the address data (ADRsz) and (ADRtz) are individually accepted.

Further, when an operation mode for reading data of the reproduced PCM signal (PBDAT) in the vicinity of the editing point written in the second memory 51 as described above is designated, the control section 14 controls the clock generation circuit 59. to a predetermined frequency (f
, ) is output, and based on the sampling clock FS, the reproduced PCM signal (PBeAt
), the second memory 5 controls the reading of data.
The reproduced PCM signal (PB
DAT) is supplied to a multiplier 62 for cross-fade processing via an interpolation circuit 60, and the multiplier 62 receives data from the cross-fade control circuit 6.3 based on the timing (to) of the editing point. Control coefficient data (α−
1), the data is subjected to cross-fade processing as shown in A in FIG. 3, and then supplied to the data adder 65 via the multiplier 68 for spot erase processing. There is.

The addition output data from the data adder 65 is sent to a multiplier 6 which performs fader processing on the beginning and end portions of the editing output.
6 as an editing output PCM signal (EDDVII).

Further, the control unit 14 controls each reproduced PCM signal (PBDVR), (PRD) near the editing point in this way.
Each playback P in rehearsal mode or concentrated output mode is written to the memory 41.51 in which data of
In order to read out the data of the CM signals (PBov++) and (PeoAy) consecutively at the editing points, each address counter 45.55 is preset so that the editing points set as described above coincide with each other. I have to.

Here, the cross-fade control circuit 63 is controlled by the control unit 14 to specify the cross-fade time (TX) in correspondence with the frequency division ratio (1/N) of each of the programmable frequency dividers 44 and 54. Data (Δ・N) is given, and each control coefficient data (α), (α
-1) to each of the multipliers 61 and 62 for cross-fade processing every 1/(N-fs).

Then, the frequency division ratio (1/N) of the programmable frequency dividers 44, 54 is set to 1, and a predetermined sampling frequency (f,
), each playback P near the editing point from each memory 41.51 above.
In the normal read mode with N=1 in which the data of the CM signals (PBov++) and (PBDAT) are read, the fader time of the TX changes in steps specified by Δ for each sampling clock FS, as shown in FIG. The cross-fade control circuit 63 transfers each control coefficient data (α) and (α-1) to each multiplier 6 for cross-fade processing.
1.62. Also, by setting N22, each reproduced PCM signal (PB++v view), (PBoat
) is read out at low speed in the N22 low-speed read mode, as shown in Figure 5, the sampling frequency (
Each control coefficient data (TX' = N-Tx) has a fader time that changes in steps determined by the above Δ for each clock of 1/N frequency H/N - r s) of TX'(TX' = N-Tx). α°), (α−1″) are supplied by the crossfade control circuit 63 to each multiplier 61, 62 for crossfade processing. , each control coefficient data (α゛) and (α-1') in the case of a readout speed that is 1/2 of the readout speed in the normal readout mode is shown.

In the editing device of this embodiment, in the rehearsal mode, each of the programmable frequency dividers 44, 54
The read address data is generated by each of the address counters 45 and 55 based on the 1/N divided output of the sampling clock FS of a predetermined sampling frequency (f, ) by setting the frequency division ratio to 1/N. When the data of each reproduced PCM signal (PB□=), (PBoAt) near the above editing point is time expanded and read out, and memory rehearsal is performed at an arbitrary speed as shown in B in Fig. 3, Each control coefficient data (α゛), (α-1°) of the fader time TX'(TX' = N-TX) is given to each multiplier 61, 62 for the cross-fade processing, and the data is Crossfade time (TX
') cross-fade processing is applied. In the low-speed read mode, each memory 41. 5
1 and each interpolation circuit 50.1 provided between each multiplier 61.62.
Performed at 60.

In this way, you can perform memory rehearsal at any speed and set the crossfade time (
By performing cross-fade processing on PCM signals (TX'), it is possible to audibly accurately recognize the cross-fade processing status of the PCM signal at the editing point, and the editing points can be determined accurately and efficiently, even for fast-touch piano pieces. You can perform editing tasks easily and reliably.

Furthermore, in the editing device of this embodiment, the display section 1
5, as shown in FIG. 6, first and second bar graph display areas AR, each having a length corresponding to the storage capacity of the first and second memories 41 and 51 of the editing processing section 4; ,A
R, are arranged in parallel, and the display is controlled as follows by the control section 14 according to the access state of each of the memories 41 and 51.

For example, in the assemble edit mode, by setting the above edit point (P0+), the above edit point (Po
t) When the data of the nearby reproduced PCM signal (PBnv*) is written into the first memory 41, as shown in FIG.
Marker (M.1) is displayed based on DRo+), and the position of the marker (M.I), that is, the edit point (
An address area for valid data and an address area for invalid data whose boundary is the address data (ADRo+) indicating P o + ) are displayed in the first bar graph display area AR so that they can be visually distinguished. Similarly, edit point (po
z), the data of the reproduced PCM signal (PBDAa) near the editing point (P, z) is changed to the second
When written to the memory 51 of , the above editing point (Paw)
The marker (M.I) is displayed based on the address data (^DRoz) indicating the above marker (M.2).
In other words, the address area of valid data and the address area of invalid data whose boundary is the address data (ADRO2) indicating the edit point (pH2) are displayed in the second bar graph display area A Rt so that they can be visually identified. Ru. The positions of the above markers (M.+) and (M.2) and the display status of each bar graph display area API and AR1 are determined by the correction processing of each editing point (Pot) and (Pat) as shown in Fig. 7. It changes as shown by the broken line. In the rehearsal mode or edit output mode, the access status of the address area of each valid data in each of the memories 41, 51 is displayed as a bar graph over time as shown by arrows in FIG.

In addition, in the case of insert W collection mode, by setting the above-mentioned editing start point (psi), the data of the reproduced PCM signal (PB D□) near the above-mentioned editing start point (Pie) is stored in the above-mentioned first memory. 41, and
By setting the above editing end point (P□),
As shown in FIG. 8, each address data (ADR) indicates the editing start point (Pie) and the editing end point (Pie).
s+), each marker (Ms+) based on (ADR□)
, (Mz+) are displayed, and each of the above markers (
L+), (MEI) position, that is, the editing start point (P
ie) and each address data (ADRs+) and (ADR1+) indicating the editing end point (P□). Display area AR
.

will be displayed. Similarly, by setting the above editing start point (Psz), the data of the reproduced PCM signal (PBDAa) near the above editing start point (Psi) is written to the second memory 51, and the above editing starts. By setting the end point (Pg□), each marker (Msz), (Mix ) is displayed, as well as the positions of each marker (Mjz) and (island), that is, the editing start point (Psi) and editing end point (Ptz).
Each address data (8DRsz), (ADRt
The address area for valid data and the address area for invalid data with boundary i) are displayed in the second bar graph display area AR so that they can be visually identified. In addition, each of the above markers (Ms+), (lb+), (Mst), (
Mtz) position and each bar graph display area A R+
, A The bar graph display state of R2 is displayed at each editing point (Pi
e), (Piθ, (Psi), (Piz) are moved by the correction processing. Then, in the rehearsal mode or edit output mode, the access state of the address area of each valid data in each of the memories 41 and 51 is changed to the eighth A bar graph is displayed as time passes as indicated by arrows in the figure.

In addition, as shown in FIGS. 6 to 8 above,
The display states of the display areas AR, AR, arranged on the left side of the bar graph display areas A R+ and A Rz are controlled by the control unit 14, and the tape running positions of the DVR1 and DAT2 are stored in the respective memories. Each PCM signal (PR
III), (PBDAT) is approached by blinking. Also,
Each of the above bar graph display areas A R+.

Each marker (IIls) placed near both ends of A Rz
+L(m(+)+ (msz), (mtt) are the above-mentioned respective edited fish (pot), (Pot).

This indicates the setting limits for (Ps+), (Pi+), (Psz), and (ht), and indicates the setting limits for each PCM signal (PBDV++) described above.
), (PBoat), the display is automatically controlled by the control section 14 according to the type of recording/reproducing device that provides the signals, the constant of the crossfader, etc.

Effects of the Invention In the PCM signal editing device according to the present invention, the data of each PCM signal in the vicinity of the editing point written in each memory is transferred from each of the above-mentioned memories at an arbitrarily settable speed with the editing points coincident. A cross-fade process is performed at the edit point on the data of each PCM signal near the edit point read from each memory by the cross-fade processing means whose cross-fade time is variably controlled according to the read speed of the data. is applied, so you can perform memory rehearsal at any speed and accurately recognize the cross-fade processing status of the PCM signal at the editing point, and accurately identify the editing point even in fast-touch piano pieces. You can make decisions and perform editing work efficiently and reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a PCM signal editing device according to the present invention, FIG. 2 is a block diagram showing the configuration of an editing processing section constituting the editing device, and FIG. 3 shows normal read mode and FIG. 4 is a schematic diagram showing the contents of each control coefficient data provided by the crossfader control section in the normal read mode, and FIG. 5 is a schematic diagram showing the status of each memory rehearsal in the low speed read mode. FIG. 6 is a schematic diagram showing the contents of each control coefficient data provided by the fader control section; FIG. 6 is a schematic diagram showing the display area of the display section constituting the editing device; FIG.
The figure is a schematic diagram showing an example of the display content of the display unit in the assemble editing mode, and FIG. 8 is a schematic diagram showing an example of the display content of the display unit in the insert editing mode.

Claims (1)

[Claims] The first PCM signal reproduced from the first recording medium is
P to be recorded on the second recording medium on which the PCM signal of
In the CM signal editing device, a first memory for storing data near an editing point of a first PCM signal reproduced from the first recording medium; a second memory for storing data near the edit point of the PCM signal; and a second memory for storing data near the edit point of the PCM signal;
a write control means for controlling writing of CM signal data into the corresponding memory; and each PCM near the edit point written in each of the above memories.
a readout control means for controlling readout of signal data at an arbitrarily settable speed with edit points matching, and first and second PCMs read out from each of the memories;
cross-fade processing means that performs cross-fade processing on each data in the vicinity of the editing point of the signal, the cross-fade time being variable; and the cross-fade time being variable control according to the reading speed of the data by the read-out control means. A PCM characterized in that it is provided with a cross-fade control means for performing
Signal editing device.