JPH01220285A - Editing device for pcm signal - Google Patents

Abstract

PURPOSE:To efficiently and surely perform insert editing less than several seconds such as the substitution of a notation, etc., by providing a cross fade control means to operate a cross fade processing means at an edit start point and an edit end point for the data of each PCM signal in the neighborhood of an edit point written on each memory. CONSTITUTION:An edit processing part 4 to which a reproducing PCM signal (PBDVR) obtained at the reproducing output terminal of a DVR1 is supplied, and also, a reproducing PCM signal (PBDAT) obtained at the reproducing output terminal of a DAT2 is supplied is provided via a decoder 3, and an edit output PCM signal (EDDVR) by the edit processing part 4 is supplied to the recording input terminal of the DVR1 via an encoder 5. And the data of the PCM signal in the neighborhood of the edit point written on each memory in the edit processing part is written on a corresponding memory, and the data of each PCM signal in the neighborhood of the edit point is read out from the memory in a state where the edit point coincide, then, the cross fade processing is applied at the edit start point and the edit end point. In such a way, it is possible to perform the insert editing in a short time such as the substitution of the notation in piano music with fast touch, etc., extremely efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a first PCM reproduced from a first recording medium.
Regarding a PCM signal editing device that records a signal on a second recording medium on which a second PCM signal is recorded, in particular, so-called electronic editing that stores data of each PCM signal near an editing point in a memory and performs editing processing. The present invention relates to an editing device having a processing function.

B. Summary of the Invention The present invention provides a first PCM reproduced from a first recording medium.
In a PCM signal editing device that performs so-called electronic editing processing by storing each data in the vicinity of an editing point of a second PCM signal reproduced from a signal and a second recording medium in a memory, each data in the vicinity of an editing point of a second PCM signal reproduced from the memory is stored in a memory. By reading out the data of the PCM signal with the editing points matching, and performing cross-fade processing at the editing start point and editing end point,
This allows short-time insert editing to be performed efficiently and reliably.

C. Conventional technology Conventionally, for example, a new PCM signal is inserted into a magnetic tape on which a PCM signal obtained by PCM modulating an audio signal is recorded, or it is recorded continuously to the original PCM signal. For example, in a digital audio/PCM signal editing device that performs editing work,
As disclosed in Publication No. 163672, etc., data in the vicinity of the editing point of each PCM signal to be edited is written in advance in memory, and the corresponding PCM signal is stored based on input data indicating the editing point.
There is a so-called electronic editing process in which CM signal data is read out from memory and edited.
JP-A-54-58013 and JP-A-55-1058
PCM to be edited as disclosed in Publication No. 71 etc.
By applying cross-fade processing to the signal data at the editing points, the data appears to be audibly smooth and continuous.

I have to.

D. Problem to be Solved by the Invention By the way, as mentioned above, in an editing device having an electronic editing processing function that stores PCM signal data in the vicinity of an editing point in a memory in advance and performs editing work, it is difficult to read out the data stored in the memory. By so-called memory rehearsal, which confirms the editing status by monitoring the insert, the editing start and end points for insert editing are determined individually, and the playback and recording devices are operated synchronously in playback mode to actually run the tape. Since previews are performed at the same time, the efficiency of the editing work is extremely low, and the repeated running of the tape is required, which places a heavy burden on the mechanism. In mask rings of compact discs, corrections are often made by insert editing after assembly editing, and in the actual insert I collection, there are many insert edits that take less than a few seconds, such as replacing notes, so it is important to improve the efficiency of short-time insert editing. It is required to increase.

Therefore, in view of the conventional problems as described above, the present invention provides a PC that records a first PCM signal reproduced from a first recording medium onto a second recording medium on which a second PCM signal is recorded.
The purpose of the M signal editing device is to efficiently and reliably perform insert W collections of several seconds or less, such as replacing notes, by editing the data of each PCM signal near the editing point with the editing point matching. An object of the present invention is to provide a PCM signal editing device having a novel configuration, which reads data from a memory and performs cross-fade processing at an editing start point and an editing end point.

Eil! Means for Solving the Problems In order to achieve the above-mentioned object, the present invention transfers a first PCM signal reproduced from a first recording medium to a second recording medium on which a second PCM signal is recorded. In an editing device for a PCM signal to be recorded, a first memory stores data near an editing point of a first PCM signal reproduced from the first recording medium, and a first memory for storing data near an editing point of the first PCM signal reproduced from the second recording medium. second P
a second memory for storing data in the vicinity of the edit point of the CM signal; and a write control means for receiving input data indicating the edit point and controlling writing of data of each PCM signal in the vicinity of the edit point in the corresponding memory. , a read control means for controlling the reading of data of each PCM signal near the editing point written in each of the above-mentioned memories in a state where the editing points coincide; and a PC near the editing point written in each of the above-mentioned memories.
A cross-fade processing means performs the above-mentioned cross-fade processing at the editing start point and the editing end point of the M signal, and a cross-fade processing means performs the above-mentioned cross-fade processing at the editing start point and the W4 collection end point for the data of each PCM signal near the editing point written in each of the above-mentioned memories. The present invention is characterized in that a cross-fade control means is provided for controlling the operation of the cross-fade processing means.

F. Effect In the PCM signal editing device according to the present invention, the data of each PCM signal near the editing point written in each memory is written into the corresponding memory, and the data of each PCM signal near the editing point is edited from the memory. Read out when the points match, and perform cross-fade processing at the editing start point and editing end point.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The embodiment shown in the block diagram of FIG. 1 is a helical scan digital video tape recorder (DVR).
1 is used on the recording side, and a fixed head type digital
The present invention is applied to a PCM signal editing device using an audio tape recorder (DAT) 2 on the playback side.

In the editing device of this embodiment, the reproduced PCM signal (PBnv+t) obtained at the reproduction output terminal of the DVR 1 is supplied, and the reproduced PCM signal (PBnv+t) obtained at the reproduction output terminal of the DAT 2 is supplied.
An editing processing section 4 is provided to which a CM signal (PB□T) is supplied via a decoder 3, and an editing output PCM signal (EDov*) from the editing processing section 4 is sent via an encoder 5 to a recording input terminal of the DVR 1. supply. This editing device also includes a reproduced PCM signal (PBov++) output from the DVR 1, a reproduced PCM signal (PBDAT) output from the DAT 2, and the editing processing unit 4.
The output PCM signal (EDov++) output from the digital
An analog (D/A) converter 7 is provided, and the D/A converter 7 converts the various PCM signals (PBov++)
, (PBIIAT), and (!!Dovi) are converted into analog signals and are supplied to a monitor speaker 9 via an audio amplifier 8. The editing output PCM signal (1!nov, l) output from the editing processing section 4 is passed through a delay circuit 10 having a delay time equal to the sum of the data processing times of the decoder 3 and encoder 5. and is supplied to the switch 6.

Furthermore, the editing apparatus of this embodiment further includes a fader operation input section 11. A control section 14 that receives operation input data from the key operation input section 12, jog dial operation input section 13, etc.; and a display section 15 that is controlled by the control section 14.
The controller 14 controls the DVR 1 and the DA.
It performs remote control of T2, operation control of the editing processing section 4 and changeover switch 6, display control of the display section 15, and the like.

The editing processing section 4 in this embodiment is configured as shown in the block diagram of FIG. 2, and has a reproduction PCM signal (PBov++
) is supplied to the first memory 41 and the clock generation circuit 42.

The clock generation circuit 42 generates the reproduced PCM signal (P
The sampling clock FS of B□, l) is generated, and this sampling clock FS is supplied from a changeover switch 43 to an address counter 45 via a programmable frequency divider 44. The address counter 45 forms address data for the first memory 41 by counting the clocks supplied from the frequency divider 44, and supplies the address data to the first memory 41. , latch circuit 46
and the first and second data comparators 47 and 48.

The editing processing unit 4 also includes a clock generation circuit 49 controlled by the control unit 14, and the clock generated by the clock generation circuit 49 is transmitted from the changeover switch 43 to the address counter 45 via the programmable frequency divider 44. It is designed to be supplied to

Said changeover switch 43. Programmable frequency division H44
and the address counter 45 are controlled by the control unit 14, and the playback P output from the DVR 1.
In the operation mode in which data near the edit point of the CM signal (PBovIl) is written to the first memory 41, the changeover switch 43 selects the clock generation circuit 42, and the division ratio ( 1/
N) is set to 1, and the data of the reproduced PCM signal CPBnv*) is set to 1 in accordance with the address data formed by the address counter 45 based on the sampling clock FS generated by the clock generation circuit 42. The information is sequentially written to the memory 41.

In the write operation mode, the control unit 14 inputs the edit point (PO2) from the key operation input unit 12.
), the address data (ADROI) at that timing is sent to the latch circuit 4.
6, the address data by the address counter 45 becomes the address data (ADR(I+
), when the address data advances by 1/2 of the storage capacity of the first memory 41, the operation mode is canceled and the write operation to the first memory 41 is completed.

When the control unit 14 cancels the write operation mode, the control unit 14 outputs address data (AD) indicating the edit point (Pop).
ROI) is preset in the address counter 45, the changeover switch 43 is controlled to select the clock generation circuit 49, and the key operation input section 1
Address data indicating the editing point (POP) is generated by supplying clock pulses from the clock generation circuit 49 to the address counter 45, the number of which corresponds to the manual data obtained by operating the jog dial operation input section 13 or the like. (ADROI) modification is accepted.

The control unit 14 also controls the reproduction PCM signal (PBovI) written in the first memory 41 as described above.
When the operation mode for reading out data near the edit point (l) is specified, the clock generation circuit 49 generates a predetermined frequency (
f, ) sampling clock FS is output, and the vicinity of the edit point of the reproduced PCM signal (PBov*) is output from the first memory 41 using the address data formed by the address counter 45 based on the sampling clock FS. The reproduced PCM signal (PBovIl) read from the first memory 41 controls the reading of data of
The data near the editing point of ! is supplied to a multiplier 61 for cross-fade processing via the interpolation circuit 50, and the multiplication! S
At step 61, by multiplying the control coefficient data (α) given by the timing (to) of the editing point from the cross-fade control circuit 63, cross-fade processing is performed as shown in A in FIG. 3, and then the data is added. The water is supplied to a container 65.

Here, in the assemble editing mode where there is one edit point, the control section 14 only accepts the import of address data (ADROI) indicating the edit point (POP) and its modification, but when the number of edit points is two In the case of the insert editing mode, the address data (ADROI) indicating the editing start point (Ps+) is imported within the storage capacity of the memory 41 in the recording operation mode described above, and the editing is started after canceling the recording operation mode. The address data (ADROI) indicating the end point (P!t) is taken in, and each address data (ADROI) and (ADH!+) can be individually modified.

Note that the control unit 14 generates address data (ADR) indicating an editing point (pot) in the assemble editing mode.
OI), or address data (ADR) indicating the editing start point (Ps+) in the above insert editing mode.
OI) and address data (Pt+) indicating the editing end point (Pt+).
80R1+) is applied to each of the data comparators 47 and 48.

Each of the data comparators 47 and 48 determines the timing of the edit point by comparing the address data formed by the address counter 45 and the address data indicating the edit point given by the control section 14. The signals are respectively formed and the timing signals are supplied to the crossfader control section 63.

Further, the editing processing section 4 in this embodiment is configured to output a reproduced PCM signal (
PBoat) is the second memory 51 and clock generation circuit 5
2.

The clock generation circuit 52 generates the reproduced PCM signal (P
It generates the sampling clock FS of BoA a), and this sampling clock FS is supplied from the changeover switch 53 to the address counter 55 via the programmable frequency divider 54. The address counter 55 forms address data for the second memory 51 by counting the clocks supplied from the programmable frequency divider 54, and supplies the address data to the second memory 51. With,
The signal is supplied to a latch circuit 56.

The editing processing unit 4 also includes a clock generation circuit 59 controlled by the control unit 14, and the clock generated by the clock generation circuit 59 is transmitted from the changeover switch 53 to the address counter 55 via the programmable frequency divider 54. It is designed to be supplied to

Said changeover switch 53. Programmable frequency divider 54
The address counter 55 is controlled by the control section 14, and the playback P output from the DAT2.
In the operation mode in which data near the edit point of the CM signal (PBDAT) is written to the second memory 51, the changeover switch 53 selects the clock generation circuit 52, and the division ratio ( 1/N
) is set to 1, and according to the address data formed by the address counter 55 based on the sampling clock FS generated by the clock generation circuit 52,
The data of the reproduced PCM signal (PBDAa) is transferred to the second
The information is sequentially written into the memory 51 of.

In the write operation mode, the control unit 14 inputs an edit point (poz) from the key operation input unit 12.
), the address data (ADRoz) at that timing is sent to the latch circuit 5.
6, the address data by the address counter 55 becomes the address data (ADR(12
), when the address data advances by 1/2 of the storage capacity of the second memory 51, the operation mode is canceled and the write operation to the second memory 51 is completed.

When the control unit 14 cancels the write operation mode, the control unit 14 outputs address data (AD) indicating the edit point (PO2).
Roz) in the address counter 55, the changeover switch 53 is controlled to select the clock generation circuit 59, and the key operation input section 1
Address data indicating the edit point (P+z) is generated by supplying clock pulses of a number of pulses from the clock generation circuit 59 to the address counter 55 according to the input data obtained by operating the input unit 2 or the Jeddah dial operation input unit 13. Accepts corrections to (ADRoz).

Here, in the assemble editing mode where there is one editing point, the control section 14 only accepts the fetching of address data (ADRoz) indicating the editing point (Pot) and its modification, but when the number of editing points is two In the case of insert editing mode, if the address data (ADRsz) indicating the editing start point (Psi) is captured in the above-mentioned recording operation mode within the storage capacity of the memory 51, then after canceling the above-mentioned recording operation mode, , the start point (ps+) and the end point of editing (P t r
), address data (ADRtz) indicating the editing end point (P, ) is automatically calculated, and each of the above address data (ADRsz), (ADRtz)
We now accept individual amendments.

Further, when the control unit 14 is designated with an operation mode for reading out the reproduced PCM signal (PBoAt) near the editing point written in the second memory 51 as described above,
A sampling clock FS of a predetermined frequency (f, ) is outputted from the clock generation circuit 59, and the address data generated by the address counter 55 based on the sampling clock FS is used to output the second memory 5I.
Control is performed to read out the reproduced PCM signal (PBDA□) near the editing point. The reproduced PCM signal (PBoAa) near the editing point read out from the second memory 51 is supplied to a multiplier 62 for cross-fade processing via an interpolation circuit 60, and the multiplier 62 performs the above-mentioned By multiplying the cross-fade control circuit 63 by the control coefficient data (α-1) given from the timing (to) of the editing point, cross-fade processing is performed as shown in A in FIG. The data is supplied to the data adder 65 via a multiplier 68 for fader processing.

The addition output data from the data adder 65 is sent to a multiplier 6 which performs fader processing on the beginning and end portions of the editing output.
6 and output as an editing output PCM signal (EDDV!1).

Furthermore, the control unit 14 controls each reproduced PCM signal (PBov*) near the editing point, (PBaA
Each playback PCM signal (
In order to read the data of PBov++) and (PBoAy) consecutively at the edit points, each address counter 45.55 is preset so that the edit points set as described above coincide. .

Here, the cross-fade control circuit 63 is controlled by the control unit 14 to specify the cross-fade time (TI) in correspondence with the frequency division ratio (1/N) of each of the programmable frequency dividers 44 and 54. Data (Δ・N) is given, and each control coefficient data (α), (α
-1) to each multiplier 61 and 62 for cross-fade processing every 1/(N-fs).
It is controlled by 4.

Then, the frequency division ratio (1/N) of the programmable frequency divider 44.54 is set to 1, and a predetermined sampling frequency (f,
), each reproduced PCM signal (P
In the normal read mode with N=1 in which data near the edit point of Bov*) and (PBaar) is read out, the fader time changes in step units specified by Δ for each sampling clock FS as shown in FIG. The cross-fade control circuit 63 supplies each control coefficient data (α) and (α-1) of Tx to the multipliers 61 and 62 for the cross-fade processing. Also, N22
, and each reproduced PCM signal (PBDVR), (PB++) near the editing point is output from each memory 41.51 with a clock having a frequency of 1/N of the sampling frequency (r3).
In the low-speed read mode of N22 in which the data (At) is read out at low speed, the sampling frequency (f,
) of l/H frequency (T
Each ff of x'(Tx' = N-Tx)
The cross-fade control circuit 63 supplies the 1l'a coefficient data (α゛) and (α-1゛) to each of the multipliers 61 and 62 for the cross-fade processing. In addition,
FIG. 5 shows each control coefficient data (α') and (α-1'') when N=2 and a readout speed of 172 in the normal readout mode.

In the editing device of this embodiment, in the rehearsal mode, each of the programmable frequency dividers 44, 54
The frequency division ratio of is set to 1/H, and the read address data formed by each of the address counters 45.55 above based on the 1/H frequency divided output of the sampling clock FS of f is set. When reading out the data of each reproduced PCM signal (PBov,l), (PBDAT) near the above editing point with time expansion t, and performing memory rehearsal at an arbitrary speed as shown in B in Fig. 3, The above fader time is Tll'(TX' = N-Tl+
) are given to each multiplier 61 and 62 for the cross-fade processing, and the cross-fade time (
Tx') is subjected to cross-fade processing.

In addition, in the low-speed read mode, interpolation processing for forming interpolated data corresponding to a predetermined sampling frequency (r,) for data read out every clock with a frequency of 1/N-f is performed in each memory 41. .51
and each interpolation circuit 50.6 provided between each multiplier 61.62.
Performed at 0.

In this way, you can perform memory rehearsal at any speed and set the crossfade time (
By applying the cross-fade processing of TK'), the situation of cross-fade processing of the PCM signal at the edit point can be accurately recognized audibly, and the "fH concentration point can be accurately determined even for fast-touch piano pieces. You can perform editing work efficiently and reliably.

Furthermore, in the editing device of this embodiment, the display section 1
5, as shown in FIG. 6, first and second bar graph display areas AR, each having a length corresponding to the storage capacity of the first and second memories 41 and 51 of the editing processing section 4; ,A
R, are arranged in parallel, and the display is controlled as follows by the control section 14 according to the access state of each of the memories 41 and 51.

For example, in the assemble edit mode, by setting the above-mentioned edit point (Pat), the playback PCM signal (
When data near the editing point (pot) of PBov++) is written to the first memory 41, as shown in FIG.
A marker (gate 1) is displayed based on the marker (M. 1), and an address area of valid data and an invalid address area bounded by the address data (ADRo+) indicating the position of the marker (M. 1), that is, the edit point (Pol) are displayed. The address area of the data is displayed in the first bar graph display area AR so that it can be visually identified. Similarly, edit point (P02)
By setting , the reproduced PCM signal (PBwaA4) near the editing point (po2) is transferred to the second memory 51.
, the marker (M.2) is displayed based on the address data (ADRoz) indicating the edit point (Pa), and the position of the marker (M.2), that is, the edit point (poz) is displayed. Address data (ADRoz
) are displayed in the second bar graph display area AR so that the valid data address area and the invalid data address area are visually distinguishable. Each marker above (M
a+), (M.2) and the display state of each bar graph display area AR, AR2 are determined by each edit point (Pat),
(Pat) changes as shown by the broken line in FIG. 7 due to the correction process. In the rehearsal mode or edit output mode, the access status of the address area of each valid data in each of the memories 41, 51 is displayed as a bar graph over time as shown by arrows in FIG.

In addition, in the case of insert editing mode, by setting the above-mentioned editing start point (Pat), data near the above-mentioned editing start point (P s + ) of the reproduced PCM signal (PBDVI) is stored in the first memory 41. , and the editing end point (Py+) is set, as shown in FIG.
) and each address data (
ADRs+), (ADRi+) for each marker (
Ms+) and (ME+) are displayed, as well as address data (ADRs+) indicating the positions of the markers (Ms+) and (M!,), that is, the editing start point (P s I) and the editing end point (PEI). ), (^DRt+) as a boundary so that the address area for valid data and the address area for invalid data can be visually identified.

will be displayed. Similarly, by setting the editing start point (pst) described above, the playback PCM signal (PBoAt)
The data near the editing start point (Psz) is written to the second memory 51, and the editing end point (PEg) is set, so that the editing start point (Psz) and the editing end point ( The markers (Msz) and (MB) are displayed based on the address data (ADRsz) and (8DR1z) indicating PE, and the positions of the markers CMsz) and (Mix), that is, the editing start point ( ps□) and editing end point CPit)
Each address data (^DRsz), (ADR
The address area for valid data and the address area for invalid data with the boundary at tz) are displayed in the second bar graph display area AR so that they can be visually identified. In addition, each of the above markers (Ms+), (M!+), (Msz), (Mt
z) position and each bar graph display area A R+ ,
The bar graph display status of A R2 is each edit point (P□),
(PEI), (hz), (hz) are moved by correction processing. In the rehearsal mode or edit output mode, the access state of the address area of each valid data in each of the memories 41, 51 is displayed as a bar graph over time as shown by arrows in FIG.

In addition, as shown in FIGS. 6 to 8 above,
The display states of the display areas ARA and ARM arranged on the left side of the bar graph display areas AR, , AR are controlled by the control unit 14, and the tape running position of the DVR 1 and DAT 2 is set at 41° in each of the memories. Each PCM signal (PBov*) written in or near the editing point written in 51
, (PBoAt) is approached by blinking.

In addition, each of the above bar graph display areas A R+, A R
Each marker (m3+), (m
□).

(msz) and (mix) are each of the above-mentioned edited fish (Pot
), (Pot), (Ps+).

(Ptt), (P32), (Pe2) setting limits, each of the above PCM signals (PBnv++)
, (PBDAT) according to the type of recording/reproducing device, crossfader constant, etc. 4, the display is automatically controlled.

Furthermore, when the rehearsal mode or edit output mode is set in the insert W collection mode, the control unit 14 reproduces the reproduced PCM signal (PB+v*) near the editing point written in each of the memories 41 and 51.

(PBIIAT) data editing starting point (Ps+),
(Psz) and each editing end point (Ptt), (Ptz
) coincide with each other (t s) and (t
i) Preset each address counter 45.55 so that the reproduced PCM signal (PB
Control is performed to read data of DVII) and (PBoat) from each of the memories 41 and 51. Further, the fader control circuit 63 controls the editing start point (P s + ) of the data of the reproduced PCM signal (PBov*) near the editing point.
and each address data (A
By giving DRs+) and (ADH□) from the control unit 14 to each data comparator 47.48, the timings (ts), ( tt), each of the above data comparators 47
．． Fader control is performed in accordance with the timing pulse output from 48, and the insert editing output as shown in FIG. 9 is output from the data adder 65. Note that the fader times (TXS) and (Txi) are
4 can be arbitrarily set using the step data (Δ) given to the fader control circuit 63. Further, the data of the reproduced PCM signal (PBIIAT) near the editing point read out from the second memory 51 is supplied to a multiplier 68 for fader processing via the multiplier 62 for cross-fade processing, which has a fader coefficient. Spot erase processing can also be performed by giving "0".

In the editing device of this embodiment, each playback PCM near the editing point
The data of the signals (PBD□) and (PBIIAT) are written to each of the memories 41.51 and 41.5.
Insert editing is performed by setting the editing start point (Ps+) and editing end point (Ptt) within the storage capacity of 1, so it is possible to insert edit up to 1 word of data, and it is possible to edit notes such as fast-touch piano songs. It is possible to perform insert editing in a short period of time, such as exchanging files, extremely efficiently.

H Effects of the Invention In the PCM signal editing device according to the present invention, the data of each PCM signal near the editing point written in each memory is written into the corresponding memory, and the data of each PCM signal near the editing point is read from the memory. is read out with the edit points aligned, and cross-fade processing is performed at the edit start and end points, so when performing short insert edits such as replacing notes in fast-touch piano pieces, the playback side and The situation from the editing start point to the editing end point in the insert I collection can be checked in memory rehearsal without requiring synchronized operation of the recording side equipment, making it possible to efficiently and reliably create the insert W collection in a short time. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a PCM signal editing device according to the present invention, FIG. 2 is a block diagram showing the configuration of an editing processing section constituting the editing device, and FIG. 3 shows normal read mode and FIG. 4 is a schematic diagram showing the contents of each control coefficient data provided by the crossfader control section in the normal read mode. FIG. 5 is a schematic diagram showing the status of each memory rehearsal in the low speed read mode. FIG. 6 is a schematic diagram showing the contents of each control coefficient data provided by the fader control section, FIG. 6 is a schematic diagram showing the display area of the display section constituting the editing device, and FIG. 7 is a schematic diagram showing the display area of the display section in the assemble editing mode. FIG. 8 is a schematic diagram showing an example of the display content of the display section in the insert W collection mode; FIG. 9 is a schematic diagram showing the editing output in the insert editing mode. .

Claims (1)

[Claims] The first PCM signal reproduced from the first recording medium is
P to be recorded on the second recording medium on which the PCM signal of
In the CM signal editing device, a first memory for storing data near an editing point of a first PCM signal reproduced from the first recording medium; a second memory for storing data near the edit point of the PCM signal; and a second memory for storing data near the edit point of the PCM signal;
a write control means for controlling writing of CM signal data into the corresponding memory; and each PCM near the edit point written in each of the above memories.
a readout control means for controlling the reading of signal data in a state where the editing points match; and each PCM near the editing point written in each of the memories mentioned above.
An editing device for a PCM signal, comprising a cross-fade control means for controlling the operation of the cross-fade processing means at an editing start point and an editing end point for signal data.