JPS641867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM signal processing device suitable for use in, for example, a PCM signal electronic editing device.

An embodiment of the present invention will be described below. As shown in FIG. 1, electronic editing is performed by two helical scan type VTRs 1 and 2, a PCM adapter 3, an editing device 4 to which the present invention is applied, and a monitor speaker 5 connected to the PCM adapter 3. It is done. As an example of electronic editing, suppose that a master tape 6 on which a plurality of programs as shown in FIG. 2A are recorded is played back on the VTR 1, and an edited tape 7 as shown in FIG. think. As an outline of this procedure, first, program #1 is recorded to a slightly longer length on the editing tape 7 by the VTR 2, as shown in FIG. 2B. next,
An edit point FO (fade-out point) is determined for the edit tape 7, and then an edit point (fade-in point) FI is determined for the master tape 6. and
The master tape 6 is played back by the VTR 1, the VTR 2 is put into a recording state at the editing point, the PCM signal that has been crossfade processed is recorded, and thereafter the PCM signal of the #2 program is recorded.

FIG. 3 shows the basic configuration of the PCM adapter 3 and the editing device 4, as well as the VTR 1,
The connection relationship with 2 is shown. Each of the VTRs 1 and 2 has video input ends VI ₁ , VI ₂ , video output ends VO ₁ , VO ₂ , and audio input ends AI ₁ , AI ₂ .
It has audio output terminals AO ₁ and AO ₂ , a remote terminal, and a synchronization input terminal. The remote terminal is connected to the remote terminal of the editing device 4,
The operations of the VTRs 1 and 2 can be controlled remotely by key operations on the editing device 4 or by control signals from the editing device 4. Further, a synchronization signal from the PCM adapter 3 is applied to the synchronization input terminal of the VTR 1. The VTR 1 plays back the master tape 6 and generates a PCM signal in the form of a video signal at the video output terminal VO ₁ . VTR2 has editing tape 7
Play and play already recorded PCM signals of
Generates a PCM signal to the video output terminal VO ₂ , and
Record the PCM signal from the video input terminal VI ₂ . Furthermore, the audio tracks of the master tape 6 and editing tape 7 are equipped with SMPTE time codes that can be played back.
The reproduced time code appears at the audio output terminals AO ₁ and AO ₂ of the VTRs 1 and 2, and the recorded time code is supplied from the audio input terminals AI ₁ and AI ₂ .

The PCM adapter 3 includes a first signal transmission path from an audio input terminal AI ₃ to video output terminals VO ₃₁ and VO ₃₂ including an A/D converter 8, a selector switch 9, an encoder 10, and a video amplifier 11, and a video input terminal. A synchronization separation circuit 12, a decoder 13, a changeover switch 14, from the terminal VI ₃ to the audio output terminal AO ₃ ,
and a second signal transmission path including a D/A converter 15. During editing, since it is processed as a digital signal, the A/D converter 8 is not used, and the data input from the data input terminal DI ₃₁ is sent via the changeover switch 9.
PCM data is supplied to the encoder 10, and PCM data from the decoder 13 is led to the data output terminal DO ₃₂ . Also, from the data input terminal DI ₃₂
PCM data is transferred to D/A via switch 14.
The audio signal is supplied to the converter 15, and the audio signal from this is supplied to the monitor speaker 5. encoder 1
0 performs interleaving and time axis compression processing, synchronization signal and error correction code addition processing, and decoder 13 performs deinterleaving and time axis expansion processing, and error detection and correction. Although FIG. 3 shows the signal path for only one channel, PCM modulation and PCM demodulation sections for two channels are provided for processing stereo audio signals.

The editing device 4 has two RAMs (random access memories) 16 and 17 and a control circuit 18. Time code generation and reading circuits 19 and 20 are provided in association with the control circuit 18, and generate a predetermined control signal by processing the absolute address according to the time code supplied from the time code input terminals TCI ₄₁ and TCI ₄₂ . A new time code is generated at time code output terminals TCO ₄₁ and TCO ₄₂ . From control circuit 18
A signal is generated to control the operation of VTRs 1 and 2,
The signal is applied to each of VTRs 1 and 2 from the remote terminal. RAM 16 and 17 by control circuit 18
writing and reading are controlled. Editing device 4
are the data input terminal DI ₄ connected to the data output terminal DO ₃₂ of the PCM adapter 3, and the data output terminal DO ₄₁ connected to the data input terminal DI ₃₁ of the PCM adapter 3.
and a data output terminal DO ₄₂ connected to the data input terminal DI ₃₂ of the PCM adapter 3. The PCM data taken out to the data output terminals DO ₄₁ and DO ₄₂ are transferred to the data selectors 21 and 22.
is selected. Furthermore, playback PCM of VTR1 and 2
A video input terminal to which the signal and the PCM signal from the video output terminal VO ₃₁ of the PCM adapter 3 are respectively supplied.
The editing device 4 has VI ₄₁ , VI ₄₂ , and VI ₄₀ , and any one of these video signals is selected by the video selector 23 and supplied to the video input terminal VI ₃ of the PCM adapter 3 .

Further, the PCM data from the data output terminal DO ₄₂ is supplied from the data input terminal DI ₃₂ to the D/A converter 15 and reproduced by the monitor speaker 5, whereas the PCM data is generated from the data output terminal DO ₄₁ and is A PCM signal appearing at the video output terminal VO ₃₂ via the input terminal DI ₃₁ and the encoder 10 is recorded by the VTR 2.

Delay time occurs in the encoder 10 and decoder 13 of the PCM adapter 3. In other words, a delay occurs when the encoder 10 adds an error correction code that performs interleaving, and the decoder 10
3, a delay occurs when deinterleaving is performed and error correction is performed. PCM adapter 3 like this
A delay time detection circuit 24 for measuring the inherent delay time of is provided in the editing device 4, and the detection result is supplied to the control circuit 18.

The signal flow in each editing process will be explained with reference to FIG.

First, VTR 1 plays master tape 6,
The reproduced PCM signal is supplied to the VTR 2 and monitored by the speaker 5, and the #1 program is recorded on the editing tape 7 by the VTR 2. The #1 program recorded on editing tape 7 is made slightly longer than needed.

Next, an edit point is determined. The editing point is
The fade-out point FO for the editing tape 7 is determined first. Therefore, the VTR 2 plays back the editing tape 7. [VTR2 terminal VO ₂ → terminal
VI ₄₂ → Video selector 23 → Terminal VO ₄₀ → Terminal VI ₃
→ Decoder 13 → Terminal DO ₃₂ → Terminal DI ₄ 〓 [Monitor path] → RAM 16] The reproduced sound can be monitored through the path, and PCM data is written in RAM 16. Then, for example, 3 seconds after a predetermined key switch is pressed near the fade-out point FO, the VTR 2 enters the pause state, and the RAM 16
±3 before and after the key switch is pressed.
Seconds' worth of PCM data is written, and then the RAM 16 changes to the read state.

PCM data is read from the RAM 16 in accordance with the rotational speed of a search dial (not shown) and supplied to the monitor path. The fade-out point FO is determined while listening to this reproduced sound, and a predetermined switch is pressed. This allows the fade out point FO
is stored in the register as an absolute address. This absolute address includes not only the time code but also the word address within one frame (for example, 1470 words).

In this example, the delay time is detected when determining the fade-out point FO. Although not shown, a digital signal for detection of a predetermined pattern is supplied to the detection circuit 2.
4, and this word is generated by a word generator provided in connection with data selector 21→terminal
DO ₄₁ → Terminal DI ₃₁ → Encoder 10 → Terminal VO ₃₁ →
The delay time is detected through the signal path of terminal VI ₄₀ → video selector 23 → terminal VO ₄₀ → terminal VI ₃ → decoder 13 → terminal DO ₃₂ → terminal DI ₄₁ → detection circuit 24].

The fade-in point FI is also determined by the fade-out point.
It is done in the same way as FO. _The master tape 6 _is played back by _the VTR ₁ , and the _RAM
PCM data is written to 16. The fade-in point can be set by operating the specified key switch.
PCM data near the FI is written to RAM16,
VTR1 enters a pause state. Next, by rotating the search dial, it was read from RAM16.
While listening to the PCM data playback sound, a fade-in point FI is determined, and the corresponding absolute address (including word address) is stored in a register.

While the search dial is being rotated to determine the fade-in point FI, PCM data near the fade-out point FO is written into the RAM 17.
After the editing tape 7 is rewound by a predetermined amount by the VTR 2, it is put into the playback state, and the PCM data from a predetermined amount, for example, 10 frames before the fade-out point FO to 6 frames after the FO stored in the register, is transferred to the [terminal VI ₄₂ →Video selector 23→Terminal VO ₄₀
→Terminal VI ₃ →Decoder 13 →Terminal DO ₃₂ →Terminal DI ₄
→RAM17] is also written to RAM17.

Once the editing point has been determined in the manner described above, an editing operation is then performed. Rehearsals are commonly performed to confirm whether the editing operations are performed as expected. The only difference between the editing operation and the rehearsal is that during the editing operation, the VTR 2 is switched from the playback state to the recording state, whereas during the rehearsal, the VTR 2 remains in the playback state.

Further, the control during editing operation is performed based on the absolute addresses corresponding to the husband and wife of the predetermined fade-out point FO and fade-in point FI. In this case, if these absolute addresses are used as is,
Because the position actually recorded on the editing tape 7 lags behind the predetermined position due to the delay occurring in the PCM adapter 3, it is necessary to correct this. For this purpose, the detection result of the delay time detection circuit 24 is used, and the absolute addresses of the fade-out point FO and the fade-in point FI are modified to be earlier by the number of words N corresponding to the detected delay time. Editing operations are performed based on this corrected address. On the other hand, the PCM data supplied to the monitor path does not need to be modified as described above.
It is sufficient to delay the PCM data supplied to the data input terminal DI ₃₁ by N words. The RAM 17 is also used for this delay.

The RAM 17 first stores PCM data #1 near the fade-out point FO, secondly delays PCM data #2 played from the master tape 6 to synchronize it with PCM data #1, and thirdly stores the PCM data #1 near the fade-out point FO. It has a function to delay PCM data and supply it to the monitor path.

Before moving on to the editing operation, the master tape 6 and editing tape 7 are moved back by a predetermined amount based on the corrected editing point address, and then at the same time
VTRs 1 and 2 start playback operation. In this case, the amount of return for the editing tape 7 is increased by one to several frames compared to the master tape 6. Therefore, it is played by each of VTRs 1 and 2.
Regarding the PCM data, PCM data #2 precedes PCM data #1 by one to several frames. Fade out point FO and fade in point
By comparing the address corresponding to the FI with the time code reproduced from the master tape 6 and editing tape 7, synchronization deviations excluding one to several frames are detected as the number of words n. At this time,
Program #1 being played back by VTR 2 is being monitored.

And 10 frames before the edit point,
[RAM17 → Data selector 21 → Terminal DO ₄₁ →
Terminal DI ₃₁ → Encoder 10 → Terminal VO ₃₂ → VTR2
Terminal VI ₂ ] is also connected to the editing tape 7 via the PCM
Data #1 is re-recorded. In this case, since the PCM data is supplied to the data input terminal DI ₃₁ earlier by N words corresponding to the delay time, continuity with the originally recorded PCM data is maintained. On the other hand, [RAM17 → data selector 2
2 → terminal DO ₄₂ → [monitor path]]
The reproduced sound delayed by N words can be monitored by RAM17. Furthermore, from 10 frames before the edit point
PCM data #2 reproduced by the VTR 1 is written to and read from the RAM 17, and by providing a delay of one to several frames and n words between writing and reading, PCM data #2 is converted into PCM data. It can be synchronized with #1. PCM data #1 and #2 read from the RAM 17 are supplied to a crossfader (not shown), but only PCM data #1 appears in the output up to the fade-out point FO and the fade-in point FI.

When the fade-out point FO and fade-in point FI are reached, the cross fader starts operating.
PCM data, which is a mixture of PCM data #1 whose level gradually decreases and PCM data #2 whose level gradually increases, is recorded on the editing tape 7 via the same path as described above, and the N word Delayed and fed to the monitor path. When the crossfade ends, only PCM data #2 appearing from the crossfade is recorded and monitored. PCM data #2 is recorded on the editing tape 7 for a slightly longer time than required, and the editing operation ends.

A more specific configuration of the above-mentioned delay time detection circuit 24 is shown in FIG. In FIG. 4, 25 indicates a frame signal generator, and when the delay time detection mode is entered, the control signal shown in FIG. 5A is supplied from the control circuit 18, and from the frame pulse of the frame period shown in FIG. 5B, As shown in FIG. 5C, the frame signal generator 25 generates a frame signal Sf which becomes "1" for three frames after the control signal is generated. The video selector 23 is controlled by this frame signal Sf, and is switched to a state in which the PCM signal appearing at the terminal VO ₃₁ of the PCM adapter 3 is selected and supplied to the terminal VI ₃ of the PCM adapter 3. Further, the frame signal Sf is supplied to the data generator 26, and as shown in FIG. 5D, the frame signal Sf is "0" in one frame of the "1" period and "1" in the remaining two frames. A detection digital signal Sg is generated and supplied to the AND gate 27. The detection digital signal Sg is
Data output terminal DO ₄₁ via data selector 21
guided by. The data selector 21 selects the detection digital signal Sg while the frame signal Sf is "1". A word of PCM data 1 is, for example, 32 bits, and the least significant bit thereof corresponds to the detection digital signal Sg. Furthermore,
The data input terminal DI ₄ is supplied with a digital signal appearing at the data output terminal DO ₃₂ of the PCM adapter 3, and this is applied to the "1" detection circuit. “1”
The detection operation of the detection circuit 28 is enabled only when the frame signal Sf is "1", and its detection output Sh is inverted by the inverter 29 and supplied to the AND gate 27. While the output of AND gate 27 is "1", counter 30 counts word clock pulses from 31.

_The detection digital signal Sg shown in _{FIG .}
→Terminal VI ₄₀ →Video selector 23 →Terminal VO ₄₁ →
Terminal VI ₃ → Decoder 13 → Terminal DO ₃₂ → Terminal DI ₄ ]
“1” detection circuit 28
As shown in FIG. 5E, the detection output Sh is delayed by the delay time T generated in the signal transmission path described above. Therefore, the output of the AND gate 27 becomes "1" during this delay time T, as shown in FIG. 5F, and the counter 30 counts word clock pulses only during this period. The counted value N words of the counter 30 corresponds to the delay time T, and is used to correct the address of the edit point as described above, and is also used to delay the PCM data for monitoring.

Note that the detection signal Sg may be one in which only a certain word is set to "1" and all others are set to "0".

As understood from the description of one embodiment above,
According to the present invention, in order to add an error detection or correction signal and perform error detection or correction processing,
It is possible to detect the delay time that occurs in the PCM signal processing device. The configuration of the error correction code is continuous
Reordering the PCM data array (interleaving)
There are various methods such as those that perform interleaving, and the length of delay time when performing interleaving is not constant depending on the method. Therefore, when performing electronic editing using two PCM recorders and a PCM adapter as in the above-mentioned embodiment, this PCM
Without knowing the adapter's inherent delay time, the desired editing operation cannot be performed. According to the present invention, it is effective to use when performing such electronic editing, and for example, it is effective to use when performing such electronic editing.
When re-recording the PCM signal, the recorded state can be exactly matched to the original one.

Also, when monitoring, the delay caused by the PCM adapter is
This causes a discrepancy between the current PCM data and the monitor playback sound. This results in inconvenience when controlling the recording (or playback) operation while listening to the monitor playback sound. According to the present invention, it is possible to avoid such inconveniences.

Furthermore, as in the above-mentioned embodiment, if the delay time is automatically detected while reading the PCM data stored in the RAM 16 and determining the edit point, the operation becomes very simple. There is a profit.

Note that the present invention is not limited to electronic editing, and may be applied to measuring the delay time of a PCM signal processing device.

[Brief explanation of drawings]

Figures 1 and 3 are block diagrams showing the interconnection of a VTR, a PCM adapter, and an editing device in an embodiment in which the present invention is applied to electronic editing of PCM signals, and Figure 2 is an explanation of the editing process. 4 is a block diagram of a delay time detection circuit in one embodiment of the present invention, and FIG. 5 is a time chart used for explaining the same. 1 and 2 are VTRs, 3 is a PCM adapter, 4 is an editing device, 5 is a monitor speaker, 6 is a master tape, 7 is an editing tape, 10 is an encoder, 13
2 is a decoder, and 24 is a delay time detection circuit.

Claims (1)

[Claims] 1. A first transmission line including an encoder that performs processing such as adding an error correction code to PCM data and outputs a PCM signal with a predetermined code configuration;
Processing such as error correction is performed on the PCM signal and the above
In a PCM signal editing device that is connected to an arbitrary PCM signal processing device having a second transmission path including a decoder that outputs PCM data, and edits the first PCM signal to connect the second PCM signal. , configured to be electrically connected to any of the above PCM signal processing devices, generates a predetermined pattern of detection digital signals and supplies them to the input terminal of the first transmission path of the connected PCM signal processing device; a detection signal generating means configured to
configured to be electrically connected to a PCM signal processing device, and supplied with the detection digital signal via the first transmission path and second transmission path of the connected PCM signal processing device; Delay time detection means configured to detect a delay time occurring between the first transmission path and the second transmission path of the PCM signal processing device connected using the detection digital signal;
and means for outputting the second PCM signal so that the delay time detected with respect to the time of the editing point is supplied to the input terminal of the first transmission path in advance. PCM signal editing device. 2. A first transmission path including an encoder that performs processing such as adding an error correction code to PCM data and outputs a PCM signal with a predetermined code configuration;
Processing such as error correction is performed on the PCM signal and the above
In a PCM signal editing device that is connected to an arbitrary PCM signal processing device having a second transmission path including a decoder that outputs PCM data, and edits the first PCM signal to connect the second PCM signal. , configured to be electrically connected to any of the above PCM signal processing devices, generates a predetermined pattern of detection digital signals and supplies them to the input terminal of the first transmission path of the connected PCM signal processing device; a detection signal generating means configured to
configured to be electrically connected to a PCM signal processing device, and supplied with the detection digital signal via the first transmission path and second transmission path of the connected PCM signal processing device; Delay time detection means configured to detect a delay time occurring between the first transmission path and the second transmission path of the PCM signal processing device connected using the detection digital signal;
means for outputting the second PCM signal so that it is supplied to the input terminal of the first transmission line; and outputting the second PCM signal so that it is supplied to the input terminal of the first transmission line. 1. A PCM signal editing device comprising means for delaying and outputting the delay time detected for a PCM signal to the outside.