JPS62172804A - Buffer amplifying circuit - Google Patents

Abstract

PURPOSE:To realize a characteristic of a low output impedance extending over a wide frequency by a small number of transistors, by connecting an output terminal and the second input of an operational amplifier, and connecting a bias circuit between the output terminal and the second power source. CONSTITUTION:A base of a transistor TR Q1 is connected to an output of an operational amplifier 1 whose one input is connected to an input terminal IN, connected to an output terminal OUT having a load capacity C through its emitter resistance R1, and its collector is connected to a base of a TR Q2, and also, connected to the first power source VCC through a resistance R2. An emitter of the TR Q2 is connected to the power source VCC through a resistance R3, and its collector is connected to the terminal OUT. The terminal OUT and the other input of the amplifier 1 are connected, and also, a bias circuit 4 is connected between the terminal OUT and the second power source VEE. In this way, by selecting suitably a resistance value of the resistances R1, R2 and R3, a low output impedance can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a buffer amplifier circuit such as a fundamental voltage generator, and more particularly to a small and economical buffer amplifier circuit with a wide band and low output impedance.

[Background of the invention]

In order to stabilize the unipolar and bipolar basic voltage sources of conventional measuring instruments so that the output voltage does not change even when the load current fluctuates rapidly, low output impedance such as an operational amplifier with negative feedback is used. A buffer amplifier circuit is used. In particular, when the load current is turned on and off at high speed by FETs, transistors, etc., it cannot be followed by the operational amplifier alone, and the output impedance becomes high in the high frequency region. This causes fluctuations in the output voltage, so a circuit with a higher frequency band and lower impedance is required, and a small buffer amplifier circuit with a small number of components is required.

FIG. 5 is a block diagram showing an example of a conventional buffer amplifier circuit of this type. In FIG. 5, this buffer amplifier circuit is composed of an operational amplifier 1 with negative feedback, a high-speed amplifier 2, an output amplifier 3, and a load capacitance C, whose output impedance is determined by the load capacitance C at high frequencies. , is reduced at low frequencies by the negative feedback of the high speed amplifier 2, and the operational amplifier 1 is provided to realize a highly accurate voltage. In this way, it is generally difficult to stably apply negative feedback in a capacitive load circuit because a second pole occurs in the negative feedback loop, but this can be solved by providing a high-speed amplifier 2 and providing a negative feedback called minor feedback. This problem was solved by introducing a method of applying negative feedback to a large amount and at high frequencies, thereby realizing a circuit with low output impedance over a wide range of frequencies.

FIG. 6 is a bipolar circuit diagram showing an example of a conventional buffer amplifier circuit. In diagram wJ6, transistor Q*-
Qa, Q? constitutes the high-speed amplifier 2 in FIG. The number of transistors used in the circuit is six.

FIG. 7 is a unipolar circuit diagram showing another example of the conventional buffer amplifier circuit. In Figure 7, transistor Q*
mQn constitutes the output amplifier 3 in FIG. This buffer amplifier circuit is a circuit modified from the circuit shown in Figure 5 so that it can output only a flowing current as an example of a unipolar circuit. The number of transistors used in this circuit is five.

However, conventional buffer amplifier circuits have limitations when it is desired to reduce the number of transistors used to further downsize the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer amplifier circuit that can be constructed in a small size with a smaller number of transistors and has a low output impedance over a wide range of frequencies.

[Summary of the invention]

The present invention connects the base of the first transistor to the output of the operational amplifier whose first input is connected to the input terminal, connects the emitter to the output terminal via the first resistor, and connects the collector to the output terminal of g2. connected to the base of the transistor and the second
The emitter of the second transistor is connected to the first power supply through a third resistor, the collector thereof is connected to the output terminal, and the output terminal and the operational amplifier are connected to the first power supply through a resistor. This buffer amplifier circuit has the functions of an output amplifier and a high-speed amplifier by connecting the second input and connecting a bias circuit between the output terminal and the second power supply. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

The first factor is a basic circuit diagram showing an embodiment of the buffer amplifier circuit according to the present invention. In FIG. 1, this buffer amplifier circuit connects the base of an agl transistor Q1 to the output of an operational amplifier (op-amp) 1 whose one input (non-inverting input) is connected to an input terminal IN, and connects its emitter to a first Output terminal OU with load capacitance C via resistor R8 of
T, its collector is connected to the base of the transistor wJ2, and connected to the power supply (positive power supply) Vcc of Ml via the second resistor, and the emitter of the second transistor Q is connected to the base of the transistor wJ2. It is connected to the first power supply FCC via a resistor R8, its collector is connected to the output terminal OUT, the output terminal OUT is connected to the other input (inverting input) of the operational amplifier (op-amp) 1, and the output terminal OUT is connected to the first power supply FCC through the resistor R8. A bias circuit 4 is connected between the power source Vxx and the second power source (negative power source) Vxx. Note that the transistor ('1.9!) constitutes an amplifier that simultaneously realizes the functions of the conventional output amplifier 2 (FIG. 5) and the high-speed amplifier 3.

With this configuration, the output signal of the operational amplifier 1 based on the input signal of the input terminal IN is voltage amplified by the transistor Q1,
Transistor Q! Since the current is amplified by , a large output current is output to the output terminal OUT. Furthermore, since the transistors Q* and Q* form a cascade-connected emitter-grounded amplifier, it has high speed and high gain, and since negative feedback is applied from the output terminal OUT, it functions as a conventional high-speed amplifier.

Next, the output impedance of this circuit will be explained.

The voltage gain obtained by transistors Q1-Qt, that is, the open loop gain of the amplifier, is expressed by the following formula (%) where A is the voltage amplification factor of transistor Q1, G is the mutual conductance of voltage-current conversion of transistor Q,
Xc is the impedance of the load capacitor C connected to the output terminal OUT. - The output impedance Z0 of this amplifier becomes the impedance xc of the load capacitance C when negative feedback is not applied, so when negative feedback of the amount of negative feedback (open loop gain) A is applied, it becomes as follows.

Z0=X/A=X(/(Ay XGXXc)=1/(
AFXG) Here, the resistance value of resistor R1y't t R3 is the same <Rt
When used as ybird*R3, it can be expressed as follows.

Ar=horse/RI G = 17R3 therefore, Z0=RIXR3/R.

If the resistance value R1*R1 is selected appropriately, a low output impedance can be achieved.

Further, the limit of the operating frequency of this amplifier is expressed by the following equation.

A=AyxGxXc≧1 That is, Xc≧l/ (JF X a ) = xs X R8/
xt Therefore, the impedance xc of the load capacitance C is
At frequencies below the frequency at which R3/R1 decreases, the output impedance Z0 becomes Zo=A ×Rs due to the effect of negative feedback.
/"v. At frequencies above this frequency, due to the action of the load capacitance C, Z.=xc≦R, xRv/horse. In this way, a low output impedance is achieved over a wide band.

In this way, according to this embodiment, the functions of an output amplifier and a high-speed amplifier, which were conventionally constructed using separate transistors, can be simultaneously realized using the above-mentioned amplifier with a smaller number of transistors. Further, an operational amplifier 1 is connected to the above-mentioned low output impedance amplifier to achieve high voltage accuracy, and the negative feedback provided by the operational amplifier 1 further reduces the output impedance at a low south wave number.

FIG. 2 is a unipolar circuit diagram showing another embodiment of the buffer amplifier circuit according to the present invention. In FIG. 2, this buffer amplifier circuit includes an operational amplifier 1, a transistor Q*,
In addition to using the constant current source using the transistor Q as the bias circuit 4 in FIG. A resistor is inserted between the output and the base of the first transistor Q, its base is connected to the collector of the transistor Q4, and the emitter of the transistor Q4 is connected to the \output terminal O.
Connect to UT and connect its base to the output terminal O through the resistor.
Connected to UT, these transistors Q, and resistors R4, R
6 constitutes and adds a current limiting circuit for output short circuit protection. In addition, in order to suppress the increase in impedance due to self-resonance at high frequencies as the load capacitance C in Figure 1, a load capacitor (capacitor) with a different capacitance of "l'1m" is used.
Connect multiple 'l's in parallel.

Next, FIG. 3 is a side view of the frequency characteristics of the output impedance shown in FIG. 2. Figure 3 shows the resistance R+ in Figure 2 = i0Ω,
The characteristics are shown when H = 1fΩ and R5 = IOΩ. In this case, the output impedance Z0 = R, XR, /R, is the transistor Ql.

Taking into consideration 6.5Ω in the impedance r1 of the emitter of Q, the following is obtained.

Zo = (R1+re) (Rs +r,)/4=
(10+6.5) (10+6.5)/100
0 = 272 (sO) On the other hand, the maximum value of the output impedance Z0 in Fig. 3 is 300 ohms, which is almost the same as the above theoretical value.
Moreover, low output impedance values are obtained over a wide range of frequencies from direct current to 100&ffz or more. In addition, in this characteristic curve, the dip in the output impedance Z0 at frequencies above IMHz is the load capacitance (capacitor) 'I
This is due to the self-resonance of y Cm v Cm. By connecting a plurality of capacitors with different capacities in parallel as in this circuit, it is possible to suppress the increase in output impedance due to the self-resonance of the load capacitance C at high frequencies.

In this way, according to this embodiment, low output impedance can be achieved in a wide frequency band, and its characteristics are equivalent to those of the conventional diagram @7, but the number of transistors used is 5 or 1 compared to the conventional one. On the other hand, the number can be reduced to three, thereby achieving miniaturization and cost reduction of the circuit. Note that the unipolar circuit in the non-embodiment is a case where the output current flows out, but by replacing the NPN polarity of the transistor shown in FIG. You can also do it.

FIG. 4 is a bipolar circuit diagram showing still another embodiment of the buffer amplifier circuit according to the present invention.

This buffer amplifier circuit consists of the unipolar outflow type circuit shown in FIG. 2 and the NPN polarity of the transistors Q+-Qt.
A bipolar circuit is constructed by combining unipolar flow-in type circuits constructed by transistors Q1m and Qtl, in which the transistors Q1m and Qtl are replaced with PNPs, and a resistor Rtse ``n s 'st.According to this embodiment, a bipolar circuit is constructed by combining A low output impedance characteristic over a wide frequency range equivalent to that shown in the figure can be obtained, but the number of convenient transistors is 5 instead of the conventional 6 (
The number of constant current source transistors is reduced to one.

According to the embodiments described above, low output impedance characteristics in a wide frequency band can be realized with a smaller number of transistors, and the following effects can be obtained. In other words, while the conventional circuit required a capacitor of, for example, 1 μF as the load capacitance, the circuit of this embodiment required a capacitor of, for example, θμF.
Equivalent characteristics were obtained with the capacitors. This is transistor Q1. This is because negative feedback is applied due to the inclusion of an emitter resistance in Q*, and the frequency characteristics of each transistor are improved, which improves the limit frequency of the amplifier.

Since the load capacitance C can be made small in this way, the charging/discharging current is reduced and the frequency characteristics as a buffer are also improved.

Furthermore, in the circuit of this embodiment, the output impedance Z0 does not depend on the load capacitance C over a wide frequency range, and Z0=R1
It has the characteristic of being determined as xR1/4, so that an inexpensive capacitor can be used as the load capacitance C, and at the same time, it can also be used as a general buffer circuit for driving a capacitive load. It is also possible to add a resistor to the operational amplifier to provide gain to the circuit.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a buffer amplifier circuit that can achieve a low output impedance characteristic over a wide range of frequencies with a small number of transistors and can be made smaller and lower in price.

[Brief explanation of drawings]

FIG. 1 is a basic circuit diagram showing an embodiment of a buffer amplifier circuit according to the present invention, FIG. 2 is a unipolar circuit diagram showing another embodiment according to the present invention, and FIG. 3 is a characteristic side view of FIG. 2. , FIG. 4 is a bipolar circuit diagram showing roughly another embodiment of the invention;
FIG. 5 is a block diagram showing an example of a conventional buffer amplifier circuit, FIG. 6 is a bipolar circuit diagram of the conventional buffer amplifier circuit, and FIG. 7 is a unipolar circuit diagram of the conventional buffer amplifier circuit. 1... operational amplifier, 4... bias circuit Q
+ , ('t...first and second transistors. Qs y ('4t Qu v Q!I...transistors. RI y bird-Rs-R, -R, -Rs□#'!l e
Rss...Resistance. ' * 'l # '! e'l...Load capacity. IN...Input terminal, OUT...Output terminal. Vcc, vxx'...Power supply. ,,-. Representative Patent Attorney Katsoo Ogawa Figure 1 Pig. 3rd frequency 11 Patent Applicant 2+ Name ・51 1 Shareg) G) Day of Amplifier Circuit 117
Subject of person's amendment Detailed explanation of the invention in the specification and Figure 4 of the drawings

Claims (1)

[Claims] 1. Connect the first input of an operational amplifier to the input terminal, connect the base of the first transistor to the output of the operational amplifier, and connect the emitter of the first transistor to the first resistor. connecting the collector of the first transistor to the base of a second transistor, and connecting the collector of the first transistor to a first power supply through a second resistor; The emitter of the second transistor is connected to the first power supply via a third resistor, the collector of the second transistor is connected to the output terminal, and the output terminal and the second transistor of the operational amplifier are connected to each other. Connect the input of the output terminal and the second
A buffer amplifier circuit consisting of a bias circuit connected between the power supplies. 2. In the buffer amplifier circuit according to claim 1, the first and second transistors are respectively NPN transistors or PNP transistors to form a unipolar buffer amplifier circuit with an output current flowing out or flowing in. , a bipolar buffer amplifier circuit that combines both buffer amplifier circuits. 3. The buffer amplifier circuit according to claim 2, wherein the bias circuit is a constant current source circuit. 4. The buffer amplifier circuit according to claim 1, 2, or 3, wherein a current limiting circuit made of a transistor is connected between the base of the first transistor and the output terminal. 5. The buffer amplifier circuit according to claim 1, claim 2, claim 3, or claim 4, wherein a plurality of load capacitors having different capacitance values are connected to the output terminal.