JPH02119472A - Video camera - Google Patents

Abstract

PURPOSE:To easily realize the strobe reproduction function due to multiple exposure by applying multiple exposure to an image pickup element in the 1st field period and operating a vertical transfer register in the 2nd field period so as to transfer the signal subject to multiple exposure. CONSTITUTION:An electronic shutter is operated intermittently in the 1st field and the operation of the vertical transfer register 3 is stopped during the period. Thus, the electronic shutter is switched intermittently for plural number of times during one field and since the pattern at that time is synthesized by a vertical transfer register 5, multiple exposure is attained. The vertical register 3 is operated in the 2nd field and the signal subject to multiple exposure is transferred. The strobe reproduction by multiple exposure is realized by applying the control as above. Thus, the strobe photographing by multiple exposure is implemented simply with a desired setting value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video camera, and particularly to a strobe playback function using multiple exposure of the video camera.

[Summary of the invention]

The present invention provides a video camera in which an image sensor is subjected to multiple exposures in a first field period, and signals resulting from the multiple exposures are controlled to be combined on a vertical transfer register,
In the second field period, the vertical transfer register is operated to transfer signals resulting from multiple exposure, thereby easily realizing the strobe playback function of the video camera using multiple exposure.

[Conventional technology]

Strobe photography using multiple exposures is used when it is desired to observe changes in the state of an object that is moving at high speed. Such multiple exposure strobe photography has conventionally been performed using a still camera.

There is a desire to realize strobe photography using multiple exposures using a video camera. In this case, as shown in FIG. 9, a rotatable slit plate 102 having a slit 103 is arranged in front of the CCD image sensor 101,
This slit plate 102 is rotated, and the subject image obtained intermittently through the slit 103 of the slit plate 102 is
The image is captured by the OD image sensor 101, and the sample and hold circuit 1
It is conceivable that the image pickup outputs of the CCD image pickup device 101 obtained from 04 are added by the memory 105 and the addition circuit 106.

[Problems to be Solved by the Invention] However, when the slit plate 102 having the slits 103 is disposed in front of the CCD image sensor 101 as described above, the problem arises that the camera becomes larger and the cost increases. In addition, when intermittent exposure is performed by rotating the slit plate 102 in this way, the slit 9) Fi1020
It is difficult to set the rotation speed to a predetermined speed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a video camera that can produce strobe shadows by multiple exposure at desired setting values without increasing the size or cost by using an electronic shutter.

[Means to solve the problem]

In the first field period, the image sensor is subjected to multiple exposures, and the signals resulting from the multiple exposures are controlled to be synthesized on the vertical transfer register of the image sensor. This is a video camera that operates the vertical transfer register of the device to control the transfer of multiple exposure signals.

[Effect]

As the CCD image sensor 1, one is used which is an interline transfer type and has a vertical overflow drain structure in which an overflow drain is provided in the depth direction of the chip. Such a CCD 1 image element 1 can release an electronic shutter at high speed. In the first field, the electronic shutter is operated intermittently multiple times. During this period, the operation of the vertical transfer register 3 is stopped. In this way, the electronic shutter is intermittently activated a plurality of times during one field, and the images at that time are combined in the vertical transfer register 5, making multiple exposure possible.

In the second field, vertical transfer register 3 is operated,
Multiple exposed signals are transferred. By performing such control, strobe playback using multiple exposures can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In one embodiment of the present invention, the CCD image sensor 1 is of an interline transfer type and has a vertical overflow drain structure in which an overflow drain is provided in the depth direction of the chip.

Interline transfer one type 〇〇CD image sensor 1
As shown in FIG. 2, the sensor 2 is arranged in a matrix, the vertical transfer register 3 is arranged for each vertical line of the sensor 2, and the horizontal transfer register 3 is arranged at the end of the vertical register 3. It consists of a transfer register 4. An output terminal 5 is derived from the horizontal transfer register 4.

As shown in FIG. 1, from the CCD image sensor 1, an input terminal 8 for a sensor gate pulse SGP, an input terminal 9 for a vertical transfer lock VCI+, and an input terminal 10 for a shutter pulse SHP are led out. The sensor gate pulse SGP from the input terminal 8 causes the charge of the sensor 2 to be transferred to the vertical transfer register 3. Then, charges are transmitted through the vertical transfer register 3 by the vertical transfer lock VCX from the input terminal 9. Further, the timing of accumulating and discharging charges in the sensor 2 is controlled by the shutter pulse SHP from the input terminal 10.

In the above example, in order to simplify the explanation, the sensor gate pulse SGP and vertical transfer lock (2) are used. CC
Although the signals are input to the D image sensor 1 separately, in reality, the vertical transfer register 3 of the CCD image sensor 1 is driven in three values. That is, sensor gate pulse SGP
is superimposed on the vertical transfer lock VCK as shown in FIG. When the sensor gate pulse SGP is applied, t in FIG. As shown in (), the vertical transfer port (vcK) reaches the highest level (■1°). In such a state, the read output gate 5 (FIG. 4) located between the sensor 2 and the vertical transfer register 3 is collapsed.
The charge on sensor 2 is transferred to vertical transfer register 3.

Also, in the above example, vertical transfer lock ■. is shown as one phase, but in reality, the vertical transfer register 3 has, for example, four phases.
It is transferred using the phase clock.

CCD with vertical overflow drain structure shown in Figure 4
jlBy the DC bias applied to the CCD image sensor 1 substrate 7, the accumulation and draining of charges can be controlled. That is, when the DC bias applied to the N-type group vi, 7 is high, charges are swept out to the sensor 2. When this DC bias is low, charge on sensor 2 is accumulated. This N
A shutter pulse SHP is applied to the type substrate 7 from a terminal 10, and the bias of the N type substrate 7 is controlled by this shutter pulse SHP. Therefore, this shutter pulse SHP can control the accumulation and discharge of charges in the sensor 2.

2, in one embodiment of the present invention, the CCD image sensor 1 is of an interline transfer type and has a vertical overflow drain structure in which an overflow drain is provided in the depth direction of the chip. Such a CCD image sensor 1 has a sensor gate pulse S
The GP can control the timing of transferring the charge of the sensor 2 to the vertical transfer register 3, and the shutter pulse SHP can sweep away the charge of the sensor 2 at high speed. Therefore, such a CCD image sensor 1 can release an electronic shutter at high speed. Therefore, if such a CCD image sensor 1 is used, it is possible to multiple-expose the screen within one field.

That is, within one field period, the charge of the sensor 2 is transferred to the vertical transfer register 3 multiple times, and
Correspondingly, the accumulation and discharge of the charge in the sensor 2 is controlled, that is, the electronic shutter is operated intermittently multiple times within one field. During this time, the operation of the vertical transfer register 3 is stopped. In this way, the electronic shutter is intermittently activated a plurality of times during the 1 field, and the images at that time are combined in the vertical transfer register 5, making multiple exposure possible.

By the way, when a plurality of screens are combined on the vertical transfer register 3, only exposure is performed in the first field, and only transfer is performed in the second field. Therefore, in this case, as shown in FIG. 5, a video signal is recorded only on the track TRA of the first field, and no video signal is recorded on the track TRB of the second field. For this reason, flicker may occur on the playback screen.

However, when performing strobe playback using multiple exposure, a still playback mode or a slow playback mode is used.In a normal VTR, only the signal of the track TRA of the first field is used in the still playback mode or slow playback mode. ing. Therefore, even if no video signal is recorded on the track TRB of the second field, no problem arises.

FIG. 1 shows an embodiment of the present invention. 1st
In the figure, a terminal 11 is supplied with a field identification signal FLD for identifying whether the field is the first field or the second field. A vertical synchronization pulse VD is supplied to the terminal 12. A vertical transfer lock VCI11 is supplied to the terminal 13. A horizontal synchronizing pulse HD is supplied to the terminal 14. Terminal 15 has a shutter pulse S HP I
is supplied.

Field identification signal FLD from terminal 11 is supplied to field switching signal generation circuit 16.

Further, a vertical synchronizing pulse VD is supplied from the terminal 12 to the field switching signal generating circuit 16. Field identification signal FLD from terminal 11 is latched by vertical synchronizing pulse VD, and field switching signal generation circuit 16 outputs field switching signal SF. This field switching signal SF is, as shown in FIG. 6A,
For example, it is set to a low level during a period Ta of the first field, and set to a high level during a period T3 of the second field.

This field switching signal SF is supplied to one input terminal of the AND gate 17, and is inverted via the inverter 18, and is applied to the AND gate 19 and the AND gate 2.
is supplied to one input terminal of 3.

The vertical synchronizing pulse VD from the terminal 12 is sent to the period setting circuit 21.
is supplied to A horizontal synchronizing pulse HD is supplied from the terminal 14 to the period setting circuit 21 .

Vertical transfer lock VCIII from terminal 13 is supplied to the other input terminal of AND gate 17. The output of the AND gate 17 is connected to the CCD image sensor 1 via the inverter 27.
is supplied to terminal 9 of.

A period setting circuit 21 generates a shutter interval control signal ST for controlling the shutter interval.

This period setting circuit 21, for example, as shown in FIG.
It is constructed using a counter 31 that counts horizontal synchronization pulses HD.

That is, in FIG. 7, the clock input terminal GK of the counter 31 receives the horizontal synchronization pulse I(
D is supplied. The output of the fourth bit and the output of the fifth bit of the counter 31 are supplied to an AND gate 33.

The output of the AND gate 33 and the output of the 6th bit of the counter 31 are supplied to an AND gate 34. The output of the 6th bit of the counter 31 is supplied to the input terminal a of the switch 35, and the output of the 7th bit of the counter 31 is supplied to the input terminal of the switch 35. The output of the AND gate 33 is supplied to the input terminal a of the switch 36, and the AND gate 3
The output of switch 36 is supplied to the input terminal of switch 36. The output of the switch 36 is taken out from the output terminal 39 as a shutter interval control signal ST.

The output of switch 35 is supplied to one input terminal of OR gate 37. The other input terminal of the OR gate 37 is
A vertical synchronizing pulse VD is supplied from a terminal 38. The output of the OR gate 37 is the reset terminal R3T of the counter 31.
is supplied to

The switches 35 and 36 control the shutter interval control signal ST.
This is to switch the period of Switches 35 and 36
When the horizontal synchronization signal HD is switched to the a side, the horizontal synchronization signal HD becomes 2.
The shutter interval control signal ST becomes high level at the timing when 4 is counted, and the shutter interval control signal ST becomes low level at the timing when the horizontal synchronization signal HD is counted 32. Since one field has 262.5 lines, in this case, the electronic shutter will be released eight times in one field.

When the switches 35 and 36 are switched to the b side,
The shutter interval control signal ST becomes high level at the timing when the horizontal synchronization signal HD is counted 56, and the shutter interval control signal ST becomes low level at the timing when the horizontal synchronization signal HD is counted 64. In this case, the electronic shutter will be released four times in the l field.

In FIG. 1, a shutter interval control signal ST from a period setting circuit 21 is supplied to a sensor gate pulse generation circuit 22. The sensor gate pulse generation circuit 22 receives a shutter interval control signal S from the cycle setting circuit 21, for example.
It is triggered at the rising edge of T and sets a predetermined exposure time. The sensor gate pulse generation circuit 22 is composed of, for example, a monostable multipiper. The sensor gate pulse generation circuit 22 generates a CCD image sensor 1.
A sensor gate pulse SOP is formed. This sensor gate pulse SGP, /+(AND gate 19
is supplied to the other input terminal of The output of the AND gate 19 is supplied to the input terminal 8 of the surgate pulse on the CCDCD image sensor.

Also, the shutter interval control signal ST from the cycle setting circuit 21 is ANDed as a masking signal for vertical transfer lock.
It is supplied to the other input terminal of gate 23. The output of AND gate 23 is supplied to the other input terminal of OR gate 24. The output of the OR gate 24 is connected to the shutter pulse input terminal 10 of the CCD image sensor 1 via the inverter 25.
supplied to

As shown in FIG. 6A, in the first field period T^,
The field switching signal SF is at a low level. Therefore, during the period TA of the first field, the output of the AND gate 17 is always at a low level, and the input terminal 9 of the vertical transfer lock of the CCD image sensor 1 receives the vertical transfer lock (2). will no longer be supplied.

The cycle setting circuit 21 outputs a shutter interval control signal ST as shown in FIG. 6C. The sensor gate pulse generation circuit 22 generates this shutter interval control signal ST.
A sensor gate pulse SGP is formed at a predetermined timing with reference to SGP. In the first field period TA,
Since the field switching signal SF is at a low level, the output of the inverter 18 is at a high level. Therefore, in the first field period TA, the sensor gate pulse SGP from the sensor gate pulse generation circuit 22
, are passed through the AND gate 19.

As a result, the sensor gate pulse input terminal 8 has
At the timing shown in Figure 6, the sensor gate pulse S
GP is supplied.

Further, in the first field period TA, the period setting circuit 21
The shutter interval control signal ST (Fig. 6C) from AN
It is supplied to the OR gate 24 via the D gate 23. While the shutter interval control signal ST is at a high level, OR
The output of the gate 24 becomes high level, and the inverter 25
output becomes low level. Therefore, as shown in Figure 6, during the first field period T^, the shutter interval control signal ST is at a high level during the period T, and the shutter pulse SHP supplied to the shutter pulse input terminal 10 of the CCD image sensor 1 is at a low level. maintained at the level. During this time, charge is stored in the sensor 2. Then, during the period T2 during which the shutter pulse SHP is applied, the charge on the sensor 2 is swept away. The period T3 from when the shutter pulse SHP is stopped until the sensor gate pulse SGP appears is the accumulation time. At time t, when the sensor gate pulse SGP appears, the charge of the sensor 2 is transferred to the vertical transfer register 3. 1st field period TA
Now, as shown in FIG. 6B, since the vertical transfer lock v0 is stopped, the signals transferred to the vertical transfer register 3 at time t are synthesized on the vertical transfer register 3.

In the second field period TII, as shown in FIG. 6A, the field switching signal SF is at a high level. Therefore, in the second field, the vertical transfer lock V CKI from the terminal 13 is passed through the AND gate 17 and the inverter 27. Therefore, in the second field period Tll, the vertical transfer locks v, K are supplied to the vertical transfer lock input terminal 9 of the CCD image sensor 1, as shown in FIG. 6B.

Furthermore, in the second field period T, since the field switching signal SF is at a high level, the output of the inverter 18 is at a low level.

Therefore, the output of the AND gate 19 is always at a low level, and the sensor gate pulse SGP is not applied to the sensor gate pulse input terminal 8 of the CCD image sensor 1, as shown in FIG.

Furthermore, in the second field period T, the field switching signal SF is at a high level, so the output of the inverter 1 is at a low level, and the output of the AND gate 23 is always at a low level.

Therefore, the shutter pulse SHP from the terminal 15 is passed through the OR gate 24 and the inverter 25. Therefore, in the second field period T1, as shown in Figure 6, the CCD image sensor element shutter pulse input 4 elements 10
A shutter pulse SHP is always supplied to the shutter pulse SHP. Therefore, no charge is stored in the sensor 2.

In this way, in the first field, if the vertical transfer is locked and multiple exposure is performed, and in the second field, only transfer is performed, as shown in FIG. If the image is photographed with a VTR and reproduced as a still image or as a slow motion image, strobe reproduction using multiple exposures can be performed.

〔Effect of the invention〕

According to this invention, in the first field, the electronic shutter is operated intermittently a plurality of times, and during this period, the operation of the vertical transfer register 3 is stopped. In this way, the electronic shutter is intermittently activated a plurality of times during one field, and the images at that time are combined in the vertical transfer register 5, making multiple exposure possible. In the second field, the vertical register 3 is operated and this multiple exposure signal is transferred. By performing such control, strobe playback using multiple exposures can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a CCD image sensor in an embodiment of the invention, and FIG. 3 is an example of a CCD image sensor in an embodiment of the invention. FIG. 4 is a sectional view used to explain an example of a CCD tIl image element in an embodiment of the present invention, and FIG. 5 is a route diagram used to explain an embodiment of the present invention. FIG. 6 is a timing chart used to explain an embodiment of this invention, FIG. 7 is a block diagram of an example of a period setting circuit in an embodiment of this invention, and FIG. 8 is used to explain an embodiment of this invention. FIG. 9 is a block diagram used to explain the strobe function of a conventional video camera. Explanation of symbols included in the drawings 1: CCD image sensor, 8: Sensor gate pulse input terminal, 9: Vertical transfer lock input terminal. 10: Shutter pulse input terminal.

Claims (1)

[Claims] In a first field period, the image sensor is subjected to multiple exposures, and the signals resulting from the multiple exposures are controlled to be synthesized on a vertical transfer register of the image sensor, and in a second field period, The video camera is configured to control a vertical transfer register of the image sensor to transfer the multiple exposure signal.