JP2864505B2 - Recording and playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera, and more particularly, to a strobe reproducing function of a video camera by multiple exposure.

[Summary of the Invention]

According to the present invention, in a video camera, control is performed such that an image pickup element is subjected to multiple exposure in a first field period, and signals subjected to multiple exposure are synthesized on a vertical transfer register, and the vertical transfer register is controlled in a second field period. Is operated so as to transfer the signal subjected to the multiple exposure, so that the strobe reproducing function by the multiple exposure of the video camera can be easily realized.

[Conventional technology]

In order to observe a state change of an object moving at high speed, stroboscopic photographing by multiple exposure is performed. Such flash photography by multiple exposure has been conventionally performed using a still camera.

There is a demand for realizing such flash photography by multiple exposure with a video camera. In this case, as shown in FIG.
A rotatable slit plate 102 having a is provided, the slit plate 102 is rotated, a subject image obtained intermittently through the slit 103 of the slit plate 102 is captured by the CCD image sensor 101, and a sample hold circuit 104 It is conceivable that the image pickup output of the CCD image pickup element 101 obtained from the above is added by the memory 105 and the addition circuit 106.

[Problems to be solved by the invention]

However, when the slit plate 102 having the slit 103 is provided on the front surface of the CCD image sensor 101 as described above, there is a problem that the camera becomes large and the cost increases. Further, when the slit plate 102 is rotated to perform intermittent exposure, it is difficult to set the rotation speed of the slit plate 102 to a predetermined speed.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a video camera capable of performing flash photography by multiple exposure at a desired set value without increasing the size or increasing the cost by using an electronic shutter.

[Means for solving the problem]

According to the present invention, in the first field period, the image pickup device is subjected to multiple exposure, and the signals subjected to the multiple exposure are controlled to be synthesized on the vertical transfer register of the image pickup device. This is a video camera in which a vertical transfer register of an element is operated so as to transfer a signal subjected to multiple exposure.

[Action]

As the CCD image pickup device 1, a vertical overflow drain structure in which an overflow drain is provided in a depth direction of a chip by an interline transfer method is used. Such a CCD image sensor 1 can release an electronic shutter at high speed. In the first field,
The electronic shutter is operated intermittently a plurality of times. And
During this time, the operation of the vertical transfer register 3 is stopped. In this manner, the electronic shutter is released a plurality of times intermittently during one field, and the screen at that time is synthesized by the vertical transfer register 5, so that multiple exposure is possible. In the second field, the vertical transfer register 3 is operated, and a signal subjected to multiple exposure is transferred. By performing such control, strobe reproduction by multiple exposure can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In one embodiment of the present invention, a CCD image sensor 1 having a vertical overflow drain structure in which an overflow drain is provided in a depth direction of a chip by an interline transfer method is used.

Interline transfer type CCD image sensor 1
As shown in FIG. 2, sensors 2 arranged in a matrix, vertical transfer registers 3 arranged for every vertical line of the sensors 2, and horizontal And a transfer register 4. An output terminal 5 is derived from the horizontal transfer register 4.

As shown in FIG. 1, an input terminal 8 of a sensor gate pulse SGP and a vertical transfer clock V
An input terminal 9 for the _{CK and} an input terminal 10 for the shutter pulse SHP are derived. Sensor gate pulse SG from input terminal 8
By P, the electric charge of the sensor 2 is transferred to the vertical transfer register 3. The vertical transfer clock V from the input terminal 9
_The charges are transmitted through the vertical transfer register 3 by _CK . In addition, the timing of accumulating and discharging the electric charge of the sensor 2 is controlled by the shutter pulse SHP from the input terminal 10.

In the above example, in order to simplify the description, although each is separately input to the CCD image sensor 1 sensor gate pulse SGP and vertical transfer clock V _CK, in fact, vertical CCD image sensor 1 The transfer register 3 is driven by three values. That is, the sensor gate pulse SGP is superimposed on the vertical transfer clock _VCK as shown in FIG. When the sensor gate pulse SGP is given, the third
As shown by the t ₁₀ in FIG., The highest level v ₁₀ is the vertical transfer clock V _CK. In such a state, the read output gate 5 (FIG. 4) between the sensor 2 and the vertical transfer register 3 is broken, and the electric charge of the sensor 2 is moved to the vertical transfer register 3. Further, in the above example, the vertical transfer clock _VCK is shown in one phase, but actually, the vertical transfer register 3 is transferred by, for example, a four-phase clock.

CCD with vertical overflow drain structure shown in Fig. 4
The image pickup device 1 can control accumulation and discharge of electric charges by a DC bias applied to the N-type substrate 7. That is, N
When the DC bias applied to the mold substrate 7 is high, charges are swept out to the sensor 2. When the DC bias is low, the electric charge of the sensor 2 is accumulated. A shutter pulse SHP is given to the N-type substrate 7 from the terminal 10, and the bias of the N-type substrate 7 is controlled by the shutter pulse SHP. Therefore, the accumulation and discharge of the electric charge of the sensor 2 can be controlled by the shutter pulse SHP.

As described above, in one embodiment of the present invention, the CCD imaging device 1 having a vertical overflow drain structure in which an overflow drain is provided in a depth direction of a chip by an interline transfer method is used. In such a CCD image sensor 1, the timing of transferring the charge of the sensor 2 to the vertical transfer register 3 can be controlled by the sensor gate pulse SGP, and the shutter pulse SH
By P, the charge of the sensor 2 can be swept away at high speed. Therefore, such a CCD imaging device 1 can release the electronic shutter at high speed. For this reason, if such a CCD image sensor 1 is used, it is possible to perform multiple exposure on a screen within one field.

That is, within one field period, the sensor 2
Is transferred to the vertical transfer register 3 a plurality of times, and the accumulation and discharge of the charges of the sensor 2 are controlled correspondingly. That is, the electronic shutter is operated intermittently a plurality of times in one field. During this time, the operation of the vertical transfer register 3 is stopped. In this manner, the electronic shutter is released a plurality of times intermittently during one field, and the screen at that time is synthesized by the vertical transfer register 5, so that multiple exposure is possible.

If a plurality of screens are combined on the vertical transfer register 3, only exposure is performed in the first field, and only transfer is performed in the second field. Therefore, in this case, as shown in FIG. 5, a video signal is recorded only on the track TRA of the first field, and no video signal is recorded on the track TRB of the second field. For this reason, flicker may occur on the playback screen.

However, when performing strobe reproduction by multiple exposure, a still reproduction mode or a slow reproduction mode is used. In a normal VTR, in the still playback mode or the slow playback mode, only the signal of the track TRA of the first field is used. Therefore, there is no problem even if the video signal is not recorded on the track TRB of the second field.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, a terminal 11 is supplied with a field identification signal FLD for identifying a first field or a second field. The terminal 12 is supplied with a vertical synchronization pulse VD. The terminal 13 is supplied with the vertical transfer clock _VCK1 .
The terminal 14 is supplied with a horizontal synchronization pulse HD. The terminal 15, the shutter pulse SHP ₁ is supplied.

The field identification signal FLD from the terminal 11 is supplied to the field switching signal generation circuit 16. Also, a vertical synchronization pulse VD is supplied from a terminal 12 to a field switching signal generation circuit 16.
Supplied to The field identification signal FLD from the terminal 11 is latched by the vertical synchronization pulse VD, and the field switching signal generation circuit 16 outputs a field switching signal SF. As shown in FIG. 6A, for example, the field switching signal SF is at a low level during a first field period T _A and is at a high level during a second field period T _B.

The field switching signal SF is supplied to one input terminal of the AND gate 17 and inverted via the inverter 18 and supplied to one input terminal of the AND gate 19 and the AND gate 23.

The vertical synchronization pulse VD from the terminal 12 is supplied to the cycle setting circuit 21. Horizontal synchronization pulse HD from terminal 14 cycle setting circuit
Supplied to 21.

The vertical transfer clock _VCK1 from the terminal 13 is supplied to the other input terminal of the AND gate 17. The output of the AND gate 17 is supplied to the terminal 9 of the CCD 1 via the inverter 27.

In the cycle setting circuit 21, a shutter interval control signal ST for controlling the shutter interval is formed.

This cycle setting circuit 21, for example, as shown in FIG.
It is configured using a counter 31 that counts the horizontal synchronization pulse HD.

That is, in FIG. 7, the horizontal synchronization pulse HD from the terminal 32 is supplied to the clock input terminal CK of the counter 31. The output of the fourth bit and the output of the fifth bit of the counter 31 are supplied to the AND gate 33. The output of the AND gate 33 and the output of the sixth bit of the counter 31 are the AND gate 34
Supplied to The output of the sixth bit of the counter 31 is supplied to the input terminal a of the switch 35, and the output of the seventh bit of the counter 31 is supplied to the input terminal b of the switch 35. The output of the AND gate 33 is supplied to the input terminal a of the switch 36, and
The output of the gate 34 is supplied to the input terminal b of the switch 36.
The output of the switch 36 is extracted from the output terminal 39 as a shutter interval control signal ST.

The output of the switch 35 is supplied to one input terminal of the OR gate 37. A vertical synchronization pulse VD is supplied from a terminal 38 to the other input terminal of the OR gate 37. The output of the OR gate 37 is supplied to the reset terminal RST of the counter 31.

The switches 35 and 36 switch the cycle of the shutter interval control signal ST. When the switches 35 and 36 are switched to the a side, the shutter interval control signal ST goes high at the timing when the horizontal synchronization signal HD is counted 24, and the shutter interval control signal ST at the timing when the horizontal synchronization signal HD is counted 32. ST goes low. 1
Since the field is 262.5 lines, in this case 1
The electronic shutter will be released eight times in the field.

When the switches 35 and 36 are switched to the b side, the shutter interval control signal ST goes high at the timing when the horizontal synchronization signal HD is counted 56, and the horizontal synchronization signal HD
The shutter interval control signal ST becomes low level at the timing when 64 is counted. In this case, the electronic shutter is released four times in one field.

In FIG. 1, a shutter interval control signal ST from a cycle setting circuit 21 is supplied to a sensor gate pulse generation circuit 22. The sensor gate pulse generation circuit 22 is triggered by, for example, the rise of the shutter interval control signal ST from the cycle setting circuit 21 and sets a predetermined exposure time. The sensor gate pulse generation circuit 22 is composed of, for example, a monostable multivibrator. In the sensor gate pulse generation circuit 22, a sensor gate pulse SGP1 of the CCD ₁ is formed. This sensor gate pulse SG
P ₁ is supplied to the other input terminal of the AND gate 19. The output of the AND gate 19 is supplied to the sensor gate pulse input terminal 8 of the CCD 1.

Also, a shutter interval control signal from the cycle setting circuit 21
ST is supplied to the other input terminal of the AND gate 23 as a masking signal of the vertical transfer clock. The output of the AND gate 23 is supplied to the other input terminal of the OR gate 24. The output of the OR gate 24 is supplied to the shutter pulse input terminal 10 of the CCD image sensor 1 via the inverter 25.

As shown in FIG. 6A, in the first field period T _A ,
The field switching signal SF is at a low level.
Therefore, in the period T _A of the first field, the AND gate 17
Is always low level, and the vertical transfer clock input terminal 9 of the CCD image sensor 1 is connected to the vertical transfer clock V _CK
Will not be supplied.

The period setting circuit 21 outputs a shutter interval control signal ST as shown in FIG. 6C. A sensor gate pulse generating circuit 22, a sensor gate pulse SGP ₁ at a predetermined timing the shutter interval control signal ST as a reference is formed. In the first field period T _A , the output of the inverter 18 goes high because the field switching signal SF is low. Therefore, in the first field period T _A , the sensor gate pulse SGP ₁ from the sensor gate pulse generation circuit 22 is passed through the AND gate 19. Thus, the sensor gate pulse SGP is supplied to the sensor gate pulse input terminal 8 at the timing shown in FIG. 6E.

In the first field period T _A , the shutter interval control signal ST (FIG. 6C) from the cycle setting circuit 21 is supplied to the OR gate 24 via the AND gate 23. While the shutter interval control signal ST is high, the output of the OR gate 24 is high and the output of the inverter 25 is low. Accordingly, as shown in FIG. 6D, in the first field period T _A , the shutter pulse SHP supplied to the shutter pulse input terminal 10 of the CCD ₁ during the period T _{1 in} which the shutter interval control signal ST is at the high level. Maintained at low level. During this time, charge is stored in the sensor 2.
Then, a period T ₂ during which the shutter pulse SHP is given
Then, the electric charge of the sensor 2 is swept away. Period T ₃ from the shutter pulse SHP is stopped until the sensor gate pulse SGP appears is the accumulation time. Once t _g the sensor gate pulse SGP appears, the charge on the sensor 2 is transferred to the vertical transfer register 3. Period T _{A of} the first field
In, as shown in FIG. 6 B, since the vertical transfer clock V _CK is stopped, the signal transferred to the vertical transfer register 3 at the time t _g is synthesized on the vertical transfer register 3.

In the second field period T _B , as shown in FIG.
The field switching signal SF is at a high level.
Therefore, in the second field, the vertical transfer clock _VCK1 from the terminal 13 is passed through the AND gate 17 and the inverter 27. Accordingly, in the second field period T _B , the vertical transfer clock _VCK is supplied to the input terminal 9 of the vertical transfer clock of the CCD 1 as shown in FIG. 6B.

In the second field period T _B , the field switching signal SF is at a high level.
Output goes low. Therefore, the output of the AND gate 19 is always at the low level, and the sensor gate pulse SGP is not applied to the sensor gate pulse input terminal 8 of the CCD 1 as shown in FIG. 6E.

In the second field period T _B , the field switching signal SF is at a high level.
Is at a low level, and the output of the AND gate 23 is always at a low level. Therefore, the shutter pulse SHP ₁ from the terminal 15 is through the OR gate 24, an inverter 25. Therefore, in the second field period T _B , as shown in FIG. 6D, the shutter pulse input terminal 10
Is always supplied with a shutter pulse SHP. For this reason,
No charge is stored in the sensor 2.

As described above, in the first field, when the vertical transfer clock is stopped and the multiple exposure is performed, and in the second field, only the transfer is performed, as shown in FIG. If a picture is taken with a VTR and this is played back in still or slow mode, stroboscopic playback by multiple exposure can be performed.

〔The invention's effect〕

According to the present invention, in the first field, the electronic shutter is operated intermittently a plurality of times, during which the operation of the vertical transfer register 3 is stopped. In this manner, the electronic shutter is released a plurality of times intermittently during one field, and the screen at that time is synthesized by the vertical transfer register 5, so that multiple exposure is possible. In the second field, the vertical register 3 is operated, and the multiple-exposed signal is transferred. By performing such control, strobe reproduction by multiple exposure can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of an example of a CCD image pickup device in one embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram used to describe an example of the CCD image sensor in the example, FIG. 4 is a cross-sectional view used to describe an example of the CCD image sensor in one embodiment of the present invention, and FIG. FIG. 6 is a timing chart for explaining one embodiment of the present invention, FIG. 7 is a block diagram of an example of a cycle setting circuit in one embodiment of the present invention, and FIG. FIG. 9 is a schematic diagram used for explaining an embodiment, and FIG. 9 is a block diagram used for explaining a flash function of a conventional video camera. Explanation of the reference numerals in the drawings: 1: CCD image sensor, 8: Sensor gate pulse input terminal, 9:
Vertical transfer clock input terminal, 10: Shutter pulse input terminal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/225

Claims (1)

(57) [Claims] 1. A recording / reproducing apparatus in which an image is picked up by a solid-state image pickup device and a video signal obtained from the solid-state image pickup device is recorded / reproduced on a tape-shaped recording medium. A photoelectric conversion element,
A vertical transfer element to which the charge from the photoelectric conversion element is sent via a readout gate; a horizontal transfer element provided at the end side of the vertical transfer element; and sweeping out the charge from the photoelectric conversion element of each pixel to a substrate Charge sweeping means, wherein a charge from the photoelectric conversion element of each pixel is sent to the vertical transfer element by a gate pulse, and a charge from the photoelectric conversion element of each pixel is swept to the substrate by a sweep pulse. And a charge from the photoelectric conversion element of each pixel by the sweep pulse after the charge from the photoelectric conversion element is sent to the vertical transfer element by the gate pulse during the period of the first field. The multiple exposure is performed by repeating the operation of sweeping the signals to the substrate a plurality of times, the signals subjected to the multiple exposure are synthesized by the vertical transfer element, and the second filter is formed. Control means for controlling the transfer of the multi-exposure signal synthesized by the vertical transfer element during the multi-exposure period, and the multi-exposure signal during the first field period during multi-exposure recording. The first azimuth track is recorded, the second azimuth track is set to no signal, and at the time of multiple exposure reproduction, only the reproduction signal of the first azimuth track is reproduced to perform still reproduction or slow reproduction. A recording / reproducing apparatus characterized by the above-mentioned.