JPH0585083B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a buffer amplifier circuit such as a reference voltage generator, and more particularly to a small and economical buffer amplifier circuit having a wide band and low output impedance.

[Background of the invention]

In unipolar and bipolar reference voltage sources such as conventional measuring instruments, it is used to stabilize the output voltage so that it does not change even when the load current fluctuates rapidly.
A buffer amplifier circuit with low output impedance, such as an operational amplifier with negative feedback, is used.
In particular, when the load current is turned on and off quickly by FETs or transistors, the operational amplifier alone cannot keep up with it, and the output impedance becomes high in the high frequency range. This causes fluctuations in the output voltage, so a circuit with a higher frequency band and lower impedance is required, and a small buffer amplifier circuit with a small number of parts is required.

FIG. 5 is a block diagram showing an example of a conventional buffer amplifier circuit of this type. In FIG. 5, this buffer amplifier circuit is composed of an operational amplifier 1 with negative feedback, a high-speed amplifier 2, an output amplifier 3, and a load capacitor C, and the output impedance is changed by the load capacitor C at high frequencies. The voltage is determined by the voltage and is reduced at low frequencies by the negative feedback of the high speed amplifier 2, and the operational amplifier 1 is provided to realize a highly accurate voltage. In this way, it is generally difficult to stably apply negative feedback in a capacitive load circuit because a second pole occurs in the negative feedback loop, but this can be solved by providing a high-speed amplifier 2 to provide a minor feedback to this. This problem was solved by introducing a method of applying negative feedback, making it possible to apply negative feedback in large amounts and at high frequencies, and realizing a circuit with low output impedance over a wide range of frequencies.

FIG. 6 is a bipolar circuit diagram showing an example of a conventional buffer amplifier circuit. In FIG. 6, transistors Q ₅ , Q ₆ , and Q ₇ constitute high-speed amplifier 2 of FIG. 5, and transistors Q ₈ , Q ₉ , and Q ₁₀ constitute output amplifier 3.
Configure. This buffer amplifier circuit can output a bipolar current, that is, an outflow current and an inflow current. The number of transistors used in this circuit is six.

FIG. 7 is a unipolar circuit diagram showing another example of the conventional buffer amplifier circuit. In FIG. 7, transistors Q ₉ and Q ₇₁ constitute the output amplifier 3 of FIG. This buffer amplifier circuit is a modified version of the circuit shown in FIG. 5, which is an example of a unipolar circuit, so that only a flowing current can be output. The number of transistors used in this circuit is five.

However, conventional buffer amplifier circuits have limitations when it is desired to reduce the number of transistors used in order to further downsize the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer amplifier circuit that can be configured to have a low output impedance over a wide range of frequencies with a smaller number of transistors.

[Summary of the invention]

The present invention connects the base of the first transistor to the output of an operational amplifier whose first input is connected to the input terminal, connects its emitter to the output terminal via the first resistor, and connects its collector to the output terminal of the operational amplifier. is connected to the base of the first transistor through the second resistor.
the emitter of the second transistor is connected to the first power supply through a third resistor, its collector is connected to the output terminal, and the output terminal is connected to the second input of the operational amplifier. This is a buffer amplifier circuit in which a bias circuit is connected between an output terminal and a second power supply to provide the functions of an output amplifier and a high-speed amplifier.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is a basic circuit diagram showing an embodiment of a buffer amplifier circuit according to the present invention. In Figure 1,
This buffer amplifier circuit connects the base of a first transistor Q1 to the output of an operational amplifier (op-amp) ₁ whose one input (non-inverting input) is connected to the input terminal IN, and connects its emitter to the output of a first resistor R. ₁ to the output terminal OUT having a load capacitance C,
This collector is connected to the base of the second transistor and connected to the first power supply (positive power supply) V _CC through the second resistor _R2 , and the emitter of the second transistor _Q2 is connected to the third resistor R2. ₃ to the first power supply V _CC and its collector to the output terminal OUT,
Connect the output terminal OUT and the other input (inverting input) of operational amplifier (op-amp) 1, and connect the output terminal
It is constructed by connecting a bias circuit 4 between OUT and the second power supply (negative power supply) _VEE . Note that the transistor
Q ₁ and Q ₂ constitute an amplifier that simultaneously realizes the functions of the conventional output amplifier 2 (FIG. 5) and the high-speed amplifier 3.

With this configuration, the output signal of the operational amplifier 1 based on the input signal of the input terminal IN is voltage amplified by the transistor _Q1 and current amplified by the transistor _Q2 , so that a large output current is outputted to the output terminal OUT. Furthermore, since the transistors Q ₁ and Q ₂ form a cascade-connected emitter-grounded amplifier, it has high speed and high gain, and since negative feedback is applied from the output terminal OUT, it functions as a conventional high-speed amplifier.

Next, the output impedance of this circuit will be explained. The voltage gain obtained by transistors Q ₁ and Q ₂ , that is, the closed loop gain of the amplifier, is expressed by the following equation.

A = A _V × G × X _C where A _V is the voltage amplification factor of transistor _Q1 , G
is the voltage-to-current conversion mutual conductance of the transistor _Q2 , and _Xc is the impedance of the load capacitance C connected to the output terminal OUT.

The output impedance Z ₀ of this amplifier becomes the impedance X _C of the load capacitance C when negative feedback is not applied, so the amount of negative feedback (open loop gain)
When negative feedback of A is applied, the following results.

Z _{0 =} X _C / A = _{X C} / ( _{A V × G ×}
When used as R ₂ and R ₃ , it can be expressed as follows.

A _V = R ₂ / R ₁ G = 1 / R ₃ Therefore, Z ₀ = R ₁ × R ₃ / R ₂ If the resistance values R ₁ , R ₂ , and R ₃ are selected appropriately, low output impedance can be obtained. realizable.

Further, the limit of the operating frequency of this amplifier is expressed by the following equation.

A= _{A V × G ×X C ≧ 1} That _is ,
At frequencies below the frequency where R ₁ ×R ₃ /R ₂ decreases, the output impedance Z ₀ becomes Z ₀ =
It becomes R ₁ ×R ₃ /R ₂ . Furthermore, at frequencies higher than this frequency, due to the effect of load capacitance C, Z ₀ = X _C ≦ R ₁ ×
It becomes R ₃ /R ₂ . In this way, low output impedance is achieved over a wide band.

In this way, according to this embodiment, the functions of an output amplifier and a high-speed amplifier, which were conventionally constructed using separate transistors, can be simultaneously realized using the above-mentioned amplifier with a smaller number of transistors.
Further, an operational amplifier 1 is connected to the above-mentioned low output impedance amplifier to achieve high voltage accuracy, and the negative feedback provided by the operational amplifier 1 further reduces the output impedance at low frequencies.

FIG. 2 is a unipolar circuit diagram showing another embodiment of the buffer amplifier circuit according to the present invention. In FIG. 2, this buffer amplifier circuit consists of an operational amplifier 1
, transistors Q ₁ , Q ₂ , and resistors R ₁ , R ₂ , and R ₃ constitute the same amplifier as the basic circuit in Figure 1, and the constant current source using transistor Q ₃ is configured as the bias circuit in Figure 1. 4, a resistor _R6 is inserted between the output of the operational amplifier 1 and the base of the first transistor _Q1 , its base is connected to the collector of the transistor _Q4 , and the emitter of the transistor _Q4 is connected to the output terminal OUT. and connect its base to the output terminal OUT through the resistor R ₄ , these transistors
Q ₄ and resistors R ₄ and R ⁶ constitute and add a current limiting circuit for output short circuit protection. As the load capacitor C in FIG. 1, a plurality of load capacitors (capacitors) C ₁ , C ₂ , and C ₃ having different capacities are connected in parallel in order to suppress an increase in impedance due to self-resonance at high frequencies.

Next, FIG. 3 is a diagram showing an example of the frequency characteristic of the output impedance shown in FIG. 2. Figure 3 shows the resistance in Figure 2.
The characteristics are shown when R ₁ = 10Ω, R ₂ = 1KΩ, and R ₃ = 10Ω. In this case, the output impedance Z ₀ =
Transistors Q ₁ and Q ₂ are shown as R ₁ ×R ₃ /R ₂
Considering the impedance of the emitter γ _e ≒ 6.5Ω, it is determined as follows.

Z ₀ = (R ₁ + γ _e ) (R ₃ + γ _e ) / R ₂ = (10 + 6.5) (10 + 6.5) / 1000 = 272 (mΩ) In contrast, the maximum output impedance Z ₀ in Figure 3 The value was 300 mΩ, which is almost in agreement with the above theoretical value, and low output impedance values were obtained over a wide frequency range from direct current to 100 MHz or more. Note that the dip in the output impedance Z ₀ at frequencies above 1 MHz in this characteristic curve is due to the self-resonance of the load capacitances (capacitors) C ₁ , C ₂ , and C ₃ . By connecting them, it is possible to suppress an increase in output impedance due to self-resonance of the load capacitance C at high frequencies.

In this way, according to this embodiment, low output impedance can be achieved in a wide frequency band,
Although the characteristics are the same as those of the conventional circuit shown in FIG. 7, the number of transistors used can be reduced to three from five in the conventional circuit, thereby achieving miniaturization and cost reduction of the circuit. Note that the unipolar circuit in this embodiment is a type in which the output current flows, but by replacing the NPN polarity of the transistor shown in Fig. 2 with PNP, it is possible to create a buffer amplifier circuit in which the unipolar type is made into a type in which the output current flows. You can also do it.

FIG. 4 is a bipolar circuit diagram showing still another embodiment of the buffer amplifier circuit according to the present invention. This buffer amplifier circuit consists of the unipolar outflow type circuit shown in Fig. 2 and the polarity change of its transistors Q ₁ and Q ₂ .
Transistors Q ₁₁ and Q ₂₁ with NPN replaced with PNP
A bipolar circuit is constructed by combining a unipolar flow-in type circuit constituted by resistors R ₁₁ , R ₂₁ , and R ₃₁ . According to this embodiment, it is possible to obtain low output impedance characteristics over a wide frequency range equivalent to the conventional one shown in FIG. 6, but the number of transistors used is 5 (constant current source transistor
).

According to the embodiments described above, low output impedance characteristics in a wide frequency band can be realized with a smaller number of transistors, and the following effects can be obtained. That is, while the conventional circuit requires a capacitor of, for example, 1 μF as the load capacitance, the circuit of this embodiment can obtain equivalent characteristics with a capacitor of, for example, 0.1 μF. This is because negative feedback is applied due to the inclusion of emitter resistance in the transistors Q ₁ and Q ₂ , and the frequency characteristics of each transistor are improved, which improves the limit frequency of the amplifier. Since the load capacitance C can be made small in this way, the charging/discharging current is reduced and the frequency characteristics as a buffer are also improved. Furthermore, the circuit of this example has a characteristic that the output impedance Z ₀ is independent of the load capacitance C over a wide frequency range and is determined as Z ₀ = R ₁ × R ₃ /R _2. Therefore, an inexpensive capacitor is used for the load capacitance C. At the same time, it can also be used as a general buffer circuit for driving capacitive loads. It is also possible to add a resistor to the operational amplifier to provide gain to the circuit.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a buffer amplifier circuit that can achieve a low output impedance characteristic over a wide range of frequencies with a small number of transistors and can be made smaller and lower in price.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram showing one embodiment of the buffer amplifier circuit according to the present invention, Fig. 2 is a unipolar circuit diagram showing another embodiment according to the invention, and Fig. 3 is a characteristic example diagram of Fig. 2. , FIG. 4 is a bipolar circuit diagram showing still another embodiment of the present invention, FIG. 5 is a block diagram showing an example of a conventional buffer amplifier circuit, and FIG. 6 is a bipolar circuit diagram of a conventional buffer amplifier circuit. Circuit diagram, 7th
The figure is a unipolar circuit diagram of a conventional buffer amplifier circuit. 1... operational amplifier, 4... bias circuit, Q ₁ ,
Q ₂ ...first and second transistors, Q ₃ , Q ₄ ,
Q ₁₁ , Q ₂₁ ...transistor, R ₁ , R ₂ , R ₃ , R ₄ ,
R ₆ , R ₁₁ , R ₂₁ , R ₃₁ ...Resistance, C, C ₁ , C ₂ , C ₃ ...
…Load capacity, IN…Input terminal, OUT…Output terminal, V _CC , V _EE …Power supply.

Claims (1)

[Claims] 1. A first input of an operational amplifier is connected to an input terminal, a base of a first transistor is connected to an output of the operational amplifier, and an emitter of the first transistor is connected to a first resistor. the collector of the first transistor is connected to the base of the second transistor, and the collector of the first transistor is connected to the first power supply via the second resistor; an emitter of a second transistor is connected to the first power supply via a third resistor, and a collector of the second transistor is connected to the output terminal;
A buffer amplifier circuit comprising: connecting the output terminal to a second input of the operational amplifier; and connecting a bias circuit between the output terminal and a second power supply. 2. In the buffer amplifier circuit according to claim 1, the first and second transistors are each
A buffer amplifier circuit that forms a unipolar buffer amplifier circuit with either a flow-out type or a flow-in type output current as an NPN transistor or a PNP transistor, and combines both buffer amplifier circuits to create a bipolar buffer amplifier circuit. 3. The buffer amplifier circuit according to claim 2, wherein the bias circuit is a constant current source circuit. 4. The buffer amplifier circuit according to claim 1, 2, or 3, wherein a current limiting circuit made of a transistor is connected between the base of the first transistor and the output terminal. 5 Claims 1 and 2 or 3
The buffer amplifier circuit according to item 1 or 4, wherein a plurality of load capacitors having different capacitance values are connected to the output terminal.