JPS62172785A - Electronic parts - Google Patents
Electronic partsInfo
- Publication number
- JPS62172785A JPS62172785A JP61014078A JP1407886A JPS62172785A JP S62172785 A JPS62172785 A JP S62172785A JP 61014078 A JP61014078 A JP 61014078A JP 1407886 A JP1407886 A JP 1407886A JP S62172785 A JPS62172785 A JP S62172785A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- film layer
- thin film
- nickel plating
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 59
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 50
- 239000010931 gold Substances 0.000 claims description 49
- 229910052737 gold Inorganic materials 0.000 claims description 49
- 239000010408 film Substances 0.000 claims description 27
- 229910052759 nickel Inorganic materials 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000010304 firing Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 37
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000011521 glass Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- -1 or Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えばＩＣＣチップ縁縁基板上搭載した、
厚膜サーマルヘッドの如き′電子部品の小型化、低価格
化、及び製造上の改良に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides, for example, an ICC chip mounted on an edge substrate,
This invention relates to miniaturization, cost reduction, and manufacturing improvements in electronic components such as thick film thermal heads.
第２図は、従来のＩＣ搭載型の厚膜サーマルヘッドと呼
ばれる電子部品の断面図であり、図ニオいて、（１）は
例えばアルミナセラミックからなる絶縁基板、（２）は
絶縁基板ＩＩ＋全面に薄く均一に厚膜金ベース）１印刷
し、焼成した後写真製版、食刻技術により導体パターン
を形成した金薄膜層、（３）は導体パターン形成した金
薄膜層（２）上に厚膜抵抗ペーストを印刷、焼成し形成
した厚膜抵抗体、（４）は１１７膜抵抗体（３）及びそ
の近傍の金薄膜層全保護する為、厚膜ガラスペーストを
印判、焼成し形成した保護ガラス、（６）は絶縁基板Ｉ
ＩＩ上に接着剤等で固定されたＩＣチップ、（８）＃−
ｊ４体パターン形成した金Ｍ１層□（２１とＩＣチップ
を電気的に接続する金ワイヤ、（９）は、工Ｃチップ（
６）、金ワイヤ（８）？保護する、例えばシリコーン樹
脂からなる保護頃脂である。Figure 2 is a cross-sectional view of an electronic component called a conventional IC-mounted thick film thermal head. Thin and uniform thick film gold base) 1. A thin gold film layer on which a conductor pattern is formed by photolithography and etching techniques after printing and baking. (3) A thick film resistor on the thin gold film layer (2) on which a conductor pattern is formed. Thick film resistor formed by printing and firing the paste, (4) is a protective glass formed by stamping and firing thick film glass paste to protect the 117 film resistor (3) and the entire gold thin film layer in the vicinity. (6) is an insulating substrate I
IC chip fixed on II with adhesive etc., (8) #-
The gold M1 layer □ (21) and the gold wire that electrically connects the IC chip (21) and the IC chip (9) are
6), gold wire (8)? For example, it is a protective layer made of silicone resin.
次に動作について説明する。絶縁基板ｔｌｌ上に複数個
の発熱抵抗体を配置し、該発熱抵抗体を選択的にスイッ
チングし、発熱抵抗体上の感熱記録紙（図示せず）等て
文字記号等記録する電子部品がサーマルヘッドであり、
第２図において、厚膜抵抗体（３）が発熱抵抗体に、工
Ｃチップ（６）が選択的スイッチング素子に対応してい
る。Next, the operation will be explained. A plurality of heat generating resistors are placed on an insulating substrate tll, the heat generating resistors are selectively switched, and an electronic component for recording characters, symbols, etc. on a thermal recording paper (not shown) on the heat generating resistors is thermally activated. is the head,
In FIG. 2, the thick film resistor (3) corresponds to the heating resistor, and the C-chip (6) corresponds to the selective switching element.
さて、工Ｃチップ（６）と絶縁基板＋１１上に形成した
導体パターンとの電気的接続方法には半田付け、ワイヤ
ポンド等の方法が用いられるが、厚膜抵抗体（３）及び
保護ガラス（４）の形成プロセス上、導体には、金を用
いることが必要となり、絶縁基板＋１１上の金薄膜層（
２）は厚膜金ペーストが用いられ、ＩＣチップ（６）と
の接続ＶＣｆ″ｉ金ワイヤ（８）を用いてのワイヤボン
ドが用いられた。Now, methods such as soldering and wire bonding are used to electrically connect the C chip (6) and the conductor pattern formed on the insulating substrate +11, but the thick film resistor (3) and the protective glass ( Due to the formation process of 4), it is necessary to use gold for the conductor, and the gold thin film layer (
In 2), a thick film gold paste was used, and a wire bond using a VCf''i gold wire (8) was used for connection to the IC chip (6).
この導体が金の場合、ワイヤポンドが用いられる理由は
、スズ、鉛合金の半田を金薄膜層（２１上に半田付けし
た場合、金が半田の中に食われてしまい、金薄膜層（２
］のはがれ、食われにより、スズ・鉛合金は使えず、し
たがって高価な低融点のインジクム半田を用いることが
必要となる。しかるに、ＩＣチップ（６）上の接続点箇
所に、スズ・鉛合金の半田バンプ形成プロセスは容易で
あるが、インジクム半田バンプは高価、低融点等の条件
で実現がチｔしいからである。When this conductor is gold, the reason why a wire pond is used is that when a tin-lead alloy solder is soldered onto the gold thin film layer (21), the gold is eaten into the solder, and the gold thin film layer (21
] Because of peeling and erosion, tin-lead alloy cannot be used, and therefore it is necessary to use expensive low-melting-point Indicum solder. However, although the process of forming tin-lead alloy solder bumps at the connection points on the IC chip (6) is easy, it is difficult to realize indicum solder bumps due to their high cost and low melting point.
ところで、金ワイヤ（８）と金薄膜層（２）との接着強
度は、ワイヤポンド条件により異なり、その条件管理は
難しいものであるが、金薄膜層（２１の的に大となる。Incidentally, the adhesive strength between the gold wire (8) and the gold thin film layer (2) differs depending on the wire bonding conditions, and although it is difficult to control the conditions, it is the target of the gold thin film layer (21).
この強度的に許容可能な金薄膜層（２）の最低膜厚とし
ては２〜３ミクロン程度である。The minimum thickness of the gold thin film layer (2) that is allowable in terms of strength is about 2 to 3 microns.
また、ワイヤポンドでは、企ワイヤ（８）の隣接ワイヤ
同志のタッチによる歩留り悪化や、金ワイヤ（８）の線
長が無視できず、サーマルヘッドの小型化への要求のさ
またげとなる。In addition, in the case of a wire pond, the yield is deteriorated due to the touch of adjacent wires of the wire (8), and the wire length of the gold wire (8) cannot be ignored, which hinders the demand for miniaturization of the thermal head.
従来のサーマルヘッドと呼ばれる電子部品は以上のよう
に構成されているので、高価な金薄膜層を２〜３ミクロ
ン厚以下にすることができず、電子部品の高１１１Ｉｉ
格化につながり、また、小力μ化できないなどの問題点
があった。Conventional electronic components called thermal heads are constructed as described above, so it is not possible to reduce the thickness of the expensive gold thin film layer to less than 2 to 3 microns, and the height of the electronic component is 111Ii.
There were also problems such as the inability to reduce the power to μ.
この発明は上記のような問題点を解消するためになされ
たもので、金薄膜層の厚みを薄くし、サーマルヘッドの
ような電子部品の低師格化、より小型化を目的とする。This invention was made to solve the above-mentioned problems, and aims to reduce the thickness of the gold thin film layer, thereby making electronic components such as thermal heads less expensive and more compact.
この発明に係る電子部品は、絶縁基板上に金薄膜層の導
体パターンを形成し、その金薄膜層の上にニッケルメッ
キ層を設け、ＩＣチップ等の能動素子を半田付けしたも
のである。The electronic component according to the present invention has a conductive pattern of a thin gold film layer formed on an insulating substrate, a nickel plating layer provided on the thin gold film layer, and an active element such as an IC chip soldered thereto.
この発明における電子部品は、金薄膜層上に、スズ・鉛
合金の半田付は可能なニッケルメッキを施すことにより
、半田バンプ形成したＩＣチップを電気的に接続可能と
することに特徴があり、ニッケルメッキ？無電解ホウ票
系ニッケルメッキを用いて行なうことに特徴がある。The electronic component of the present invention is characterized in that an IC chip on which solder bumps are formed can be electrically connected by applying nickel plating, which can be soldered to a tin-lead alloy, on the gold thin film layer. Nickel plating? It is characterized by the use of electroless nickel plating.
〔矢施例〕 以下、この発明の一実施例を図について説明する。[Arrow example] An embodiment of the present invention will be described below with reference to the drawings.
第１図はその断面図を示すものであり、図において、ｔ
ｌｌは例えばアルミナセラミックからなる絶縁基板、（
２１は絶縁基板ＩＩ＋全面に有機金ペースト、たとえば
エンゲルハード社製メタルオーカ゛ニックＡ−４６１５
と薄く均一に令布し、焼成して厚さ０．３ミクロン程度
にし、写真製版、食刻技術によシ導体パターン全形成し
た金薄膜層、（３）は導体パターン形成した金薄膜層（
２）上に厚膜抵抗ペーストを印刷、焼成し形成した厚膜
抵抗体、１４】は厚膜抵抗体（３Ｊ、及び近傍の金薄膜
層を保護する為、厚膜ガラスペーストを印刷、焼成し形
成した保護ガラス、（５）は金薄膜層（２）上の一部に
形成されたニッケルメッキ層、（６）は半田バンプ（７
）全形成された工Ｃチップ、（９１は工Ｃテップ（６）
全保護する、例えばシリコーン樹脂からなる築護樹脂で
ある。FIG. 1 shows its cross-sectional view, and in the figure, t
ll is an insulating substrate made of alumina ceramic, for example (
21 is an insulating substrate II + an organic gold paste on the entire surface, such as Metal Organic A-4615 manufactured by Engelhard.
(3) is a gold thin film layer with a conductor pattern formed thereon, and then fired to a thickness of about 0.3 microns.
2) A thick film resistor is formed by printing and firing a thick film resistor paste on it, 14] is a thick film resistor (3J, and in order to protect the nearby gold thin film layer, a thick film glass paste is printed and fired. The formed protective glass, (5) is the nickel plating layer formed on a part of the gold thin film layer (2), and (6) is the solder bump (7).
) Fully formed C tip, (91 is C tip (6)
For example, it is a protective resin made of silicone resin that provides total protection.
次に動作について説明する。サーマルヘッドなる電子部
品の印字作用については従来例と同様である。さて、従
来例にて説明したように、金薄膜層ｔ２１には半田付け
が難であり、ワイヤボンドを用いることが必要のため、
金薄膜層（２１ヲ２〜３ミクロン厚以下にすることは問
題があった、
しかるに、工Ｃチップ（６）との接続導体箇所のみ金で
なく、半田付けが容易な銅、ニッケル等であれば、工Ｃ
チップ（６）の接続点箇所に、スズ・鉛合金の半田バン
プ（７）全形成したフリツプチツプエＣの接続は容易で
ある。Next, the operation will be explained. The printing operation of the electronic component called the thermal head is the same as in the conventional example. Now, as explained in the conventional example, since it is difficult to solder the gold thin film layer t21 and it is necessary to use wire bonding,
There was a problem with making the gold thin film layer (21) less than 2 to 3 microns thick.However, only the connection conductor part with the C-chip (6) could be made of copper, nickel, etc., which is easy to solder, instead of gold. B, Engineering C
It is easy to connect the flip chip C, in which solder bumps (7) of tin-lead alloy are completely formed at the connection points of the chip (6).
したがって、絶縁基板＋１１上におけるＩＣチップ１６
）の半田バンプ１７（との接続点となる金薄膜層（２１
部分を銅又はニッケルにて被えばよく、半田付けに必要
な銅又はニッケルの導体膜厚が得られれば、金ｎ暎層（
２１はより薄くて済む。以上のことから発明者は、種々
の天険の債、金薄膜層＋２１ ？ 、エンゲルハード社
製メタルオーガニックＡ４６１５なる有機金ペーストの
・情布、焼成にて、０．Ｓミクロン厚にて製造し、次い
で、厚膜抵抗体（３）、保護ガラス（４１ヲ形成した後
、該基板をｒ俊洗い、アルカリ洗いを数分同行ない純水
にて洗浄し、金綺膜Ｉ＋！！ ＋２１表面を活性化させ
、全面にホトレジストを塗布し、半田付は部分のみ除去
させた後、無電解ホウ素系ニッケルメッキ液浴（微量の
ホウ素を金回する）中に、該基板を揺動し、数十分浸漬
させ、Ｏ，Ｓミクロン厚の金薄膜層（２１上に、ホウ素
ニッケル合金を２〜８ミクロン厚析出し、ニッケルメッ
キｆｌ ！５１ ’に形成した。Therefore, the IC chip 16 on the insulating substrate +11
) of the gold thin film layer (21
It is sufficient to cover the part with copper or nickel, and if the copper or nickel conductor film thickness required for soldering is obtained, a gold layer (
21 can be made thinner. Based on the above, the inventor has created various natural bonds, gold thin film layer +21? 0.0% by firing the organic gold paste, Metal Organic A4615 manufactured by Engelhard. After forming the thick film resistor (3) and the protective glass (41), the substrate was washed with pure water followed by alkaline washing for a few minutes, and then the metal was cleaned. After activating the film I+!!+21 surface, applying photoresist to the entire surface, and removing only the soldered parts, the substrate was placed in an electroless boron-based nickel plating solution bath (a trace amount of boron was added). The sample was shaken and immersed for several minutes, and a boron-nickel alloy was deposited to a thickness of 2 to 8 microns on the O, S micron thick gold film layer (21) to form a nickel plating fl!51'.
この後、ホトレジストを剥離し、７リツプチツプエＣの
半田付は可能なサーマルヘッド基板を完成させた。Thereafter, the photoresist was peeled off, and a thermal head board capable of soldering with 7 lip chips C was completed.
この完成されたサーマルヘッド基板を数百度の加熱台Ｖ
Ｃ截せ、７リツブチツプＩＣ″ｆｔ：基板の搭載位置に
位置決めし、加圧、加熱でることにより、半田バンプ（
７）がニッケルメッキ層（５）に付着し、ＩＣチップ（
６）全接続し、従来例より比べて、金ワイヤの線長分だ
け小型化した。ここで金薄膜層（２１上の銅メッキは可
能であったが、酸化拡散の問題があり、望ましくなかっ
た。また無電解リン系ニッケルメッキ液・液では、ニラ
グルメツキ析出が琲しく、：ｍ電解ホウ禾系ニッケルメ
ッキをストライクに用いた後では可能であった。This completed thermal head board is heated to several hundred degrees on a heating stand V.
Cut out the 7-rib chip IC″ft: Position it at the mounting position on the board, pressurize it, and heat it to make the solder bumps (
7) adheres to the nickel plating layer (5), and the IC chip (
6) All connections are made, and the size is reduced by the length of the gold wire compared to the conventional example. Here, copper plating on the gold thin film layer (21) was possible, but it was undesirable due to the problem of oxidation diffusion.Furthermore, with electroless phosphorus-based nickel plating solution, the precipitation of niraglumetaki was severe; This was possible after using porcelain-based nickel plating for the strike.
ニッケルメッキは必ずしも漂電解ホウ素系ニッケルメッ
キに限らない。結果として、ニッケルメッキが得られれ
ば良いのだが、発明者の試みた範囲では無′亀解ホウ票
ニッケルメッキでたまたま良い結果が得られたと云うこ
とでめる・ニッケルメッキ層は純粋なＮ１であって良い
し、ニッケル合金であっても良い。Nickel plating is not necessarily limited to drifted boron-based nickel plating. As a result, it would be good if nickel plating could be obtained, but within the scope of the inventor's attempts, good results were obtained by chance using nickel plating without any oxidation.The nickel plating layer was made of pure N1. It may be a nickel alloy.
なお、上記実施例では、金薄膜層１２１が有機金ペース
トの焼成の場合について示したが、厚膜金ペーストであ
ってもよく、微少な銅成分が混入した金ペーストであっ
てもよく、また、ニッケルメッキ層（５）上下部に池の
金属を界在させてもよい。さらに、サーマルヘッドに限
らず、金パターンから形成される池の各種の電子部品で
あってもよく上記実施例と同様の幼果を奏することは明
らかである。In the above embodiment, the gold thin film layer 121 is made of fired organic gold paste, but it may be a thick film gold paste, a gold paste mixed with a minute amount of copper, or , metal may be interposed between the upper and lower parts of the nickel plating layer (5). Furthermore, it is clear that the present invention is not limited to the thermal head, and that various electronic parts of the pond made of gold patterns may be used to produce the same young fruit as in the above embodiment.
以上のように、この発明によれば、絶縁基板上に金薄膜
層の導体パターンを形成し、金薄膜層の一部又は全面に
ニッケルメッキ層を設け、受動素子、能動素子のチップ
を半田付けした構成にしたので、金薄膜層の厚みを薄く
でき、電子部品の低価格化、より小型化が得られる効果
がある。As described above, according to the present invention, a conductive pattern of a thin gold film layer is formed on an insulating substrate, a nickel plating layer is provided on a part or the entire surface of the thin gold film layer, and chips of passive elements and active elements are soldered. With this structure, the thickness of the gold thin film layer can be reduced, which has the effect of lowering the price and making the electronic components more compact.
第１図はこの発明の一実施例によるサーマルヘッドの如
き電子部品の断面図、第２図は従来のサーマルヘッドの
如き電子部品の断面図である。図について、（１１は絶
縁基板、（２）は金薄膜層、（５１はニッケルメッキ層
、（６）はＩＣチップ、（））は半田バンプ。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a sectional view of an electronic component such as a thermal head according to an embodiment of the present invention, and FIG. 2 is a sectional view of an electronic component such as a conventional thermal head. Regarding the figures, (11 is an insulating substrate, (2) is a gold thin film layer, (51 is a nickel plating layer, (6) is an IC chip, and ()) is a solder bump. In addition, the same symbols in the figures are the same or equivalent. Show parts.
Claims (7)
該金薄膜層上の少なくとも一部にニッケルメッキ層を設
け、このニッケルメッキ層の上に受動素子、又は能動素
子のチップを半田付けしたことを特徴とする電子部品。(1) Forming a conductor pattern of a thin gold film layer on an insulating substrate,
An electronic component characterized in that a nickel plating layer is provided on at least a portion of the gold thin film layer, and a chip of a passive element or an active element is soldered onto the nickel plating layer.
ることを特徴とする特許請求の範囲第１項記載の電子部
品。(2) The electronic component according to claim 1, wherein the gold thin film layer is formed by firing a thick film gold paste.
ることを特徴とする特許請求の範囲第１項記載の電子部
品。(3) The electronic component according to claim 1, wherein the composite thin film layer is formed by firing an organic gold paste.
ることを特徴とする特許請求の範囲第１項、第２項、第
３項のいずれかに記載の電子部品。(4) The electronic component according to any one of claims 1, 2, and 3, wherein the gold paste contains at least copper.
ッキにより形成されることを特徴とする特許請求の範囲
第１項、第２、第３項、第４項のいずれかに記載の電子
部品。(5) The electronic component according to any one of claims 1, 2, 3, and 4, wherein the nickel plating layer is formed by electroless boron-based nickel plating.
れサーマルヘッドを形成することを特徴とする特許請求
の範囲第１項、第２項、第３項、第４項、第５項のいず
れかに記載の電子部品。(6) Claims 1, 2, 3, 4, and 5, characterized in that the conductor pattern of the gold thin film layer is connected to a heating resistor to form a thermal head. Electronic components listed in any of the above.
特徴とする特許請求の範囲第１項、第２項、第３項、第
４項、第５項、第６項のいずれかに記載の電子部品。(7) Any one of claims 1, 2, 3, 4, 5, and 6, characterized in that the passive element or the active element is an integrated circuit. Electronic components listed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61014078A JP2703757B2 (en) | 1986-01-24 | 1986-01-24 | Electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61014078A JP2703757B2 (en) | 1986-01-24 | 1986-01-24 | Electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62172785A true JPS62172785A (en) | 1987-07-29 |
| JP2703757B2 JP2703757B2 (en) | 1998-01-26 |
Family
ID=11851071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61014078A Expired - Fee Related JP2703757B2 (en) | 1986-01-24 | 1986-01-24 | Electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2703757B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50103275A (en) * | 1974-01-11 | 1975-08-15 | ||
| JPS5586130A (en) * | 1978-12-25 | 1980-06-28 | Hitachi Ltd | Connection of semiconductor element |
-
1986
- 1986-01-24 JP JP61014078A patent/JP2703757B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50103275A (en) * | 1974-01-11 | 1975-08-15 | ||
| JPS5586130A (en) * | 1978-12-25 | 1980-06-28 | Hitachi Ltd | Connection of semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2703757B2 (en) | 1998-01-26 |
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