JPS62172720A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62172720A JPS62172720A JP1439886A JP1439886A JPS62172720A JP S62172720 A JPS62172720 A JP S62172720A JP 1439886 A JP1439886 A JP 1439886A JP 1439886 A JP1439886 A JP 1439886A JP S62172720 A JPS62172720 A JP S62172720A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- silicon wafer
- oxide film
- wafer
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 9
- 239000002253 acid Substances 0.000 claims abstract description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000005406 washing Methods 0.000 abstract description 4
- 238000001704 evaporation Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000001035 drying Methods 0.000 abstract description 2
- 230000003472 neutralizing effect Effects 0.000 abstract description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
、産1」ぶり旧1分立
本発明は半導体装置の製造方法に関し、特に電極層を蒸
着するにあたってウェハとのオーミックコンタクトを良
好にする電極層の蒸着前処理工程を改良したものである
。[Detailed Description of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular improves a pre-evaporation treatment process for an electrode layer to improve ohmic contact with a wafer when depositing an electrode layer. This is what I did.
従来二技丑
例えばダイオードやトランジスタなどの素子のの裏面(
デバイスを形成しない側の面)に裏電極層を形成する場
合、シリコンウエノ\の表面側に前記のようなデバイス
を形成した後、シリコンウェハの裏面側を機械的に研摩
して薄くさせてから、この研摩面に所望の電極層を蒸着
させている。しかし、研摩面には非常に薄い膜厚の自然
酸化膜が形成されるため、シリコンウエノλに対する前
記電極層のオーミック特性および電極層の密着強度とい
う点においてあまり良好でないことが知られている。Traditionally, two techniques have been used: For example, the back side of elements such as diodes and transistors (
When forming a back electrode layer on the surface on which no devices are formed, after forming the above-mentioned device on the front side of the silicon wafer, mechanically polish the back side of the silicon wafer to make it thinner. , a desired electrode layer is deposited on this polished surface. However, since a very thin native oxide film is formed on the polished surface, it is known that the ohmic properties of the electrode layer and the adhesion strength of the electrode layer to silicon wafer λ are not very good.
このような場合には、前記研摩面をHF系の薬液で軽く
ケしカルエツチングしてから超音波水洗することで、研
摩面に形成された自然酸化膜を除去させるといった処理
を行うのが適当であると考えられている。In such a case, it is appropriate to perform a treatment such as lightly quenching the polished surface with an HF-based chemical solution and then performing ultrasonic water washing to remove the natural oxide film formed on the polished surface. It is believed that
O<ゞしよ゛と る。占
ところが、前述のようなHF系の薬液を用いると、シリ
コンウェハの表面(デバイスを形成している側の面)に
形成されているシリコン酸化膜などがエツチングされる
から、これを防止するために、エツチング前においてシ
リコンウエノ\の表面側をレジストなどで覆うといった
煩わしい作業を追加しなければならない。しかも、エツ
チング後において前記レジストなどを除去する工程によ
ってせっかくエツチング処理した面が汚染されるのは避
けられない。O <I'll do it. However, if the HF-based chemical solution mentioned above is used, the silicon oxide film formed on the surface of the silicon wafer (the side on which devices are formed) will be etched, so to prevent this, In addition, it is necessary to add the troublesome work of covering the surface side of the silicone wafer with a resist or the like before etching. Moreover, it is inevitable that the etched surface will be contaminated by the process of removing the resist and the like after etching.
このようなことから、現状では前述のようなHF系の薬
液でのエツチングを行なわずに、シリコンウェハに対す
る電極層のオーミック特性および密着強度を多少犠牲に
しなければならなかった。For this reason, at present, the ohmic properties and adhesion strength of the electrode layer to the silicon wafer have to be sacrificed to some extent without performing etching with an HF-based chemical as described above.
本発明は上記事情に鑑みて創案されたもので、簡単かつ
有効な作業でもってシリコンウェハに対する電極層のオ
ーミック特性を良好にしかも密着強度を向上できる半導
体装置の製造方法を提供することを目的としている。The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the ohmic characteristics of an electrode layer to a silicon wafer and improve the adhesion strength with simple and effective operations. There is.
口 占 iンするための
本発明にかかる半導体装置の製造方法は、電極層を蒸着
すべきシリコンウェハをKOHによりケミカルエツチン
グしてから仮水洗し、このシリコンウェハの前記エツチ
ング部分を酸系の薬液でもって中和処理させて超音波水
洗させた後、そこに所望の電極層を蒸着させるようにし
ている。In the method for manufacturing a semiconductor device according to the present invention, a silicon wafer on which an electrode layer is to be deposited is chemically etched with KOH and then temporarily washed with water, and the etched portion of the silicon wafer is etched with an acid-based chemical solution. After neutralization treatment and ultrasonic water washing, a desired electrode layer is deposited thereon.
■
KOHを用いるからエツチング時におけるシリコンウェ
ハとの反応が比較的遅くなると共に、シリコンウェハの
露出部分以外が不要にエツチングされない。KOHがア
ルカリ系であるがらに+イオンが原因となって前記シリ
コンウェハのエツチング面が汚染されると考えられるが
、これは酸系の薬液でもって中和処理して超音波水洗を
行うことにより、前記エツチング面が活性化される。(2) Since KOH is used, the reaction with the silicon wafer during etching is relatively slow, and areas other than the exposed portion of the silicon wafer are not unnecessarily etched. Although KOH is alkaline, the etching surface of the silicon wafer is thought to be contaminated by positive ions, but this can be prevented by neutralizing it with an acid-based chemical solution and performing ultrasonic water cleaning. , the etched surface is activated.
災凰皿
以下図面を参照して本発明の一実施例について説明する
。ここでは、ダイオードの裏電極層を形成する場合とし
、シリコンウェハにおける1素子に着目して説明してい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Here, a case is described in which a back electrode layer of a diode is formed, focusing on one element on a silicon wafer.
第1図(a)において、N形のシリコシウェハ1には、
N−形のエピタキシャル層2が成長されていて、エピタ
キシャル層2の表面側にはP形不純物領域3が埋め込ま
れている。エピタキシャル層2の上面には、シリコン酸
化膜4が被着されている。In FIG. 1(a), an N-type silicon wafer 1 includes:
An N-type epitaxial layer 2 is grown, and a P-type impurity region 3 is embedded in the surface side of the epitaxial layer 2. A silicon oxide film 4 is deposited on the upper surface of the epitaxial layer 2 .
P形不純物領域3の表面のシリコン酸化膜4は窓開けさ
れていて、ここにP形の表電極層5が被着されている。A window is opened in the silicon oxide film 4 on the surface of the P-type impurity region 3, and a P-type front electrode layer 5 is deposited thereon.
このようなデバイスが形成されたシリコンウェハ1の裏
面(デバイスが形成されていない側の面)を例えば12
5〜150μm程度の厚さに機械的に研摩する。この研
摩面は凹凸になっていて後から蒸着する裏電極層の蒸着
面積が大きくなるので好ましいが、ここには非常に薄い
自然酸化膜6が形成されるのを防ぐことはできない(第
1図(b)参照)。For example, the back side of the silicon wafer 1 on which such devices are formed (the side on which no devices are formed) is
Mechanically polished to a thickness of about 5 to 150 μm. This polished surface is uneven, which is preferable because it increases the deposition area of the back electrode layer that will be deposited later, but it cannot prevent the formation of a very thin native oxide film 6 on this surface (see Figure 1). (see (b)).
よってこの研摩面について下記する処理を行う。Therefore, the following process is performed on this polished surface.
まず、エツチング槽内に入れたKOHを約4d〜60℃
に恒温し、ここに前述のシリコンウェハ1を約1〜3分
間浸漬することにより、シリコンウェハ1の研摩面を軽
くケミカルエツチングする。KOHではシリコン酸化膜
4をエツチングせずに、シリコンウェハ1の露出面つま
り研摩面のみを軽くライトエツチングするだけとなるか
ら、研摩面の表面の自然酸化膜6は除去される(第1図
(C)参照)。しかし、KOHはアルカリ系であるがら
に+イオンによる研摩面のパシベーション汚染が考えら
れるためエツチングした研摩面を次のように清浄化させ
る。それは、まず超純水などで仮水洗(10〜15秒程
度)し、続いて酢酸などの薄い酸系の薬液でシリコンウ
ェハ1を洗浄してから、超純水中に浸漬して超音波をか
ける超音波水洗を20分間程度行う。First, the KOH placed in the etching tank was heated at about 4d~60℃.
The polished surface of the silicon wafer 1 is lightly chemically etched by keeping the temperature at a constant temperature and immersing the silicon wafer 1 therein for about 1 to 3 minutes. In KOH, only the exposed surface of the silicon wafer 1, that is, the polished surface, is lightly etched without etching the silicon oxide film 4, so the natural oxide film 6 on the surface of the polished surface is removed (see FIG. 1). See C). However, although KOH is an alkaline type, there is a possibility of passivation contamination of the polished surface due to + ions, so the etched polished surface is cleaned as follows. First, the silicon wafer 1 is temporarily rinsed with ultrapure water (about 10 to 15 seconds), then cleaned with a dilute acidic chemical such as acetic acid, and then immersed in ultrapure water and subjected to ultrasonic waves. Perform ultrasonic water washing for about 20 minutes.
次に、いわゆるアセトンディップでの遠心乾燥を行って
から、シリコンウェハ1の研摩面に所望の裏電極層7を
適宜な電極蒸着法で形成する(第1図(d)参照)。こ
の裏電極層7は多層構造が多く用いられる傾向にあるの
で、ここでは例えばCr−N i −A g構造にして
いる。Next, after performing centrifugal drying using so-called acetone dipping, a desired back electrode layer 7 is formed on the polished surface of the silicon wafer 1 by an appropriate electrode deposition method (see FIG. 1(d)). Since this back electrode layer 7 tends to have a multilayer structure, for example, it has a Cr-Ni-Ag structure here.
ところで、上記実施例でのダイオードおよび従来のそれ
における各裏電極層のCr膜厚と順方向電圧の関係を第
2図に示している。同図から判るように、本発明の実施
例によるダイオードのほうが従来のそれよりもオーミッ
ク性が改善されていることが確認されている。Incidentally, FIG. 2 shows the relationship between the Cr film thickness of each back electrode layer and the forward voltage in the diode in the above embodiment and in the conventional diode. As can be seen from the figure, it has been confirmed that the diode according to the embodiment of the present invention has improved ohmic properties compared to the conventional diode.
光匪度処果
本発明では、HF系で処理する場合のように電極層を形
成すべき部分以外(シリコンウェハの露出部分以外)を
レジストなどで覆うといった煩わしい作業を追加する必
要のない簡単かつ有効な作業でもって、電極層を蒸着す
べき部分を良好に処理できるから、この部分に蒸着させ
る電極層はシリコンウェハに対してオーミック特性が良
好になると共に密着強度を高くできる。The present invention provides a simple and easy processing method that does not require the additional troublesome work of covering areas other than the areas where electrode layers are to be formed (other than the exposed areas of the silicon wafer) with resist, as in the case of processing using an HF system. Since the area on which the electrode layer is to be deposited can be treated well with effective operations, the electrode layer deposited on this area can have good ohmic characteristics and high adhesion strength to the silicon wafer.
第1図(a)〜(dlは本発明の一実施例を説明するた
めの工程図、第2図は本発明を適用したダイオードおよ
び従来のそれの裏電極層のCr膜厚と順方向電圧の関係
を示す図である。
1・・・シリコンウェハ
5・・・表電極層
7・・・裏電極層。
特許出願人 ローム株式会社
代理人 弁理士 大 西 孝 治
第1図Figures 1(a) to (dl are process diagrams for explaining one embodiment of the present invention; Figure 2 is a diode to which the present invention is applied and the Cr film thickness and forward voltage of the back electrode layer of the conventional diode) 1...Silicon wafer 5...Top electrode layer 7...Back electrode layer. Patent applicant: ROHM Co., Ltd. Agent, patent attorney Takaharu Ohnishi Figure 1
Claims (1)
りケミカルエッチングしてから仮水洗し、このシリコン
ウェハの前記エッチング部分を酸系の薬液でもって中和
処理させて超音波水洗させた後、そこに所望の電極層を
蒸着させることを特徴とする半導体装置の製造方法。(1) The silicon wafer on which the electrode layer is to be deposited is chemically etched with KOH and then temporarily washed with water, and the etched portion of the silicon wafer is neutralized with an acid-based chemical and washed with ultrasonic water. 1. A method for manufacturing a semiconductor device, comprising depositing a desired electrode layer on a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61014398A JPH0654767B2 (en) | 1986-01-24 | 1986-01-24 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61014398A JPH0654767B2 (en) | 1986-01-24 | 1986-01-24 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62172720A true JPS62172720A (en) | 1987-07-29 |
JPH0654767B2 JPH0654767B2 (en) | 1994-07-20 |
Family
ID=11859939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61014398A Expired - Fee Related JPH0654767B2 (en) | 1986-01-24 | 1986-01-24 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0654767B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000243736A (en) * | 1999-02-18 | 2000-09-08 | Mitsubishi Materials Silicon Corp | Rinsing method of semiconductor wafer |
JP2000243737A (en) * | 1999-02-18 | 2000-09-08 | Mitsubishi Materials Silicon Corp | Rinsing liquid for semiconductor wafer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5633836A (en) * | 1979-08-29 | 1981-04-04 | Fujitsu Ltd | Patterning method of gaas thermal oxide film |
JPS6091627A (en) * | 1983-09-26 | 1985-05-23 | エクソン リサーチ アンド エンジニアリング カンパニー | Method of producing pin semiconductor device |
JPS60247928A (en) * | 1984-05-23 | 1985-12-07 | Seiko Instr & Electronics Ltd | Cleaning method of semiconductor substrate |
-
1986
- 1986-01-24 JP JP61014398A patent/JPH0654767B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5633836A (en) * | 1979-08-29 | 1981-04-04 | Fujitsu Ltd | Patterning method of gaas thermal oxide film |
JPS6091627A (en) * | 1983-09-26 | 1985-05-23 | エクソン リサーチ アンド エンジニアリング カンパニー | Method of producing pin semiconductor device |
JPS60247928A (en) * | 1984-05-23 | 1985-12-07 | Seiko Instr & Electronics Ltd | Cleaning method of semiconductor substrate |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000243736A (en) * | 1999-02-18 | 2000-09-08 | Mitsubishi Materials Silicon Corp | Rinsing method of semiconductor wafer |
JP2000243737A (en) * | 1999-02-18 | 2000-09-08 | Mitsubishi Materials Silicon Corp | Rinsing liquid for semiconductor wafer |
Also Published As
Publication number | Publication date |
---|---|
JPH0654767B2 (en) | 1994-07-20 |
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Legal Events
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LAPS | Cancellation because of no payment of annual fees |