JPS62171211A - Hybrid power amplifier - Google Patents
Hybrid power amplifierInfo
- Publication number
- JPS62171211A JPS62171211A JP1258086A JP1258086A JPS62171211A JP S62171211 A JPS62171211 A JP S62171211A JP 1258086 A JP1258086 A JP 1258086A JP 1258086 A JP1258086 A JP 1258086A JP S62171211 A JPS62171211 A JP S62171211A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- monolithic
- voltage
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims description 30
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 30
- 238000010586 diagram Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高出力電力増幅器をモノリシックＩＣで構成
する混成電力増幅装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hybrid power amplifier device in which a high output power amplifier is constructed from a monolithic IC.
従来の技術
近年、混成電力増幅装置は、音響用増幅器などに多く利
用さｎるようになってきた。BACKGROUND OF THE INVENTION In recent years, hybrid power amplifiers have come into widespread use in acoustic amplifiers and the like.
以下図面を参照しながら、上述した従来の混成電力増幅
装置の一例について説明する。An example of the above-mentioned conventional hybrid power amplifier will be described below with reference to the drawings.
第４図、第６図は従来の混成電力増幅装置の基本構成図
であり、第４図において１ｉｌ−ｔ、モノリシックＩＣ
電圧増幅部入力端、２はモノリシックＩＣ電圧増幅部、
３は出力電力増幅部、４は出力電力増幅部出力端、６は
最高電位電源端である。4 and 6 are basic configuration diagrams of conventional hybrid power amplifiers.
Voltage amplification section input terminal, 2 is monolithic IC voltage amplification section,
3 is an output power amplification section, 4 is an output terminal of the output power amplification section, and 6 is a highest potential power supply terminal.
第６図は、正負両極性の電源を使用する場合の基本構成
図であり、第５図において、１はモノリシックＩＣ電圧
増幅部入力端、２はモノリシックＩＣ電圧増幅部、３は
出力電力増幅部部、４は出力電力増幅部出力端、６は最
高電位電源端、９は最低電位電源端である。FIG. 6 is a basic configuration diagram when using a power supply with both positive and negative polarities. In FIG. 5, 1 is the monolithic IC voltage amplifier input terminal, 2 is the monolithic IC voltage amplifier section, and 3 is the output power amplifier section. 4 is the output end of the output power amplification section, 6 is the highest potential power source end, and 9 is the lowest potential power source end.
以上のように構成された混成電力増幅装置について、以
下その動作について説明する。The operation of the hybrid power amplifier configured as described above will be described below.
まず、モノリシックＩＣ電圧増幅部入力端１に信号が印
加さ扛ると、モノリシックＩＣ電圧増幅部２で電圧増幅
さｎる。その次に出力電力増幅部３でインピーダンス変
換さｎ１所定の出力電流を獲得することができる。この
場合、最大出方電力は最高電位電源端６の電源電圧に依
存することになる。第５図の場合、最高電位電源端６の
電圧と、最低電位電源端９の電圧が最大出力電力を決定
する０
発明が解決しようとする問題点
しかしながら上記のような構成では、最高電位電源端お
よび最低電位電源端の最大電圧は、モノリシックＩＣの
最大電源電圧定格の範囲内に設定しなけｎばならない。First, when a signal is applied to the monolithic IC voltage amplifying section input terminal 1, the voltage is amplified by the monolithic IC voltage amplifying section 2. Next, the output power amplifying section 3 performs impedance conversion and a predetermined output current n1 can be obtained. In this case, the maximum output power depends on the power supply voltage of the highest potential power supply terminal 6. In the case of FIG. 5, the voltage at the highest potential power supply terminal 6 and the voltage at the lowest potential power supply terminal 9 determine the maximum output power. And the maximum voltage at the lowest potential power supply terminal must be set within the maximum power supply voltage rating of the monolithic IC.
一般に出力電力増幅部へ供給する電源電圧は変成器より
取り出した整流電圧である。このため出力電力増幅部が
出力電力増幅部出力端から負荷に供給さ牡る電力が最大
のとき、電源電圧が最低であり、無負荷時には最大にな
る。Generally, the power supply voltage supplied to the output power amplification section is a rectified voltage extracted from a transformer. Therefore, when the output power amplifying section supplies the maximum power to the load from the output terminal of the output power amplifying section, the power supply voltage is the lowest, and when there is no load, it is the highest.
したがって最大出力電力は、モノリシックＩＣの最大電
源電圧定格から、電圧損失を差し引いた電源電圧で決定
さｎることになる。モノリシックＩＣの耐圧は、プロセ
スで決定さｒ１高耐圧化はプロセスコストが増大し、チ
ップサイズも大きくなる。そのため最大出力電力を大き
くするには、高いコストが要求されるという開明があっ
た。Therefore, the maximum output power is determined by the power supply voltage obtained by subtracting the voltage loss from the maximum power supply voltage rating of the monolithic IC. The breakdown voltage of a monolithic IC is determined by the process, and increasing the breakdown voltage increases the process cost and increases the chip size. Therefore, it has been discovered that increasing the maximum output power requires high costs.
本発明は上記問題点に鑑み、モノリシックＩＣの最大電
源電圧定格で最大出力電力を達成する電力増幅装置を提
供するものである。In view of the above problems, the present invention provides a power amplification device that achieves maximum output power at the maximum power supply voltage rating of a monolithic IC.
問題点を解決するだめの手段
上記問題点を解決するために本発明の混成電力増幅装置
は、モノリシックＩＣ電圧増幅部と、出力電力増幅部と
、上記モノリシックＩＣの最大電源電圧定格の範囲に電
源電圧を制限する電源電圧制限部という構成を備えたも
のである。Means for Solving the Problems In order to solve the above problems, the hybrid power amplifier of the present invention includes a monolithic IC voltage amplification section, an output power amplification section, and a power supply within the maximum power supply voltage rating of the monolithic IC. This device includes a power supply voltage limiting section that limits the voltage.
作 用
本発明は上記した構成によって、無負荷のときには、電
源電圧制限部はモノリシックＩＣの最大電源電圧定格の
範囲に電源電圧を制限するように働く。また最大出力電
力時には、電源電圧制限部−、は電源電圧を低損失でモ
ノリシ
ックＩＣに供給するように働く。このように動作させる
ことにより、最大出力電力全モノリシックＩＣの最大電
源電圧定格近くで達成できるようになる。Operation In the present invention, with the above-described configuration, when there is no load, the power supply voltage limiting section works to limit the power supply voltage to the range of the maximum power supply voltage rating of the monolithic IC. Also, at maximum output power, the power supply voltage limiter operates to supply the power supply voltage to the monolithic IC with low loss. Operating in this manner allows maximum output power to be achieved near the maximum power supply voltage rating of the entire monolithic IC.
実施例
以下本発明の一実施例の混成電力増幅装置について、図
面を参照しながら説明する。Embodiment Hereinafter, a hybrid power amplifier according to an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例における混成電力増幅装
置の基本構成図を示すものである。第１図において、１
′ｒＪ、、モノリシックＩＣ電圧増幅部入力端、２はモ
ノリシックＩＣ電圧増幅部、３は出力電力増幅部、４は
出力電力増幅部出力端、５は電源電圧制限部、６は最高
電位電源端、７は電源電圧制限部出力端である。FIG. 1 shows a basic configuration diagram of a hybrid power amplifier according to a first embodiment of the present invention. In Figure 1, 1
'rJ, monolithic IC voltage amplification section input terminal, 2 is monolithic IC voltage amplification section, 3 is output power amplification section, 4 is output power amplification section output terminal, 5 is power supply voltage limiting section, 6 is highest potential power supply terminal, 7 is an output terminal of the power supply voltage limiting section.
以上のように構成さｎた混成電力増幅装置について、以
下第１図をもちいてその動作を説明する。The operation of the hybrid power amplifier configured as described above will be explained below with reference to FIG.
まず、モノリシックＩＣ電圧入力端１に信号が印加さ扛
ると、モノリシ、りＩＣＣ電圧幅幅部２電圧増幅さｎる
。その次に出力電力増幅部３で・インピーダンス変換さ
れ、所定の出力電流を獲得することができる。最大出力
電力は電源電圧制限部上カフｉ！７から供給さｎる電源
電圧で決まる。この電源電圧をモノリシックＩＣ電圧増
幅部２の最大電源電圧定格範囲内に設定するように電源
電圧制限部５を構成すｎば、最大電力をモノリシックＩ
Ｃの最大電源電圧定格付近まで高めることができる０
以上のように本実施例によｎば、モノリシックＩＣ電圧
増幅部の電源電圧を、電源電圧制限部の出力端から供給
することにより、最大電力をモノＩＪ ７・り１０の−
′−・ ９最大電源電圧定格付近まで高めるこ
とができる。First, when a signal is applied to the monolithic IC voltage input terminal 1, the monolithic IC amplifies the voltage at the ICC voltage width section 2. Then, the output power amplification section 3 performs impedance conversion, and a predetermined output current can be obtained. The maximum output power is the power supply voltage limiter upper cuff i! It is determined by the power supply voltage supplied from 7 to 7. By configuring the power supply voltage limiting section 5 to set this power supply voltage within the maximum power supply voltage rating range of the monolithic IC voltage amplifying section 2, the maximum power
As described above, according to this embodiment, by supplying the power supply voltage of the monolithic IC voltage amplifying section from the output terminal of the power supply voltage limiting section, the maximum power Mono IJ 7・ri10-
'-・9 Can be raised to around the maximum power supply voltage rating.
以下本発明の第２の実施例について図面を参照しながら
説明する。A second embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の第２の実施例を示す混成電力増幅装置
の基本構成図である。FIG. 2 is a basic configuration diagram of a hybrid power amplifier device showing a second embodiment of the present invention.
同図において、１はモノリシックＩＣ電圧増幅入力端、
２はモノリシックＩＣ電圧増幅部、３は出力電力増幅部
、４は出力電力増幅部出力端、５は第１の電源電圧制限
部、６は最高電位電源端、７は第１の電源電圧制限部や
出力端、で以上は第する。８は第２の電源電圧制限部、
９は最低電位電源端、１ｏは第２の電源電圧制限部出力
端である。In the figure, 1 is a monolithic IC voltage amplification input terminal;
2 is a monolithic IC voltage amplification section, 3 is an output power amplification section, 4 is an output terminal of the output power amplification section, 5 is a first power supply voltage limiting section, 6 is a highest potential power supply terminal, and 7 is a first power supply voltage limiting section. or the output end, the above is the first one. 8 is a second power supply voltage limiting section;
9 is the lowest potential power supply terminal, and 1o is the output terminal of the second power supply voltage limiting section.
上記のように構成さｎた混成電力増幅装置について、以
下その動作を説明する。まず、モノリシックＩＣ電圧入
力端１に信号が印加されると、モノリシックＩＣ電圧増
幅部２で電圧増幅さ扛る。The operation of the hybrid power amplifier configured as described above will be described below. First, when a signal is applied to the monolithic IC voltage input terminal 1, the voltage is amplified by the monolithic IC voltage amplifying section 2.
その次に出力電力増幅部３でインピーダンス変換さｎ、
所定の出力電流を獲得することができる。Then, the output power amplification section 3 performs impedance conversion n,
A predetermined output current can be obtained.
最大出力電力は第１の電源電圧制限部出力端７の電圧と
、第２の電源電圧制限部出力端１Ｑの電圧とで決まる。The maximum output power is determined by the voltage at the first power supply voltage limiting section output terminal 7 and the voltage at the second power supply voltage limiting section output terminal 1Q.
この電源電圧をモノリシックＩＣ電圧増幅部２の最大電
源電圧定格範囲内に設定するように、第１の電源電圧制
限部６と第２の電源電圧制限部８を構成すｎば、最大電
力をモノリシックＩＣの最大電源電圧定格付近まで高め
ることができる。By configuring the first power supply voltage limiting section 6 and the second power supply voltage limiting section 8 so as to set this power supply voltage within the maximum power supply voltage rating range of the monolithic IC voltage amplification section 2, the maximum power It is possible to increase the voltage to near the maximum power supply voltage rating of the IC.
以上のように、第２の電源電圧制限部を設けて最低電位
も制限することにより、グランド電位に対して両極性の
混成電力増幅装置に対しても、最大電力をモノリシック
ＩＣの最大電源電圧定格付近まで高めることができる。As described above, by providing the second power supply voltage limiting section and also limiting the lowest potential, the maximum power can be adjusted to the maximum power supply voltage rating of the monolithic IC, even for a hybrid power amplifier device having polarity with respect to the ground potential. It can be raised to near.
以下本発明の電源電圧制限部の一実施例について図面を
参照しながら説明する。An embodiment of the power supply voltage limiting section of the present invention will be described below with reference to the drawings.
第３図は本発明の電源電圧制限部の第１の実施例におけ
る回路構成図である。FIG. 3 is a circuit diagram of a first embodiment of the power supply voltage limiting section of the present invention.
同図において、６は最高電位電源端、７は電源電圧制限
部出力端、１１は基準電位を作るツェナーダイオード、
１２はツェナーダイオード電流を設定する抵抗、１３は
基準電位を増幅するトランジスタ、１４は電源電圧制御
トランジスタ、１６は発振防止用コンデンサ、１６．１
７は電源電圧設定用抵抗である。In the figure, 6 is the highest potential power supply terminal, 7 is the output terminal of the power supply voltage limiter, 11 is a Zener diode that creates a reference potential,
12 is a resistor for setting the Zener diode current, 13 is a transistor for amplifying the reference potential, 14 is a power supply voltage control transistor, 16 is a capacitor for preventing oscillation, 16.1
7 is a power supply voltage setting resistor.
上記のように構成さｎた電源電圧制限部について、以下
その動作を説明する。The operation of the power supply voltage limiting section configured as described above will be described below.
まず、電源電圧制限部出力端７の電圧は、基準電位を作
るツェナーダイオード１１と、基準電位を増幅するトラ
ンジスタ１３と、電源電圧設定用抵抗１６．１７で設定
さｎる。この電圧をそノリシックＩＣの最大電源電圧定
格の範囲内に設定す扛ば、最大出力電力時、最高電位電
源端６の電位は、電源電圧制御トランジスタ１４のコレ
クタ・エミッタ飽和電圧の損失を通じて、電源電圧制限
部出力端７に伝達さｎるので、はとんどモノリシックＩ
Ｃの最大電源電圧定格付近の電圧がモノリシックＩＣに
供給さｎることになる。また無負荷時には最高電位電源
端６の電位は、モノＩＪンノクＩＣの最大電源電圧定格
を越えるが、電源電圧制御トランジスタ１４がその電圧
を吸収し、電源電圧制限部出力端７にはモノリシックＩ
Ｃの最大電源電圧定格の範囲内の電圧が設定される。First, the voltage at the output terminal 7 of the power supply voltage limiting section is set by the Zener diode 11 that creates a reference potential, the transistor 13 that amplifies the reference potential, and the power supply voltage setting resistors 16 and 17. If this voltage is set within the range of the maximum power supply voltage rating of the nolithic IC, the potential of the highest potential power supply terminal 6 at the maximum output power will be reduced through the collector-emitter saturation voltage loss of the power supply voltage control transistor 14. Since the voltage is transmitted to the output terminal 7 of the voltage limiter, the monolithic I
A voltage near the maximum power supply voltage rating of C will be supplied to the monolithic IC. In addition, when there is no load, the potential of the highest potential power supply end 6 exceeds the maximum power supply voltage rating of the mono IJN IC, but the power supply voltage control transistor 14 absorbs this voltage, and the power supply voltage limiter output end 7 is connected to the monolithic IJ.
A voltage within the maximum power supply voltage rating of C is set.
発明の効果
以上のように本発明は、モノリシックＩＣ電圧増幅部と
、出力電力増幅部と、モノリシックＩＣの最大電源電圧
定格の範囲に電源電圧を制限する電源電圧制限部とを設
けることにより、モノリシックＩＣの最大電源電圧定格
付近の電圧できまる出力電力全発生させることができ、
モノリシックＩＣのローコスト性と、最大出力電力の拡
大という付加価値を生みだすことができる。Effects of the Invention As described above, the present invention provides a monolithic IC voltage amplification section, an output power amplification section, and a power supply voltage limiting section that limits the power supply voltage within the range of the maximum power supply voltage rating of the monolithic IC. The full output power can be generated at a voltage close to the maximum power supply voltage rating of the IC,
It is possible to create the added value of the low cost of monolithic ICs and the expansion of maximum output power.
第１図は本発明の第１の実施例における混成電力増幅装
置の基本構成図、第２１図は本発明の第２の実施例にお
ける混成電力増幅装置の基本構成図、第３図は第１図お
よび第２図の電源電圧制限部の第１の実施例における回
路構成図、第４図は従来の混成電力増幅装置の基本構成
図、第５図は正負両極性の電源を使用する場合の従来の
混成電力増幅装置の基本構成図である。
１・・・・・・モノリシックＩＣ電圧増幅部入力端、２
・・・・モノリシックＩＣ電圧増幅部、３・・・・・・
出力電力増幅部、４・・・・・・出力電力増幅部出力端
、６・・・・・・第１の電源電圧制限部、６・・・・・
最高電位電源端、７・・・・・・第１の電源電圧制限部
出力端、８・・・・・・第２の電源電圧制限部、９・・
・・・・最低電位電源端、１゜・・・・・第２の電源電
圧制限部出力端、１１・・・・・・ツェナーダイオード
、１２・・・・・・抵抗、１３・・・・・・ＮＰＮトラ
ノジスタ、１４・・・・・・ＰＮＰ ）う／ジスタ、１
５・・・・・コンデンサ、１６・・・・・・抵抗、１７
・・・・・抵抗。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
ｌｌｌ５Ｚ図
第３図
第４図FIG. 1 is a basic configuration diagram of a hybrid power amplifier according to a first embodiment of the present invention, FIG. 21 is a basic configuration diagram of a hybrid power amplifier according to a second embodiment of the present invention, and FIG. 4 is a basic configuration diagram of a conventional hybrid power amplifier, and FIG. 5 is a circuit configuration diagram of the first embodiment of the power supply voltage limiting section shown in FIGS. 1 is a basic configuration diagram of a conventional hybrid power amplifier device. 1... Monolithic IC voltage amplification section input terminal, 2
...Monolithic IC voltage amplification section, 3...
Output power amplification section, 4... Output power amplification section output end, 6... First power supply voltage limiting section, 6...
Highest potential power supply terminal, 7...First power supply voltage limiting section output terminal, 8...Second power supply voltage limiting section, 9...
...Lowest potential power supply terminal, 1°...Second power supply voltage limiter output terminal, 11...Zener diode, 12...Resistor, 13...・・NPN tranosista, 14・・・・・・PNP ) u/jista, 1
5... Capacitor, 16... Resistor, 17
·····resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figurell5ZFigure 3Figure 4
Claims (2)
と、上記モノリシックＩＣの最大電源電圧定格の範囲に
電源電圧を制限する電源電圧制限部とを備えたことを特
徴とする混成電力増幅装置。(1) A hybrid power amplification device comprising a monolithic IC voltage amplification section, an output power amplification section, and a power supply voltage limiting section that limits the power supply voltage to a range of the maximum power supply voltage rating of the monolithic IC.
源電圧制限部と、最低電位を制限する第２の電源電圧制
限部を備えたことを特徴とする特許請求の範囲第１項記
載の混成電力増幅装置。(2) Claim 1, characterized in that the power supply voltage limiter includes a first power supply voltage limiter that limits the highest potential and a second power supply voltage limiter that limits the lowest potential. The hybrid power amplification device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012580A JP2594258B2 (en) | 1986-01-23 | 1986-01-23 | Hybrid power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012580A JP2594258B2 (en) | 1986-01-23 | 1986-01-23 | Hybrid power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62171211A true JPS62171211A (en) | 1987-07-28 |
| JP2594258B2 JP2594258B2 (en) | 1997-03-26 |
Family
ID=11809291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61012580A Expired - Lifetime JP2594258B2 (en) | 1986-01-23 | 1986-01-23 | Hybrid power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2594258B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007249384A (en) * | 2006-03-14 | 2007-09-27 | Ricoh Co Ltd | Semiconductor device |
| JP2012016574A (en) * | 2010-06-07 | 2012-01-26 | Toshiba Corp | Magnetic resonance imaging apparatus |
| JP2013093666A (en) * | 2011-10-24 | 2013-05-16 | Rohm Co Ltd | Audio signal processing circuit and electronic apparatus using the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5995706A (en) * | 1982-11-24 | 1984-06-01 | Nippon Gakki Seizo Kk | Amplifier |
| JPS59208710A (en) * | 1983-05-07 | 1984-11-27 | マシイネンフアブリーク・ラインハウゼン・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング | Contacor for load tap selector of on-load tap changing transformer |
| JPS60219803A (en) * | 1984-04-16 | 1985-11-02 | Fuji Electric Co Ltd | Operational amplifier |
-
1986
- 1986-01-23 JP JP61012580A patent/JP2594258B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5995706A (en) * | 1982-11-24 | 1984-06-01 | Nippon Gakki Seizo Kk | Amplifier |
| JPS59208710A (en) * | 1983-05-07 | 1984-11-27 | マシイネンフアブリーク・ラインハウゼン・ゲゼルシヤフト・ミト・ベシユレンクテル・ハフツング | Contacor for load tap selector of on-load tap changing transformer |
| JPS60219803A (en) * | 1984-04-16 | 1985-11-02 | Fuji Electric Co Ltd | Operational amplifier |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007249384A (en) * | 2006-03-14 | 2007-09-27 | Ricoh Co Ltd | Semiconductor device |
| JP2012016574A (en) * | 2010-06-07 | 2012-01-26 | Toshiba Corp | Magnetic resonance imaging apparatus |
| JP2013093666A (en) * | 2011-10-24 | 2013-05-16 | Rohm Co Ltd | Audio signal processing circuit and electronic apparatus using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2594258B2 (en) | 1997-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04111506A (en) | Amplifying circuit | |
| JPS62171211A (en) | Hybrid power amplifier | |
| US3417339A (en) | Push-pull transistor amplifiers with transformer coupled driver | |
| JP2566786Y2 (en) | Power supply load circuit | |
| JPS59224905A (en) | Amplifier circuit | |
| JP2725290B2 (en) | Power amplifier circuit | |
| JP3062164B2 (en) | Semiconductor output circuit and idling current control method | |
| JPS6192171A (en) | Converter output circuit | |
| JPS62261207A (en) | Agc circuit | |
| JPH0117847Y2 (en) | ||
| JPH0724807Y2 (en) | DC amplifier circuit | |
| JPH06303043A (en) | Amplifier circuit | |
| JPS6029226Y2 (en) | amplifier circuit | |
| JP2586075Y2 (en) | Optically coupled insulation amplifier | |
| JPS61167338A (en) | Rapid discharge circuit | |
| KR900006020Y1 (en) | Power stabilization circuit of a speaker | |
| JPH03115415U (en) | ||
| JPS6333367Y2 (en) | ||
| JPS6314489Y2 (en) | ||
| JPS62225014A (en) | Push-pull amplifier | |
| JPH0357616U (en) | ||
| JPH02109110A (en) | Constant voltage protector | |
| JPS5950115U (en) | Protection circuit for switching type amplifier | |
| JPS58133822U (en) | transistor protection circuit | |
| JPS62165128A (en) | Current and voltage converting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |