JPS62171064A - Buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of the overflow or the empty condition of a data buffer and to shorten a data bus exclusive time by providing a transferring error detecting part, a number of transferring setting part, etc., and changing the set value of the number of data which can be transferred once. CONSTITUTION:When a data buffer 2 is full and an empty signal 10 is vanished, data are removed from the buffer 2 in accordance with a buffer requesting signal 19. In such a case, before the signal 19 is sent to the buffer 2 and an error detecting part 6, the data are outputted from a memory 1, a data transmitting signal 13 is not sent through a buffer transferring control part 3 to the detecting part 6, then, the detecting part 6 detects a transfer error. Thus, the detecting part 6 sends a setting number changing signal 21 to a transferring number setting part 5 and the setting part 5 increases a set value 14 and therefore, the maximum value of the number of data which can be transferred once is increased. When other transfer error signal 20 is sent to the detecting part 6, the value 14 is decreased, the maximum value of the number of the data, which can be transferred once, is decreased, the overflow of the buffer 2 or the empty condition will not occur and the data bus private time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application: 1] The present invention relates to a bus circuit, and particularly to a bus bus circuit that transfers data via a shared data bus.

[Conventional technology]

Conventionally, when transferring data directly from memory using a data bus, the number of data within the range of the setting value determined by the transfer number setting section was to be transferred at one time. The set number could not be changed depending on the usage status of the data bus while the unit was in operation.

[Problems to be solved by the invention] The conventional sofa circuit described above transfers the number of data within the range set by the transfer number setting section, but the transfer number setting section remains unchanged during operation. Therefore, when the degree of occupancy of the data bus changes fluidly, the data bus sofa becomes overflowing or empty. In addition, if the number of data transferred at one time is reduced, the time for exclusive use of the data bus becomes longer, which poses the problem of affecting the operation of the circuits that share the data bus.

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer circuit that can shorten the exclusive use time of a data bus without overflowing or emptying the data buffer.

[Means for solving problems]

The buffer circuit of the present invention includes a data buffer that receives and temporarily stores data read from a memory via a data bus, and a transfer number counter that counts the number of data sent to the data buffer during one transfer period. a transfer error detection unit that detects a transfer error in data transfer to the data buffer and outputs a set number change signal; and a transfer error detection unit that detects a transfer error in data transfer to the data buffer and outputs a set number change signal; a transfer number setting section for changing the number of transfers; and a buffer transfer control section for changing the number of data transfers during one transfer period in accordance with an empty state of the data buffer and a value set by the transfer number setting section. It consists of:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, memory 1 is a part that stores data, and data buffer T2 is a part that temporarily stores data from memory 1. The buffer transfer control unit 3 controls data transfer between the memory 1 and the data server 2.

The transfer number counting section 4 counts the number of data transferred during one data transfer period, and when the counted value matches the transfer data number setting value 14 set in the transfer number setting section 5, a count match signal is sent. 15 to the sofa transfer control unit 3.

The transfer error detection unit 6 detects a buffer empty signal 16°, a data transmission signal 17. When a transfer error is detected by the data request signal 18 and the buffer data request signal 19, and when the other transfer error signal 20 is input, a setting number change signal 21 is sent to the transfer number setting section 5, and the transfer number setting section 5: When the set number change signal 21 is input, the set value 14 is changed.

When data is transferred from the memory 1 to the data buffer 2, when the buffer empty signal 10 indicating that the data buffer 2 is empty is supplied from the data buffer 2 to the buffer transfer control unit 31, the buffer transfer control unit 3 Buffer empty signal 1
0 into a data request signal 12 and send it to the memory 1. Upon receiving the data request signal 12, the memory 1 sends the data to the data bus 7, and sends a data transmission 1 code 13 to the bus transfer control section 3 and transfer number counting section 4. Having received the data transmission signal 13, the buffer transfer control unit 3 sends a buffer load signal 11 to the data buffer 2, and the data buffer 2 takes in the data via the input data line 8.

On the other hand, upon receiving the data transmission signal 13, the transfer number counting section 4 counts the data transmission signal 13 and compares the counting result with the set value 14 from the transfer number setting section 5.

The transfer number counting section 4 sends a count coincidence signal 15 to the sofa transfer control section 3 when the counted value of the data transmission signal 13 and the set value 14 match.

The transfer controller 3 sends the data request signal 2 until the count match signal 15 from the transfer number counter 4 arrives or the bus empty signal 10 from the data bus sofa 2 disappears. Memory 11\Continue sending.

Memory 1 is connected to data bus 7 while data request signal 12 is present.
The data transmission signal 13 is sent to the buffer transfer control section 3 and the transfer number counting section 4.

When the data bar sofa 2 is full and the bar sofa empty signal 10 has disappeared, data is taken out from the data bar sofa 2 via the output data line 9 in response to the bar sofa request signal 19, and the data bar is returned to the bar state again. Sofa vacant signal 10 is bar.
The data is sent to the sofa transfer control unit 3, and the above-described operation is repeated.

When the data bar 2 is in an empty state, the buffer empty signal 10 is sent to the buffer transfer control unit 3, and the buffer transfer control unit 3 sends the memory 11\data request signal 12.
The transfer error detection unit 61 sends the sofa empty signal 16 and the data request signal 18.

BA/SOFA data request signal 19 is data BA/NOFA 2
And before being sent to the transfer error detection section 6, the data from the memory 1 is put on the data bus 71\, and the data transmission signal 13 from the memory 1 is passed through the bus transfer control section 3 as the data transmission signal 17 to detect a transfer error. When the detection unit 61\ is not sent, the transfer error detection unit 6 detects a transfer error and sends a set number change signal 21 to the transfer number setting unit 5, and the transfer number setting unit 5 increases the set value 14. This increases the maximum number of data that can be transferred at one time.

When the transfer error signal 20 is sent to the transfer error detection section 6, the transfer error detection section sends a setting number change signal 2] to the transfer number setting section 5, and the transfer number setting section 5 decreases the setting value 14. , the maximum number of data that can be transferred at one time is reduced.

I. Effects of the Invention] As explained above, the bus sofa circuit of the present invention is a buffer circuit that shares a data bus for transferring data, and the buffer circuit can refer to the usage state of the data buffer and the result of counting the number of data transfers. By doing this, you can change the setting value for the number of data that can be transferred at one time, so you can prevent the data bus from overflowing or becoming empty, and reduce the exclusive time of the data bus. This has the effect of improving the utilization efficiency of 7).

[Brief explanation of drawings]

1st ``4'' is a professional diagram of an embodiment of the present invention. ■...Memory, 2...Database...Sofa, 3...
BA sofa transfer control unit, 1...transfer number counting unit, 5.
... Transfer number setting section, b... Transfer error detection section, 7...
data bus, 8...input data line, 9...output data line, 10...Ha/lfa empty signal, 11...
...Ba... Sofa load signal, ]2... Data request signal, 13... Data transmission signal, 14... Setting value, 15
...Counting τ signal, 1()...Ba sofa empty signal,
17...Data transmission signal, 18...Data request signal, 19...Bath data request signal, 20...Position transfer error signal, 21...Setting number change signal.

Claims (1)

[Claims] a data buffer that receives and temporarily stores data read from memory via a data bus; a transfer number counter that counts the number of data sent to the data buffer during one transfer period; a transfer error detection unit that detects a transfer error in the data transfer and outputs a set number change signal; and a transfer number setting unit that changes the number of data that can be transferred during one transfer period when the set number change signal is input. , a buffer transfer control unit that changes the number of data transfers during one transfer period in accordance with the empty state of the data buffer and the value set by the transfer number setting unit. circuit.