JPS62165971A - Dynamic type semiconductor memory device - Google Patents

Dynamic type semiconductor memory device

Info

Publication number
JPS62165971A
JPS62165971A JP61008575A JP857586A JPS62165971A JP S62165971 A JPS62165971 A JP S62165971A JP 61008575 A JP61008575 A JP 61008575A JP 857586 A JP857586 A JP 857586A JP S62165971 A JPS62165971 A JP S62165971A
Authority
JP
Japan
Prior art keywords
layer
formed
layers
cell
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61008575A
Inventor
Daisuke Azuma
Yoshiji Oota
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP61008575A priority Critical patent/JPS62165971A/en
Publication of JPS62165971A publication Critical patent/JPS62165971A/en
Priority claimed from US07/267,679 external-priority patent/US4888631A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells

Abstract

PURPOSE:To obtain the capacity of a cell capacitor of a memory cell and to reduce the area of a three-dimensional semiconductor device by composing the semiconductor device in a laminated structure of a plurality of active layers, and connecting the layers via through holes perpendicularly. CONSTITUTION:A first layer single active layer 1 is formed on a single crystal Si substrate. A second layer single active layer 2 is obtained by melting and growing a polycrystalline silicon by emitting a beam to the top of an insulating layer for insulating the layer 1. An MOS transistor Ti of the same channel is formed on the layers 1, 2. An NMOSTr 3 is, for example, formed on the layer 1, and a PMOSTr 6 is formed on the layer 2. Here, the memory cell is formed of a through hole 5 connected with the Tr 3 and a second layer cell capacitor 4, or becomes a three-dimensional structure memory cell formed of the Tr 6, the first layer cell capacitor 7 via a through hole 8. Thus, the layers 1, 2 are formed of single crystal active element regions and an element separating region for insulating the regions at an arbitrary interval to reduce the size of the cell.
JP61008575A 1986-01-17 1986-01-17 Dynamic type semiconductor memory device Pending JPS62165971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61008575A JPS62165971A (en) 1986-01-17 1986-01-17 Dynamic type semiconductor memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61008575A JPS62165971A (en) 1986-01-17 1986-01-17 Dynamic type semiconductor memory device
US07/267,679 US4888631A (en) 1986-01-17 1988-11-03 Semiconductor dynamic memory device

Publications (1)

Publication Number Publication Date
JPS62165971A true JPS62165971A (en) 1987-07-22

Family

ID=11696832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61008575A Pending JPS62165971A (en) 1986-01-17 1986-01-17 Dynamic type semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS62165971A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011129889A (en) * 2009-11-18 2011-06-30 Semiconductor Energy Lab Co Ltd Memory device
JP2015181159A (en) * 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 semiconductor device
JP2015201251A (en) * 2010-11-12 2015-11-12 株式会社半導体エネルギー研究所 semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853859A (en) * 1981-09-26 1983-03-30 Matsushita Electric Ind Co Ltd Integrated thin film element
JPS60250665A (en) * 1984-05-25 1985-12-11 Mitsubishi Electric Corp Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853859A (en) * 1981-09-26 1983-03-30 Matsushita Electric Ind Co Ltd Integrated thin film element
JPS60250665A (en) * 1984-05-25 1985-12-11 Mitsubishi Electric Corp Semiconductor memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011129889A (en) * 2009-11-18 2011-06-30 Semiconductor Energy Lab Co Ltd Memory device
JP2015201251A (en) * 2010-11-12 2015-11-12 株式会社半導体エネルギー研究所 semiconductor device
US9460772B2 (en) 2010-11-12 2016-10-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2015181159A (en) * 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 semiconductor device
US10217752B2 (en) 2014-03-07 2019-02-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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