JPS62165971A - Dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain the capacity of a cell capacitor of a memory cell and to reduce the area of a three-dimensional semiconductor device by composing the semiconductor device in a laminated structure of a plurality of active layers, and connecting the layers via through holes perpendicularly. CONSTITUTION:A first layer single active layer 1 is formed on a single crystal Si substrate. A second layer single active layer 2 is obtained by melting and growing a polycrystalline silicon by emitting a beam to the top of an insulating layer for insulating the layer 1. An MOS transistor Ti of the same channel is formed on the layers 1, 2. An NMOSTr 3 is, for example, formed on the layer 1, and a PMOSTr 6 is formed on the layer 2. Here, the memory cell is formed of a through hole 5 connected with the Tr 3 and a second layer cell capacitor 4, or becomes a three-dimensional structure memory cell formed of the Tr 6, the first layer cell capacitor 7 via a through hole 8. Thus, the layers 1, 2 are formed of single crystal active element regions and an element separating region for insulating the regions at an arbitrary interval to reduce the size of the cell.

Description

[Detailed Description of the Invention] <Industrial Field of Application> The major invention relates to a semiconductor integrated circuit device having a three-dimensional active layer stacked structure, and is directed to improving the degree of integration of the device.
The present invention relates to a semiconductor integrated circuit element having an element structure in which wiring is made three-dimensional, wiring is efficiently performed by using through holes, and the area thereof can be reduced and simplified.

<Prior art> Semiconductor memory circuit elements in general, especially dynamic RAM
has been highly integrated using microfabrication technology. The memory cells that occupy most of the area of the semiconductor integrated circuit elements of dynamic RAM also have a one-transistor/capacitor configuration, and now they are highly integrated by making full use of microfabrication technology to reduce the size of the memory cells. There is. Various efforts have been made to reduce the size of memory cells and to ensure the capacity of cell capacitors in memory cells. In order to increase the cell area of a memory cell, efforts are being made to increase the capacitance by using trench type or stacked type capacitors.

<Problem to be solved by the invention> However, if the degree of integration realized within an element increases, 1
Since the entire cell capacitor capacity of a memory cell must be secured, there is a limit to the miniaturization of memory cells, and the element area increases.As long as a certain level of microfabrication technology is used, the degree of memory integration will be proportional to the area. and will continue to increase.

In view of the above points, the present invention secures the cell capacitor capacity of the memory cell, reduces the cell area of the memory cell, and substantially reduces the number of memory cells compared to the conventional dynamic RAM memory cell having a two-dimensional structure. Multiple active layers that enable increased SOI (Silicon On In5ula
The purpose of this invention is to provide a semiconductor memory element using a memory cell having a three-dimensional structure realized by a tor) structure.

<Means for Solving the Problems> In order to achieve the above object, the semiconductor integrated circuit device of the invention includes a first active layer formed on a single crystal silicon substrate, and an electrical connection between the first active layer and the first active layer. A three-dimensional structure semiconductor element having a laminated structure of a second active layer obtained by melting and growing polycrystalline silicon by beam irradiation on the upper part of an insulating layer, wherein each active layer has an arbitrary structure within each layer. The active element region is composed of a single crystal active element region having a width of 1, and an element isolation region that insulates this region at an arbitrary interval. Further, the single crystal active element region is composed of PMOS, NMO5 or CMO5FET, and is not a conventional MO3
Semiconductor integrated circuit elements that take advantage of technology are provided, and furthermore,
The active layer is vertically connected to the upper or lower active layer by through holes, and conventional microfabrication techniques provide a high-density semiconductor integrated circuit device that is a little more advanced than the conventional dynamic RAM.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram of an embodiment of the great invention, in which memory cells of a dynamic RAM are
FIG. 2 is a conceptual diagram of a structure realized with a two-layer active layer made of FFI.

In the figure, 1 is a first single active layer formed on a single crystal silicon substrate, and 2 is a polycrystalline silicon layer formed on the top of an insulating layer that electrically insulates the first single active layer by beam irradiation. This is the second single active layer obtained by melt-growing. Each single active layer is formed with a same channel MOS transistor, ie PMO5 or NMOSI-transistor. For example, an NMOSI-transistor is formed in the first single active layer 1, and a PMO5 transistor is formed in the second single active layer 2).
Form a runcisister. Here, the memory cell is in the first layer N
MO5) Formed by the null hole 5 connecting the transistor 3 and the second layer cell capacitor 4, or by the second layer P
MO5) It is a three-dimensional structured memory cell formed by a through hole/L/8 connecting the transistor and the first layer cell capacitor 7.

In addition, in Fig. 1, 9.10 is a word line, and 11 is a word line.
．． 12 is a focus line, and 13.14 is a cell plate. Here, this memory cell has the same function as the conventional memory cell shown in FIG. In Figure 5, 1
5 is a single crystal silicon substrate, 16HMO5) Langinuta,
17 is a cell capacitor, 18 is a word line, 19 is a bit line, and 20 is a cell plate.

2 and 3 are diagrams showing a mask pattern and its cross-sectional structure of the three-dimensional structure memory cell shown in FIG. 1. (axis) is a mask pattern diagram, and (b) is a cross-sectional structure diagram.

FIG. 2 shows the PMOS transistor 6 of the second single active 111K memory cell in the Sol structure layer shown in FIG. It is a diagram when a cell capacitor 7 is formed. Note that 21 is a field oxide film. Here, on the cell capacitor of the memory cell 2. However, the cell capacitor part is formed by polysilicon 22 and 23 of
It may be a conventional capacitor made of single-crystal silicon and polysilicon, or it may be formed by a two-layer metal capacitor, or a trench type or stacked type capacitor. Also, through hole 8 to 1 ::・1
The connection of the active layer 1 to the cell capacitor 7 is connected to the first layer polysilicon 22 in FIG.
Connected to layer polysilicon 23, 11th polysilicon 22
It is also possible to use it as a cell rate.

FIG. 3 shows an NMOS transistor 3 of a memory cell in the first single active layer 1 of FIG.
It is a figure when forming.

Note that 24 is a field oxide film. Here, the cell capacitor of the memory cell is made of two layers of polysilicon 25.26
It is well formed. However, the cell capacitor part
It may be a conventional capacitor made of single-crystal silicon and polysilicon on an SOI structure, or it may be a two-layer metal capacitor or a stacked capacitor. In addition, the connection from the through hole 5 to the cell capacitor 4 of the second layer single active layer 2 is connected to the second layer polysilicon 26 in FIG. 3, but it is connected to the first layer polysilicon 25. It is also possible to use the second layer polysilicon 26 as a cell plate.

FIG. 4 is a conceptual diagram of another embodiment of the present invention, in which transistors and cell capacitors of a memory cell are expanded and formed in a plurality of active layers.

In the figure, 27 is 1 formed on a single crystal silicon substrate.
28 is a second active layer obtained by melting and growing polycrystalline silicon by beam irradiation on the top of an insulating layer that electrically insulates the first active layer; 29 is a second active layer; This is the third active layer obtained by melting and growing polycrystalline silicon by beam irradiation on top of an insulating layer that electrically insulates the active layer.

In FIG. 4(a), a MOS transistor 30 is formed in the active layer 28, and cell capacitors 31 and 32 of the memory 7 are formed in the active layers above and below the active layer 28, the pinch active layer 29, and the active layer 27. Then, a through hole 33 is formed between the active layers 27 and 28, and a through hole 3 is formed between the active layers 28 and 29111.
Connect with 4. Note that 35 is a word line, 36 is a bit fin, and 37.38 is a cell plate. here,
Part (a) of FIG. 4 is a conceptual diagram of a memory cell when the cell capacitor capacity of one memory cell is secured by expanding the memory cells in three active layers.

In part (b) of FIG. 4, MOS transistors 39 and 40 are formed in the active layer 28, cell capacitors 41 and 42 of the memory cell are formed in the active layer 27 and 29, and the active layer 27
, 28 and 29 to increase the degree of integration. FIG.

Note that 43.44 is a through hole, 45.46 is a word line, 47 is a pit line, and 48.49 is a cell plate.

In Figure 4, part (c) is similar to (a) and (b),
FIG. 2 is a conceptual diagram of a memory cell in the case where the memory cell is developed in three active layers, a cell capacitor of the memory cell is secured, and the degree of integration is increased to achieve high density. In the figure, 50.5
1 is a MOS transistor, 52° 53.54.55 is a memory cell cell capacitor, 56.57, 58.59 is a through hole, 60° 61 is a word line, 62 is a bit line, 63° 64 is a cell plate. be.

Here, the three cases shown in FIGS. 4(a), 4(b), and 4(c) have the same function as the conventional memory cell.

<Effects of the Invention> As described above, the semiconductor integrated circuit device of the great invention includes a first active layer formed on a single crystal silicon substrate and an insulating layer that electrically insulates the first active layer. A three-dimensional structure semiconductor memory element having a laminated structure of a second active layer obtained by melting and growing polycrystalline silicon by beam irradiation, each active layer having a single layer having an arbitrary width. Dynamic semiconductor memory consists of a crystalline active element region and an element isolation region that insulates this region at arbitrary intervals.
Since the transistors and cell capacitors of the Z child memory cells are distributed, the capacitance of the cell capacitor of the memory cell can be secured and the size of the cell can be reduced. Also,
Null-hole connections reduce routing and crossing of wiring, making it possible to reduce device area and increase speed.

In addition, the memory cell transistor is a PMOS transistor! ? ? Compared to the case where the circuit is configured using NMOS transistors, the circuit for boosting the word line in the periphery becomes unnecessary, the area of the peripheral circuit can be reduced, and the delay for boosting the word line is eliminated, so the element It is possible to achieve faster speeds.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram of a three-dimensional memory cell in which a dynamic RAM memory cell is realized with a two-layer active layer of an SOI structure, and the transistor and cell capacitor of the memory cell are each configured in separate layers. FIG. 3 is a mask pattern diagram and its cross-sectional structure diagram of the three-dimensional dynamic RAM memory cell of FIG. Figure 5 shows a conceptual diagram of a memory cell in a dynamic RAM when it is formed in the same active layer on a conventional two-dimensional single-crystal silicon substrate. It is a diagram. Code: 1:)” Kth layer single active layer, 2: 2nd layer single active layer, 3: NMO5l-transistor, 4: cell capacitor, 5 varnished through hole, 6: PMOS
Transistor, 7: Cell capacitor, 8 Varnish through hole, 27: 1st layer active layer, 28: 2nd layer active layer,
29: 3rd active layer, 30.39, 40.50.51
:MOS transistor, 31.32.41,42
．． 52゜53.54,55: Cell capacitor, 33
゜34.43,44,56.57.58.59 Varnish through hole. Agent: Patent attorney Takeshi Sugiyama (and 1 other person) 41 Figure 12

Claims (1)

[Claims] 1. A first active layer formed on a single crystal silicon substrate;
A three-dimensional active layer stacked structure semiconductor integrated circuit having a stacked structure of a second active layer obtained by melting and growing polycrystalline silicon by beam irradiation on top of an insulating layer that electrically insulates the first active layer. In the device, each of the active layers includes a single-crystal active element region having an arbitrary width and an element isolation region insulating the region at an arbitrary interval, and the single-crystal active element region includes: It is composed of PMOS, NMOS, or CMOSFET, and is characterized by having a through hole vertically connecting the active layers. A dynamic semiconductor memory element comprising a three-dimensional active layer stacked structure.