JPH02285669A - Memory device - Google Patents

Abstract

PURPOSE:To make it possible to realize a reduction in the sizes of memory cells and an increase in the integration of the memory cells and moreover, to obtain the memory cells capable of contriving an augmentation in a capacity by a method wherein a lower electrode, which is connected with a capacitor in the memory cell on one side of the memory cells adjoining each other, is formed of a first conductive layer, a lower electrode, which is connected with the capacitor in the other memory cell, is formed of a second conductive layer and the like. CONSTITUTION:An electrode 14 on one side, which is connected with a substrate 1 of a capacitor in the memory cell A on one side of at least two memory cells A and B adjoining each other, is formed of a first conductive layer, an electrode 19 on one side, which is connected with the substrate 1 of the capacitor in the other memory cell B of the above two memory cells A and B, is formed of a second conductive layer, which is a layer upper than the above first conductive layer, and at the same time, a third conductive layer, which is superposed on the above first conductive layer in a part D where the above memory cells adjoin each other and is a layer upper than the first and second conductive layers, is formed on the surface of the first conductive layer including the upper surface and lower surface of the first conductive layer and on the surface of the second conductive layer including the upper surface and lower surface of the second conductive layer and the third conductive layer is contrived so that it is used as an electrode 25 on the other side of the above capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device in which a stacked capacitor is formed covering the gate electrode of a switching transistor.

[Summary of the invention]

The present invention provides a memory device in which a memory cell includes a switching transistor and a stacked capacitor connected to the transistor, in which a substrate of the capacitor in one of at least two memory cells adjacent to each other is provided. One electrode to be connected is formed by a first conductive layer, and one electrode to be connected to the substrate of the capacitor in the other of the two memory cells is formed by a second conductive layer above the first conductive layer. The conductive layer is formed of a conductive layer, and the first conductive layer is overlapped with the first conductive layer in the adjacent portion, and the first and second conductive layers are further formed on the surfaces (including the upper surface and the lower surface) of the first and second conductive layers. By forming a third conductive layer above the capacitor and configuring the third conductive layer to serve as the other electrode of the capacitor, the area of the memory cell can be significantly reduced, the integration can be increased, and This makes it possible to increase capacity.

[Prior Art] Recently, as a structure of a memory device such as a DRAM (dynamic RAM), a structure in which the structure of a capacitor for storing information is of a laminated type (stack type) is known. In addition to increasing the area of the capacitor, it is also required to reduce the size of the memory cell and increase its integration.

As shown in FIG. 3, a conventional memory device having a stacked capacitor has an impurity diffusion region of a switching transistor on the surface of a semiconductor substrate (42) on which a field insulating layer (41) is formed. is formed,
A pinto line (46) made of, for example, an Al wiring layer is connected to one source/drain region (43a) of the impurity diffusion regions via a contact hole (44) (corresponding to region BC in the figure). ), and the other source/drain region (43b) is connected to the capacitor lower electrode (47) of the stacked capacitor.

The capacitor lower electrode (47) is connected to each memory cell (in the figure,
It is formed by patterning the second polycrystalline silicon layer for each region (corresponding to region MC), and the upper part of each gate electrode (48) of the switching transistor, which is the first polycrystalline silicon layer. It is formed through an interlayer insulating layer (49). This capacitor lower electrode (47)
is the capacitor upper electrode (
50) with a dielectric film (51) interposed therebetween, and a capacitor is constituted by the laminated structure of the capacitor upper electrode (50), the dielectric film (51), and the capacitor lower electrode (47).

In this memory device, necessary charges are stored in the stacked capacitor, and reading and writing are performed via the bit line (46) while being controlled by the switching transistor.

[Problems to be Solved by the Invention] In the conventional memory device as described above, when forming the capacitor lower electrode (47), a second layer of polycrystalline silicon is formed on the entire surface, and the polycrystalline silicon layer is Using photolithography technology, patterning is performed to separate each memory cell (MC).

At this time, by reducing the width (Re) of the pattern, the capacitor area can be increased, and by increasing this capacitor area, sufficient operation is possible even with a small memory cell size, resulting in high integration. This will result in the realization of

However, the pattern width R6 in the conventional example is a value greater than a certain value (0
, 8 to 1.0 μ), making it impossible to achieve higher integration.

FIG. 4 is a schematic diagram of a planar layout of a conventional memory device, in which a 2-bit memory device has a bit line extraction portion (BC) in the center and capacitor lower electrodes (47) on both sides.
When one set of cell structures is considered as one unit (U), the capacitor lower electrodes (47) for each unit (U) are arranged so as to be separated from each other by the pattern width (Ro). The area provided for the pattern width (R,) is required as the area required for patterning, and the existence of this area has been a major barrier to high integration.

Note that the solid line (52) indicates the boundary between the field insulating layer (41) and the element formation region.

In this way, in the conventional memory device, the capacitor lower electrode (47) is arranged in a plane, and - unit (
, U), the capacitor lower electrodes (47) of adjacent memory cells (MC) cannot be overlapped with each other. Therefore, when keeping the capacity constant, memory cells (MC
, ) can be considered by reducing the thickness of the dielectric film (51) formed on the upper surface of the capacitor lower electrode (47), but there is a limit to the satisfactory reduction of the memory cell (MC). was there.

The present invention has been made in view of the above points, and an object thereof is to be able to form capacitor lower electrodes between adjacent memory cells for each unit by overlapping each other, thereby reducing the size of memory cells. The object of the present invention is to provide a memory device that can achieve high integration and high integration, and can also increase capacity.

(Means for Solving the Problems) A memory device of the present invention is a memory device (M) in which a memory cell includes a switching transistor and a stacked capacitor connected to the transistor.
at least two memory cells (A) adjacent to each other
, (B), one electrode connected to the substrate (1) of the capacitor in the negative memory cell (A), that is, the capacitor lower electrode (14), is connected to the first conductive layer (polycrystalline silicon layer (13). )), and two memory cells (A), (
One electrode connected to the substrate (1) of the capacitor in the other memory cell (B), that is, the capacitor lower electrode (19), is connected to the second conductive layer (13) above the first conductive layer (13). A conductive layer (polycrystalline silicon layer (18)) is formed, and in an adjacent portion (D), a first conductive layer (
13), and the first and second conductive layers are superimposed on the surface (including the top surface and the bottom surface) of the first conductive layer (13) and the surface (including the top surface and bottom surface) of the second conductive layer (18) A third conductive layer (polycrystalline silicon layer (24)) is formed above layers (13) and (18), and this third conductive layer (24) serves as the other electrode of the capacitor, that is, the capacitor upper electrode. (25
).

[Effect]

According to the configuration of the present invention described above, the capacitor lower electrodes (14) and (19) adjacent to each other between the units (U)
the first and second conductive layers (13) and (18), respectively.
Therefore, the capacitor lower electrodes (14) and (19) can be overlapped, and the size of the memory cell can be reduced and the memory cell can be highly integrated.

In addition, the superimposed capacitor lower electrode (14) and (
19) by a third conductive layer (24) over each surface (including the top and bottom surfaces) of the capacitor top electrode (
25), the entire surface of each of the capacitor lower electrodes (14) and (19) can be used as a capacitor, and the capacitance of the stacked capacitor memory device can be increased. Furthermore, since the surfaces of the capacitor lower electrodes (14) and (19) are used as capacitors in this way, it is easy to design for equalizing the capacitance between adjacent memory cells, thereby increasing practical use.

[Example] The present invention will be described in detail below with reference to FIGS. 1 and 2.

As shown in FIG. 1H, the memory device (M) according to this embodiment has a cell structure of one set of two bits having a memory cell (A), a memory cell (B), and a bit line lead-out portion (C).
FIG. 1 is a process diagram showing the structure of the -unit (U) in the order of manufacturing steps. The steps will be explained step by step below.

First, as shown in FIG. 1A, a field insulating layer (2) is formed on the upper surface (1a) of a semiconductor substrate (1) such as a first conductivity type silicon substrate by a selective oxidation method. 2) A gate insulating film, for example, a SiOg oxide film (3) for the gate is formed by thermal oxidation on the element formation region surrounded by the above. Thereafter, a high melting point metal polycide layer (4) consisting of an impurity-doped polycrystalline silicon layer and a high melting point metal silicide layer is formed on the gate insulating film (3) by CVD or the like. Then, a relatively thick SjO□ oxide film (5) is formed on this polycide layer (4) by CVD or the like.

Next, as shown in FIG. 1B, the 5i (h) oxide film (5) and the polycide layer (4) are selectively etched along the word line pattern. At this time, the gate electrode formed by the polycide layer (4) (6) is formed. Then, SiO*
After an oxide film is deposited on the entire surface by CVD or the like, sidewalls (7) are formed by etching back. Then, the gate electrode (6) and the sidewall (
7) as a mask, impurities of the second conductivity type are ion-implanted into the surface (1a) of the substrate (1) to form source/drain regions (
8a), (8b) and (8c) are formed. At this time, on the surface (1a) of the substrate (1), a very thin SiO□
An oxide film is formed by thermal oxidation.

Next, as shown in FIG.
After forming by CVD method etc., this SiO□ oxide film (9
) A 5iJ4 film (10) is deposited on the film by low pressure CVD method or the like. This 5iJa film (10) is removed from the SiO□ oxide film (9) and zide wall (7
) is used as a stopper mask to protect the

Thereafter, a relatively thick SiO□ oxide film (11) is formed on the Si3N4 film (10) by CVD or the like.

Next, as shown in the first diagram, source/drain regions (
8a) SiO2 oxidation NG on top? (9), S i
3N4 film (10) and SiO□ oxide film (11) were subjected to reactive ion etching (Reactive Jon E
tching: RIE) to open a contact hole (12). After that, an impurity-doped polycrystalline silicon layer (first conductive layer) (13) is formed on the entire surface including the contact hole (12) by CVD method, and then this polycrystalline silicon layer (13) is formed by RIB. It is patterned to form the capacitor lower electrode (14) of the memory cell (A). In addition, the side wall (7) and SiO
□In the future, the layer consisting of the oxide film (9) will be replaced with the interlayer insulating layer (15).
).

Next, as shown in FIG. 1E, the capacitor lower electrode (1
After forming a SiO□ oxide film (16) on the entire surface including 4) by CVD method etc., an interlayer insulating layer (15) on the source/drain region (8C), a Si:+)L film (10), 5iO
The Z oxide films (11) and (16) are removed by RIE to open the contact I/ball (17). Then, after forming an impurity-topped polycrystalline silicon layer (second conductive layer) (1B) on the entire surface including the contact hole (17) by CVD method, this polycrystalline silicon layer (18) is
It is patterned at E to form the capacitor lower electrode (19) of the memory cell (B). At this time, in the adjacent portion (D) of the memory cells (A) and (B) between units (tJ) (i.e., above the field insulating layer (2)), the capacitor lower electrodes (14) and (19) are connected to each other. A portion of it is overlapped with a SiO□ oxide film (16) interposed therebetween.

Next, as shown in FIG. 1F, a 5i02 oxide film (16) is formed.
and (11) Wet etching is performed on the entire surface using a hydrofluoric acid etching solution. At this time, the SiO□ films (16) and (11) between the capacitor lower electrodes (14) and (19) are also side etched. The lower layer of the 5iO7 oxide films (16) and (11) is a 5iJ stopper.
Since there are 4 films (10), this Si3N4 film (10)
) is not removed. As a result of this wet etching, in the adjacent portion (D), the capacitor lower electrode (19) extends in an eaves-like manner onto the lower layer capacitor lower electrode (14), and the capacitor lower electrode (14) is formed on the 5iJn film (10). A cavity (20) having a substantially S-shaped cross section is formed extending in the shape of an eave and extending from between the capacitor lower electrodes (19) and (14) to between the capacitor lower electrode (14) and the SLNs film (10). Also,
Each capacitor lower electrode (19) (14) also extends like an eave to the bit line extraction portion (C) side, and each capacitor lower electrode (19"l), (14) SiJ, film (14)
Cavities (21) and (22) are also formed between the two holes (21) and (22), respectively.

Next, as shown in FIG.
A dielectric film (23) made of an oxide film is formed.

In addition, instead of this 5in2 oxide film, a 5iJ4 film or a 5in
The 2Si3N4-3iO□ film may be used as the dielectric film (23). Then, the capacitor lower electrode (19), (1
4), an impurity-doped polycrystalline silicon layer (2
4) Form.

This polycrystalline silicon layer (24) is formed by, for example, low-pressure CVD.
The capacitor lower electrode (
19), (14) Dielectric film covering the entire surface (23)
It is formed to further cover the . That is, a polycrystalline silicon layer (24) is formed on the entire top, side and bottom surfaces of the capacitor lower electrodes (19), (1,1) via the dielectric film (23), and the cavities (20), ( 21)
and (22) are also sufficiently filled. Thereafter, the polycrystalline silicon layer (24) is patterned by RIE to form a capacitor upper electrode (25). Normally, when forming capacitor lower electrodes with different layers, it is necessary to form a capacitor upper electrode on the upper surface of each capacitor lower electrode, and to form a set of capacitor upper electrodes, further interposing an interlayer insulating layer between the two capacitor lower electrodes. However, in this example, the SiO□ oxide films (16) and (11) between the capacitor lower electrodes (19) and (14) are removed by wet etching, and then the capacitor upper electrode (25) is etched by low pressure CVD.
Since they are formed all at once, as described above, there is no need to stack a set of capacitor lower electrodes and capacitor upper electrodes in multiple layers with interlayer insulating layers interposed therebetween, and the process is simplified.

Next, as shown in FIG.
An interlayer insulating layer (26) made of SiO□ is formed on the entire surface including
) is formed by CVD method etc., then an interlayer insulating layer (15) on the source/drain region (8b) and a Si+N4 film (1
0) and the interlayer insulating layer (26) are removed by RIE to open a bit line contact hole (27). After that, an An wiring layer (28) is formed on the entire surface, and then this Aj2 wiring layer (28) is formed. For example, as shown in FIG.
29), the memory device (M) according to this embodiment is completed by patterning by RIE.

Although the above steps have been described for the unit (U) of the memory device (M) for convenience of explanation, in reality, as shown in FIG. 2, a plurality of units are formed at the same time. At this time, both sides of each unit (U) are formed so as to overlap each other. That is, the capacitor lower electrodes (19) and (14) overlap in the overlapped portion (shown by diagonal lines) (a). Note that the solid line indicated by (30) is the field insulating layer (2).
This figure shows the boundary between the area and the element formation area. Also, although it is not passed down orally, each unit is arranged in a staggered pattern.

As described above, according to this example, the capacitor lower electrode (14) of the memory cell (A) and the capacitor lower electrode (19) of the memory cell (B) are formed using different layers (the polycrystalline silicon layer (13) and the polycrystalline silicon layer (13)). Since the capacitor lower electrodes (14) and (19) are formed from a crystalline silicon layer (18), it is possible to separately pattern and form the adjacent capacitor lower electrodes (14) and (19) between each unit (U). , the capacitor lower electrodes (14), (19) can be overlapped in their adjacent parts (D), i.e. on both sides of each unit (U) (indicated by diagonal lines in FIG. 2).
Since the elements (a) can be formed in such a manner that they overlap each other, it is possible to significantly reduce the area of the memory cell, and it is possible to achieve a high degree of integration of the memory cell.

Also, a cavity (20) formed between the capacitor lower electrodes (14), (19) and the Si:+Na film (10),
The capacitor upper electrode (25) is inside (21) and (22).
) By filling the polycrystalline silicon layer (24), a capacitor upper electrode (25) is formed over each surface (including the upper and lower surfaces) of the capacitor lower electrodes (14) and (19). As a result, the entire surface of each of the capacitor lower electrodes (14) and (19) can be utilized as a capacitor, and the capacitance can be increased.

In addition, in order to utilize the entire surface of the capacitor lower electrodes (14) and (19) as a capacitor, as in a double series,
Same area, e.g. capacitor lower electrode (14) (19)
The capacitance with respect to the projected area of the overlapped portion (in FIG. 2, the area (a) not shown with diagonal lines) is the same between the capacitor lower electrodes (14) and (19). Therefore,
When obtaining the same capacitance between memory cells, the capacitor lower electrode (14
), (19) can be realized by making the shape of the projected area almost bilaterally symmetrical, which is easy to design and has many practical applications.

〔Effect of the invention〕

A memory device according to the present invention is a memory device in which a memory cell includes a switching transistor and a stacked capacitor connected to the transistor, in which one of at least two memory cells adjacent to each other is provided. One electrode connected to the substrate of the capacitor in the second memory cell is formed of a first conductive layer, and one electrode connected to the substrate of the second capacitor in the other of the two memory cells is formed of the first conductive layer. A second conductive layer is formed above the first conductive layer, overlaps with the first conductive layer in the adjacent portion, and further overlaps the surface (including the upper surface and the lower surface) of the first conductive layer. A third conductive layer that is higher than the first and second conductive layers is formed on the surface (including the upper surface and the lower surface) of the second conductive layer, and this third conductive layer is connected to the other electrode of the capacitor. With this structure, it is possible to significantly reduce the area of the memory cell, increase the degree of integration, and increase the capacity.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing the configuration of a memory device according to this embodiment, FIG. 2 is a plan view showing an example of the planar layout of this embodiment, FIG. 3 is a configuration diagram showing a conventional example, and FIG. FIG. 2 is a plan view showing an example of a conventional planar layout. (M) is a memory device, (A) and (B) are memory cells, (
C) is the bit line extraction part, (D) is the adjacent part (overlapping part), (1) is the semiconductor substrate, (2) is the filled insulating layer, (6) is the gate electrode, (8a), (8b),
(8c) is the source/drain region, (10) is 5iJn
membrane, (14) is the capacitor lower electrode, (15) is the glabella insulating layer, (19) is the capacitor lower electrode, (25) is the capacitor upper electrode, (2G) is the glabella insulating layer, (28) is A
I! The wiring layer (29) is a bit line.

Claims (1)

[Claims] In a memory device in which a memory cell includes a switching transistor and a stacked capacitor connected to the transistor, the above-mentioned method in one of at least two adjacent memory cells is provided. One electrode connected to the substrate of the capacitor is formed of a first conductive layer, and one electrode connected to the substrate of the capacitor in the other of the two memory cells is made of a first conductive layer. The surface of the first conductive layer including the upper surface and the lower surface of the first conductive layer and the second conductive layer are formed of an upper second conductive layer and overlap with the first conductive layer in the adjacent portion. A third conductive layer, which is an upper layer than the first and second conductive layers, is formed on the surface of the second conductive layer including the upper and lower surfaces of the conductive layer, and this third conductive layer covers the other conductive layer of the capacitor. A memory device that serves as an electrode.