JPH05243521A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To furnish a semiconductor memory device having a structure facilitating an increase of the capacity of a capacitor without increasing an area of occupation of a substrate, regarding a DRAM device having a structure suited for attaining a high component density. CONSTITUTION:A silicon substrate 1, an insulating layer 2 thereon, a single- crystal silicon layer 3 formed further thereon, a transistor structure 4 formed in this layer and a first fin-type electrode 8 connected electrically to a drain region D of this structure are provided, and a second fin-type electrode 9 constituting a stack-type capacitor is disposed opposite to the above electrode with insulating films 10a and 10b interlaid. Moreover, third and fourth fin-type electrodes 11 and 12 are disposed in the insulating layer in positions being symmetric with respect to a source S and the drain region, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access type semiconductor memory device having a structure suitable for achieving a high degree of integration.

[0002]

2. Description of the Related Art In a typical dynamic random access semiconductor memory (DRAM), one MOS transistor and one capacitor form one memory cell. In order to form a highly integrated DRAM, it is important to reduce the size of the memory cell.

In order to reduce the size of the capacitor and maintain the capacitance at a constant value, it is effective to make the capacitor structure a multilayer structure. The stacked fin type capacitor has a structure in which a multi-layered polysilicon layer is laminated on a semiconductor surface with an insulating film interposed to form a counter electrode pair. Although the structure is suitable for increasing the area of the counter electrode of the capacitor, the capacitor portion has a shape protruding on the semiconductor surface.

The gate electrode of the MOS transistor of DRAM is composed of a polycrystalline silicon word line. As the word line becomes thinner and the number of connected MOS transistors increases, the voltage drop in the word line increases.

To reduce the voltage drop, a shunted word line made of a low resistivity metal such as aluminum or a high melting point metal is formed above the polycrystalline Si word line, and the polycrystalline Si word line is formed at predetermined intervals. It is effective to make contact with the word line.

FIG. 2 shows an example of the structure of a conventional DRAM cell. FIG. 2A is a plan view showing a planar arrangement,
FIG. 2B is a sectional view showing a sectional structure. Figure 2 (A)
In, the active region AR on the semiconductor surface is arranged in a zigzag shape, and the bit line BL is arranged horizontally so as to be in contact with the bit contact region BC.
A capacitor fin electrode CF of a stacked fin type capacitor is arranged in the central portion of the drawing, and is in contact with the active region AR and the capacitor contact region CC.

At an intermediate position between the bit contact BC of the active region AR and the capacitor contact region CC,
A lower word line WL is arranged below the capacitor fin electrode on the semiconductor surface via an insulating film, and constitutes the gate of the MOS transistor. Further, a shunted word line WL is arranged above the capacitor fin electrode so as to overlap the lower layer word line. Although another word line WL is also arranged on the right side in the drawing, this word line WL is connected to the gate of an adjacent MOS transistor.

FIG. 2B shows a horizontal sectional structure passing through the capacitor contact region CC of FIG. 2A. p
A LOCOS (local oxidation) region 152 is selectively formed on the surface of the type silicon substrate 151 to define an active region. In the active region of the p-type silicon substrate 151, n ⁺
A type drain region 153 is formed and connected to one electrode 160 of the stacked fin type capacitor.

One electrode 160 is made of polycrystalline silicon and has two fin type 160a electrodes. A gate insulating film 154 is formed on the surface of the semiconductor active region around the electrode 160, and the gate insulating film 154 and the LOC are formed.
A polycrystalline silicon electrode 155 forming a word line WL is arranged on the OS region 152 and forms a gate electrode of a transistor.

Two insulating layers 156 and 157 are disposed on the polycrystalline silicon electrode 155. These two layers of insulating films are made of, for example, SiO ₂ , and the bit line BL is sandwiched between them. The surface of one electrode 160 of the capacitor is covered with an insulating film (not shown) such as a silicon oxide film or a silicon nitride film, and the surface thereof is covered with a cell plate 162 of polycrystalline silicon.

That is, the electrode 160 and the cell plate 16
2 face each other to form a stacked fin type capacitor. The surface of the cell plate 162 is covered with an interlayer insulating film 164 such as SiO _{2 and} the insulating layer 1 such as BPSG is formed on the surface thereof.
65 covers. The surface of the BPSG layer 165 is flattened, and the shunted word line 166 made of metal is arranged on the surface.

[0012]

If the area occupied by the capacitor is reduced in order to improve the degree of integration of the DRAM, it becomes difficult to maintain the capacitance of the capacitor at a constant value.

When the number of fin layers of the stacked fin type capacitor is increased in order to increase the capacitance of the capacitor, the unevenness on the surface of the semiconductor substrate becomes severe, and it becomes difficult to form the wiring.

An object of the present invention is to provide a semiconductor memory device having a structure in which the capacitance of a capacitor can be easily increased without increasing the area occupied by a substrate. Another object of the present invention is to provide a semiconductor memory device having a structure in which wiring can be easily formed even if the capacitance of a capacitor is increased without increasing the area occupied by a substrate.

[0015]

A semiconductor memory device of the present invention includes a supporting silicon substrate, an insulating layer formed on the supporting silicon substrate, a single crystal silicon layer disposed on the insulating layer, and a single crystal silicon layer. A transistor structure having a source region, a channel region, and a drain region formed in a crystalline silicon layer; a plurality of first fin-type electrodes electrically connected to the drain region and formed in an insulating layer; A second fin-type electrode that is disposed in the layer and faces the first fin-type electrode with an insulating film interposed therebetween to form a first stacked fin-type capacitor; and a first fin-type electrode. A plurality of third fin-type electrodes electrically connected to the drain region of the single-crystal silicon layer on the opposite side are arranged to face the third fin-type electrode via an insulating film, Stacked fin type capacity And a fourth fin type electrodes constituting the data.

Further, another semiconductor memory of the present invention includes a supporting silicon substrate, an insulating layer formed on the supporting silicon substrate, and a single crystal silicon layer arranged on the insulating layer.
A transistor structure formed in the single crystal silicon layer and having a source region, a channel region, and a drain region; and a plurality of first fin-type electrodes electrically connected to the drain region and formed in an insulating layer; Is disposed in the insulating layer, and is disposed so as to face the first fin-type electrode with the insulating film interposed therebetween,
A second fin-type electrode forming a first stacked fin-type capacitor.

[0017]

The supporting silicon substrate, the insulating layer, and the single crystal silicon layer arranged on the insulating layer constitute a so-called SOI (semiconductor on insulator) structure, and stacked fins are provided above and below the single crystal silicon layer. Type capacitors are formed. Therefore, the capacitance of the capacitor can be increased without making the step of the capacitor section excessively large.

When a capacitor is formed in the insulating layer between the single crystal silicon layer and the supporting silicon substrate and the capacitor on the single crystal silicon layer is omitted, an easy flat surface such as wiring is formed. Obtainable.

Further, since the required structure can be formed on both surfaces of the single crystal silicon layer, it becomes easy to form redundant wiring such as a shunted word line. Further, a double gate structure can be realized by forming gate electrodes above and below the single crystal silicon layer.

[0020]

1 shows the structure of a DRAM memory cell having a stacked fin type capacitor according to a basic embodiment of the present invention.

A single crystal silicon layer 3 is arranged on a supporting silicon substrate 1 with an insulating layer 2 interposed therebetween. The single crystal silicon layer 3 has a transistor structure 4 formed therein, and a source region S and a drain region D are formed with a channel region 7 interposed therebetween. A bit line 5a is formed in contact with at least one surface of the source region S.

The word lines 6a also functioning as gate electrodes on both sides of the channel region 7 with a gate insulating film interposed therebetween.
And 6b are arranged. A first fin-type electrode 8 and a third fin-type electrode 11 that form a stacked fin-type capacitor are provided on both sides of the drain region D, respectively.
Are connected.

Insulating films 10a and 10b are provided so as to face the first fin-type electrode 8 and the third fin-type electrode 11.
The second fin-type electrode 9 and the fourth fin-type electrode 12 are formed via the. At least one of the word lines 6a and 6b and the first to fourth fin-type electrodes 8;
9, 11, and 12 are preferably formed of conductive polycrystalline silicon.

In the structure shown in FIG. 1, the lower structure is once formed on the single crystal silicon layer 3 and then bonded to the supporting silicon substrate 1 to thin the single crystal silicon layer 3 to a predetermined thickness. It can then be made by forming the upper structure.

FIG. 3 shows a DRAM memory cell according to a more specific embodiment of the present invention. The planar structure of this memory cell can be made equivalent to that shown in FIG. The cross-sectional view of FIG. 3 is taken along a line passing through the bit contact region BC and the capacitor contact region CC of FIG. 2 (A).

In the single crystal silicon substrate 20 having the MOS transistor structure, the active region is defined by the LOCOS region 22, and in the active region, the p-type channel region 21 and n ⁺ forming the source region and drain region sandwiching the channel region are formed. A mold region 23 is included. On the lower surface of the n ⁺ type region 23 forming the source region, a bit line 25 made of polycrystalline silicon, polycide or the like including a source electrode is formed.

A back word line 26 and a front word line 27 are formed on the upper surface and the lower surface of the channel region 21 via a gate insulating film. The rear word line 26 is formed of, for example, polycrystalline silicon,
Front word line 27 is formed of a metal such as tungsten silicide WSi.

By thus forming the word lines on both sides of the channel region, it is possible to form a shunted word line structure which reduces the resistance of the word lines. If the rear word line 26 is also made of metal, it has a double gate structure.

SiO ₂ is formed on the rear word line 26.
The first back insulating film 34 is formed, and the bit line 25 extends thereon. A backside second insulating film 35 of SiO ₂ or the like is formed so as to cover the bit lines 25. Openings are formed in the capacitor contact regions of these laminated insulating films 34 and 35, and the back surface capacitor electrodes 31 made of impurity-doped polycrystalline silicon are connected thereto.

The back surface capacitor electrode 31 has two layers of fins 31a. The surface of the back surface capacitor electrode 31 is an insulating film (not shown) such as a silicon oxide film or a silicon nitride film.
And the surface including the space between the fins is covered with a rear cell plate electrode 32 formed of polycrystalline silicon doped with impurities. The back cell plate electrode 32 has three layers of fins 32a, and the fin 31a of the back capacitor electrode is sandwiched between the fins.

On the surface of the rear cell plate electrode 32,
A back surface interlayer film 41 made of CVDSiO ₂ or the like is formed. On the back surface interlayer film 41, a relatively thick BPSG layer 4 which is a silicate glass layer added with boron and phosphorus.
2 is formed and its surface is flattened.

On the surface of the planarized BPSG layer 42,
A supporting substrate is attached. The support substrate is C on the surface
This is a Si support substrate 44 having a support substrate oxide film 43 formed of VDSiO ₂ or thermal oxide SiO ₂ , and the support substrate oxide film 43 is bonded to the BPSG layer 42.

A front insulating film 36 made of SiO ₂ or the like is formed on the single crystal silicon layer 20 so as to cover the front word lines 27. In this structure, since the bit line is not formed on the front surface, the front insulating film is formed of one layer. However, when the bit line is formed on the front surface, the front insulating film also has a laminated structure.

An opening is formed in the front insulating film 36 on the capacitor contact region of the single crystal silicon layer 20, and a front surface capacitor electrode 38 of polycrystalline silicon doped with impurities is formed in the opening, and the single crystal silicon is formed. Layer 20 n ⁺
It is in electrical contact with the mold area 23.

The front capacitor electrode 38 has three layers of fins 38a. An insulating film (not shown) such as silicon oxide or silicon nitride is formed on the surface of the front capacitor electrode 38 including the spaces between the fins, and the surface of the front cell plate electrode 39 is made of polycrystalline silicon doped with impurities. Is covered by.

On the surface of the front cell plate electrode 39,
A front interlayer film 47 made of CVDSiO ₂ is formed, and a thick BPSG layer 48 is further formed on the surface thereof.

In the structure of FIG. 3, since stacked fin capacitors are formed above and below the single crystal silicon layer 20, it is possible to form a memory cell having a relatively high capacitor capacity with a relatively small substrate occupation area. You can

Further, by forming word lines above and below the channel region, a shunted word line with reduced resistance of the word line or a double gate structure with good controllability effective for preventing a short channel effect is realized. be able to.

A manufacturing method for making a DRAM memory cell as shown in FIG. 3 will be described below with reference to FIGS. As shown in FIG. 4A, a laminated structure of an oxide film and a nitride film (not shown) is formed on the active region of the p-type silicon substrate 20, and the exposed silicon surface is oxidized by the selective thermal oxidation method. , LOCOS regions 22 are formed. LOC
After the OS process, the nitride film and the oxide film used for the oxidation mask are removed.

Next, a back gate oxide film 24 is formed on the exposed surface of the p-type silicon substrate 20 by thermal oxidation, an impurity-doped polycrystalline silicon layer is formed on the surface, and a back word is formed by patterning. Line 2
6 is formed.

As shown in FIG. 4C, Si is formed on the surface of the semiconductor substrate while covering the patterned rear word line 26.
The first back insulating film 34 and the second back insulating film 34 made of O ₂ or the like.
The insulating film 35 is formed by CVD. The back first
A bit line is formed between the insulating film 34 and the second back insulating film 35.

Next, as shown in FIG. 4D, a silicon nitride film 51, a polycrystalline silicon layer 52, and S on the back insulating film.
Each of the iO ₂ layers 53 is formed by CVD. After that, an etching mask is formed on the surface of the SiO ₂ layer 53, and an opening 55 reaching the surface of the p-type silicon substrate 20 is formed by selective etching. After that, the etching mask is removed.

Next, as shown in FIG. 5A, a polycrystalline silicon layer 56 is formed by CVD and is connected to the already-formed polycrystalline silicon layer 52. Note that these polycrystalline silicon layers are doped with impurities to have conductivity. The polycrystalline silicon layers 52 and 56 form the back surface capacitor electrode 31.

After that, an etching mask is formed on the surface and etching is performed to reach the second back insulating film 35 to pattern the back capacitor electrode 31. Since the silicon nitride film 51 is made of a material different from that of the upper and lower layers, this layer can be used as an etching stopper, and the upper layer can be once etched and then this layer can be etched.

Further, the silicon nitride film 51 and SiO ₂ 53 above the second back insulating film 35 are removed by etching. By this step, the surface of the back surface capacitor electrode 31 is exposed. Then, the surface of the back surface capacitor electrode 31 is thermally oxidized to form a capacitor insulating film.

The capacitor insulating film may be formed not only by an oxide film but also by a combination of a nitride film and an oxide film. Further, it is possible to form the silicon nitride film 51 and the SiO ₂ layer 53 with other materials.

Next, as shown in FIG. 5B, the reduced pressure CV
Polycrystalline silicon is deposited by D to fill gaps such as between fins and cover the surface. The polycrystalline silicon is also doped with impurities to have conductivity. In this way, the back cell plate electrode 32 is formed.

Further, as shown in FIG. 5C, a CVD SiO ₂ interlayer film 41 is formed on the surface of the back cell plate electrode 32, and a relatively thick back surface BPSG is formed thereon.
Deposit layer 42. The above steps are the same
This is the same as the manufacturing process of.

Further, the surface of the back BPSG layer 42 is polished to form a flat surface. Next, as shown in FIG. 6A, another Si substrate 44 to be used as a supporting substrate is prepared, and a CVDSiO ₂ layer or a thermal oxidation layer 43 is provided on the surface thereof.
To form. The supporting substrate oxide film 43 of the supporting substrate 44 is overlapped on the back surface BPSG layer 42 whose surface is flattened, and about 900-
Bonding is performed at a temperature of 950 ° C. By such heating, the BPSG layer 42 acquires fluidity and the BPSG layer 42
Is firmly bonded to the support substrate oxide film 43.

Next, as shown in FIG. 6B, the p-type silicon substrate 20 is polished from the bottom surface side. In FIG. 6B, the substrate is shown inverted. Silicon substrate 2
If 0 is an epitaxial silicon substrate, the portion other than the epitaxial layer is first polished by etching using the difference in impurity concentration, and then the epitaxial layer is LOC'd.
Polishing may be performed until the OS region 22 is exposed, and further polishing may be performed if necessary. It is also possible to use another polishing method.

FIG. 6B shows a state in which the p-type silicon substrate 20 is thus polished to a predetermined thickness in a state in which it is turned upside down from FIG. 6A. Next, as shown in FIG. 7A, after the exposed surface of the p-type silicon substrate 20 is cleaned and a gate oxide film 54 is formed, a metal film such as tungsten silicide is deposited and patterned to form a front word. The line 27 is formed. In this state, n type impurities are ion-implanted using the front word line 27 as a mask to form an n ⁺ type region 23 in the p type silicon substrate 20. This n ⁺ type region constitutes the source / drain region of the transistor.

Thereafter, as shown in FIG. 7B, the front surface first insulating film 36 is covered with CVDS so as to cover the front word lines 27.
Opening 55 is formed in the capacitor contact region by using iO ₂ .
To form.

Thereafter, as shown in FIG. 8A, a front surface capacitor electrode 38 made of polycrystalline silicon is formed by the same process as that for forming the back surface capacitor electrode. The figure shows the case where a capacitor electrode having three layers of fins is formed.

As shown in FIG. 8B, after forming an insulating film (not shown) on the surface of the front capacitor electrode 38, the front cell plate electrode 39 is formed of polycrystalline silicon by low pressure CVD, and the surface thereof is formed. A front surface interlayer film 47 formed of CVD SiO ₂ is deposited on the upper surface, and a relatively thick front surface BPSG layer 48 is formed on the surface.

Thus, the DRAM cell having the stacked fin type capacitors on both surfaces of the MOS transistor is formed. By significantly increasing the capacitor area, the capacitor capacitance can be significantly increased.

When forming the bit line on the front surface, the bit line is formed and the front second insulating film is formed after the front first insulating layer is formed in the step of FIG. 8A. Cover the bit line. Further, in the case where the word lines and the bit lines are double formed in this way, it is preferable that at least one of them is formed of a metal having high conductivity.

As described above, the single crystal silicon layer is arranged on the supporting substrate with the insulating layer sandwiched therebetween, and the stacked fin structure is formed in the insulating layer, so that the capacitor capacitance per unit substrate area is high. It becomes possible to create a DRAM.

It is also possible to form a DRAM without forming a stacked fin structure on the front surface in the state of FIG. 6 (B) or FIG. 7 (B). In this case, a flat surface is obtained, which facilitates multilayer wiring on the surface.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0060]

As described above, according to the present invention,
It is possible to significantly increase the capacitance of the DRAM capacitor.

Therefore, the integration degree of DRAM can be increased. If gate electrodes are formed on both sides of the channel region, a shunted word line or double gate structure can be realized. By reducing the effective resistance of the word line, high speed operation of the DRAM is promoted.

Furthermore, it is possible to reduce the resistance of the bit line by forming the bit line on both sides of the single crystal silicon layer.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a DRAM cell according to a basic embodiment of the present invention.

FIG. 2 shows a configuration example of a DRAM cell according to a conventional technique. 2A is a plan view showing a planar arrangement, and FIG. 2B is a sectional view showing a sectional configuration.

FIG. 3 is a sectional view showing a structure of a DRAM cell according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the manufacturing method for manufacturing the DRAM as shown in FIG.

FIG. 5 is a cross-sectional view for explaining the manufacturing method for manufacturing the DRAM as shown in FIG.

FIG. 6 is a cross-sectional view for explaining the manufacturing method for making the DRAM as shown in FIG.

FIG. 7 is a cross-sectional view for explaining the manufacturing method for manufacturing the DRAM as shown in FIG.

FIG. 8 is a sectional view for explaining the manufacturing method for manufacturing the DRAM as shown in FIG.

[Explanation of symbols]

1 Supporting Silicon Substrate 2 Insulating Layer 3 Single Crystal Silicon Layer 4 Transistor Structure 5 Bit Line 6 Word Line 7 Channel Region 8 First Fin Type Electrode 9 Second Fin Type Electrode 10 Insulating Film 11 Third Fin Type Electrode 12 Fourth fin-type electrode S Source region D Drain region 20 Single crystal silicon layer 21 p-type region 22 LOCOS region 23 n ⁺ type region 25 bit line 26 backside wordline 27 frontside wordline 31 backside capacitor electrode 32 backside cell plate electrode 34 First back insulating film 35 Second back insulating film 36 Front insulating film 38 Front capacitor electrode 39 Front cell plate electrode 41 Back interlayer film 42 BPSG layer 43 Support substrate oxide film 44 Support substrate 47 Front interlayer film 48 BPSG layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Tanaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

[Claims] 1. A supporting silicon substrate (1), an insulating layer (2) formed on the supporting silicon substrate, a single crystal silicon layer (3) arranged on the insulating layer, and a single crystal silicon layer. A transistor structure (4) formed inside and having a source region (5), a channel region (7) and a drain region (D), and electrically connected to the drain region and formed inside the insulating layer (2) A plurality of layers of the first fin-type electrode (8) and the first fin-type electrode and the insulating film (1) disposed in the insulating layer.
Second fin-type electrodes (9) which are arranged to face each other with respect to each other and constitute a first stacked fin-type capacitor.
And a single crystal silicon layer (3) on the side opposite to the first fin type electrode.
A plurality of layers of the third fin-type electrode (11) electrically connected to the drain region of the second fin-type electrode, the third fin-type electrode (11b) and the third fin-type electrode (11b) that face each other via the insulating film (10b). Semiconductor memory device having a fourth fin-type electrode (12) forming a fin-type capacitor 2. A supporting silicon substrate (1), an insulating layer (2) formed on the supporting silicon substrate, a single crystal silicon layer (3) arranged on the insulating layer, and a single crystal silicon layer. A transistor structure (4) formed inside and having a source region (5), a channel region (7) and a drain region (D), and electrically connected to the drain region and formed inside the insulating layer (2) A plurality of layers of the first fin-type electrode (8) and the first fin-type electrode and the insulating film (1) disposed in the insulating layer.
Second fin-type electrodes (9) which are arranged to face each other with respect to each other and constitute a first stacked fin-type capacitor.
A semiconductor memory device having: 3. A first word line (6a) arranged in the insulating layer (2) on the channel region via a gate insulating film, and the insulating layer (6a) of the single crystal silicon layer. 3. The semiconductor memory device according to claim 1, further comprising a second word line (6b) arranged on the channel region on the side opposite to 2) via a gate insulating film. 4. The semiconductor memory device according to claim 3, wherein at least one of the first word line and the second word line is made of metal. 5. A first bit line (5a) arranged in the insulating layer (2) and connected to the source region, and a portion of the single crystal silicon layer opposite to the insulating layer (2). 5. The semiconductor memory device according to claim 1, further comprising a second bit line (5b) arranged on the surface and connected to the source region.