JPS62165936A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a layer insulating layer having a smooth surface by coating an Si substrate, to which a circuit element is shaped previously, with the layer insulating film, applying a resist and burying the irregularities of the surface and performing dry-type etching the resist and the layer insulating film at uniform speed. CONSTITUTION:The upper section of an Si substrate 1 is coated with a protective film 2, and a poly Si electrode 3 is shaped onto an active layer 10, and coated with a layer insulating film 4. A resist 7 is applied onto the whole surface, and an easy inclined plane is formed near the electrode 3. The surface of the resist is dry-type etched under conditions in which the etching rates of the insulating film 4 and the resist 7 are equal. The surface of the insulating film 4 is coated with a layer insulating film 4 consisting of the same blank again, a taper is formed at 30 deg.-50 deg. to a steep stepped section by the electrode 3, and the depth hG of the film 4 on the electrode 3 and the depth hS of the films 2 and 4 on the substrate 1 are equalized approximately. When openings are bored through etching and Al wiring is conducted, the wiring disconnection is not generated because the surface is made gentle.

Description

[Detailed description of the invention] “Industrial Application Fields” The present invention relates to a method for manufacturing a semiconductor device.

[Prior Art] Conventionally, in the manufacture of semiconductor integrated circuits (hereinafter referred to as semiconductor ICs) that have a multilayer wiring structure, contact holes formed in the interlayer insulating film with steep steps formed on the interlayer insulating film are used. Since the AQ wiring is easily disconnected and is unfavorable in terms of quality, the process includes a step of flattening the unevenness of the interlayer insulating film by forming the electrodes of the semiconductor element and the lower Ag wiring. An etch hack method has been conventionally used as a method for this planarization.

FIG. 2 is a front view showing a main part of a semiconductor [C] whose interlayer insulating film has been planarized using the conventional etch bank method.

In FIG. 2, reference numeral I denotes a silicon layer on which a semiconductor IC is formed, and a polysilicon film is formed on the silicon substrate 1 on top of the active layer 10 of the surface carrier element and on the surface protection film 2 by a known method. An electrode 3 consisting of is formed. Next, after depositing an interlayer insulating film 4 on the electrode 3 and the entire surface of the surface protection film 2, a resist ( (not shown). Furthermore, after performing dry etching on the resist surface of the substrate under conditions such that the etching speed of the interlayer insulating film 4 and the resist are equal, an interlayer insulating film 4 made of the same material as the interlayer insulating film 4 is deposited again, and then The base wafer of the semiconductor IC is completed in this step.

Thereafter, a contact hole 5a for connecting the electrode 3 of the semiconductor element and the wiring A (wiring) to be wired later on the interlayer insulation film 9H4, and the silicon A contact hole 5b for connecting the lower wiring wired on the substrate 1 and the above J wiring is opened by wet etching or dry etching.These contact holes 5a and 5b
After opening the hole, the above-mentioned A (wiring 6
is formed by, for example, a vapor deposition method. As a result, the A& wiring 6 is deposited not only on the upper surface of the interlayer insulating film 4 but also on the surface of the interlayer insulating film 1 inside the contact holes 5a and 5b, and connects the electrode 3 of the semiconductor element with the above. A (Wiring 6 is connected.

[Problems to be solved by the invention] However, using the conventional etchback method, the substrate I
When the upper interlayer insulating film 4 is planarized, the depth hG of the contact hole 5a on the electrode 3 and the silicon substrate! A difference occurs in the depth h3 of the upper contact pole 5b. As a result, the so-called step coverage of the above-mentioned Aσ wiring 6 deteriorates, and the AQ wiring is likely to be disconnected. This step coverage is as follows: Step coverage = A on the upper surface of interlayer insulating film 4 (thickness of 2 wirings 8□. =
Full leakage, □00[%.

(lC Defined by Therefore, the contact hole 5a.

It can be easily seen that as the depth of 5b increases, the thickness of the Aρ wiring formed by evaporation of the AC wiring becomes thinner, and the step coverage deteriorates.

As a method for improving this step coverage, as shown in FIG. 3, the corners of the interlayer insulating film 11 near the tops of the contact holes 5a and 5b are sloped and the interlayer insulating film 4 is removed. A method of increasing the opening radius of the upper portions of contact holes 5a and 5b has been used;
There still existed a difference in depth between contact holes 5a and 5b (h<h3), which did not substantially improve the step coverage of the wiring.

[Object of the Invention] The object of the present invention is to solve the following two problems and to provide a method for manufacturing an AQ wiring with good step coverage as described above [4]. (JζO ni ni Uro.

In a method of manufacturing a semiconductor device according to one aspect of the invention, after an interlayer insulating film is deposited on a silicon substrate on which circuit components such as semiconductor elements are formed, the interlayer insulating film is A step of applying a resist so that the uneven portions on the upper surface become a smooth surface, and a step of applying a resist so that the upper surface of the interlayer insulating film becomes smooth under the condition that the etching rate of the resist and the interlayer insulating film are equal after the step of applying the resist. The method is characterized in that it includes a step of dry etching the upper surface of the resist so that the resist has a flat surface.

Embodiment FIGS. 1(a) to 1(d) are front views showing longitudinal sections of essential parts of a semiconductor IC, showing the manufacturing process of a semiconductor IC according to an embodiment of the present invention. In Figure 1 (a) to d),
The same numbers as in FIGS. 2 and 3 are given the same numbers.

In FIG. 1(a), after the surface protective film 2 is formed on the silicon lζ temporary 1-hi, the surface protective film 2-1 is formed on the upper part of the active layer 10 of the semiconductor element in the silicon layer 1. −
) From polysilicon, the entire surface of the surface protective film 2 is coated with polysilicon. An interlayer insulating film 4 is deposited on the surface.

Next, in FIG. 1(b), in order to reduce the unevenness on the surface of the interlayer insulating film 4, a resist material 0MR85 (0MR85) with a viscosity of 45 cp (centivoise) is made so that the area near the electrode 3 has a smooth surface with a gentle slope. Product name)
Resist 7 is applied to the entire upper surface of interlayer insulating film 4 under the conditions shown in the table.
Apply.

Table 1 Further, in FIG. 1(c), under the condition that the etching speeds of the interlayer insulating film 4 and the resist 7 are equal, the upper surface of the lenostore of the substrate I is dry etched, and then the etching rate of the interlayer insulating film 4 is etched. An interlayer insulating film 4 made of the same material as the interlayer insulating film 4 is re-deposited on the upper surface to tipper the steep uneven portions caused by the electrodes 3 of the semiconductor element within a tipper angle range of 30° to 60°; Depth hG of interlayer insulating film 4 on electrode 3
and the depth hs of the surface protection film 2 on the silicon substrate l and the depth hs of the interlayer insulating film 4 are made to be approximately equal. After this, electrode 3
A contact wire having a radius 6 smaller than the radius of
The hole 5a and the contact hole 5b, which has approximately the same radius as the contact hole 5a and is for connecting the Aρ wiring and the lower wiring wired on the silicon substrate l, are formed by wet etching or dry etching. Open a hole. Further, a step of depositing A12 wiring (not shown) on the interlayer insulating film 4 is performed.

By going through the above steps, the contact on the electrode 3
The depth hQ of the hole 5a and the depth h3 of the contact hole 5b on the silicon substrate 1 are approximately equal, so that the step coverage of the above-mentioned Aρ wiring is good, and there is no disconnection of the Af2 wiring, and the semiconductor It is possible to improve the quality of IC.

[Effects of the Invention] As detailed above, according to the present invention, a method for manufacturing a semiconductor device includes the step of applying a resist so that the uneven portions on the upper surface of the interlayer insulating film become smooth surfaces; By including a step of dry-edging so that the upper surface of the interlayer insulating film becomes a smooth surface, it is possible to improve the steady coverage of the AQ wiring formed on the interlayer insulating film compared to the conventional example. reactor. Therefore, there is an advantage that there is no possibility of disconnection of the wiring, and the quality of the semiconductor IC can be improved.

[Brief explanation of the drawings] Figure 1 (a), (b), (c) 7Ez and (d)
1 is a front view showing a vertical cross section of a main part of an integrated circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are front views showing a vertical cross section of a main part of a conventional semiconductor integrated circuit. ■...Silicon substrate, 2. Surface protective film, 3... Electrode of semiconductor element, 4... Interlayer insulating film, 5a, 5b... Contact hole, 7... Resist.

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device having a multilayer wiring structure of at least two layers, after depositing an interlayer insulating film on a silicon substrate on which circuit components such as semiconductor elements are formed,
A step of applying a resist so that the uneven portion on the upper surface of the interlayer insulating film becomes a smooth surface, and a step of applying a resist to the upper surface of the interlayer insulating film under the condition that the etching rate of the resist and the interlayer insulating film are equal after the step of applying the resist. A method for manufacturing a semiconductor device, comprising the step of dry etching the upper surface of the resist so that the upper surface becomes a smooth surface. (2) In the dry etching step, dry etching is performed so that the depth of the interlayer insulating film on the electrode of the circuit component element is approximately equal to the depth of the interlayer insulating film on the silicon substrate on which the electrode is not formed. A method for manufacturing a semiconductor device according to claim 1, characterized in that: