JPS62165263A - Memory control system - Google Patents

Abstract

PURPOSE:To extend an address space by switching the address selectively to the access address from the second processor and that from the first processor to access a read/write memory. CONSTITUTION:When the first processor 1 writes data in a RAM 4, the first processor 1 issues a prescribed address and a write instruction (R/W=1), and the address is led to an address selector 5, and contention to the access address from the second processor 2 is avoided to perform the write access to the RAM 4. At this time, write data (W/D) is issued and is supplied to the RAM 4 through a data selector 6. When the first processor 1 accesses a ROM 3, the first processor 1 issues a prescribed address and a read instruction (R/W=0), and a decoder 7 issues a chip select signal to the ROM 3, and contents of the ROM 3 are read. Thus, the address space in the first processor side is practically extended.

Description

[Detailed Description of the Invention] [Summary] In a data processing system in which there is a processor that accesses a read-only memory and a memory corresponding to a so-called write-only memory, the read-only memory and the write-only memory are accessed. It is disclosed that the address space is substantially expanded by configuring the address space to be given redundantly with the only memory address.

[Industrial application field]

The present invention provides a memory control method, particularly a write
Part of the address of RAM corresponding to only memory,
The present invention relates to a memory control method in which the addresses of a read-only memory are configured to overlap and the address space is expanded.

[Prior Art] Conventionally, in an address space accessed by, for example, a microprocessor, ROM addresses and RAM addresses have been clearly distinguished.

For this reason, for example, when it is necessary to enlarge the RAM jJI area, it is necessary to prepare a special table for expanding addresses.

[Problem that the invention seeks to solve]

There are cases where it is not necessarily desirable to specially prepare the address extension means, and countermeasures for such cases are required.

[Means for solving problems]

The present invention solves the above-mentioned problems.2 For example, in a facsimile machine, one of the plurality of processors has a RAM.
When a configuration is adopted in which image information is unilaterally written on the RAM and another processor reads and processes the image information from the RAM.

The focus is on the fact that the RAM is a so-called write-only memory from the perspective of the former processor.

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 1 is the first processor, 2 is the second processor, and 3 is R
OM is accessed by the first processor, and 4 is RAM (corresponding to read/write memory according to the present invention), which is a write-only memory from the perspective of the first processor. , 5 is the address
selector.

6 represents a data selector, 7 represents a decoder, and 8 and 9 each represent a selector.

When the first processor 1 writes to the RAM 4, it issues a predetermined address.

Issue a write instruction (R/W=1). As a result, the current address is guided to the address selector 5 and the second
A write access is made to the RAM 4, avoiding conflict with the access address from the processor 2.

At this time, write data (W/D) is issued and supplied to the RAM 4 via the data selector 6.

When the first processor l accesses the ROM3, it issues a predetermined address and also issues a read instruction (R/W=O
) is emitted. As a result, the decoder 7 issues a chip select signal to the ROM 3, and the contents of the ROM 3 are read.

[Effect]

As described above, even if the same access address is issued in the access to the ROM 3 by the first processor 1 and the access to the RAM 4 by the first processor 1, the correct object is accessed correctly.

Access to RAM 4 from first processor 1 and access to RAM 4 from second processor are selected by address selector 5, data selector 6, selector 8, and selector 9. Any means can be used to eliminate competition in the selection, and one of them may have priority;
Either one may prohibit the other's access in advance so that it can access itself.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention. Code 1 in the figure.
2, 3, 4, 5, 6, 7, 8.9 correspond to FIG. 1, and 10 is R accessed by the second processor.
OM, 11 represents a decoder, 12 represents a storage memory, and 13 represents a line-to-line interface section. Also, 14 is a selection system between the first processor l and the second processor 2? 11
represents the department.

The operation in the case shown in FIG. 2 is basically the same as in the case shown in FIG.
The second processor 2 is equipped with ROM10.
It may be considered that l0, RAM 4, and storage memory 12 are accessed using different addresses. Regarding writing to the RAM 4 from the first processor 1 side, it goes without saying that data from the first processor 1 can be written.

Data from the line-to-line interface section 13 is also written.

Writing to the RAM 4 from the first processor 1 side is notified to the second processor 2 by an interrupt. The reverse is also written and notified in the transfer data to the first processor 1.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to substantially expand the address space on the first processor side.

[Brief explanation of drawings]

FIG. 1 shows the principle configuration of the present invention, and FIG. 2 shows the configuration of an embodiment of the present invention. In the figure, 1 and 2 are processors, and 3 is a read-only
Memory, 4 is read/write memory. 5 is an address selector, and 6 is a data selector. 7 represents a decoder, and 8.9 represents a selector.

Claims (1)

[Claims] A read-only memory (3) comprising a first processor (1) and a second processor (2), and accessed by the first processor (1); A data processing system comprising: a read/write memory (4) into which information is written by the first processor (1) and from which the written information is read by the second processor (2); The read-only memory (3) and the read-write memory (4) are configured such that at least some of their addresses overlap in the address space viewed from the processor (1), and the addresses of the read-only memory (3) and the read-write memory (4) overlap. The access address from the second processor (2) and the access address from the first processor (1) are configured to indicate read access or write access when accessing the address in the processor (1). A memory control system characterized in that the read/write memory (4) is accessed by selectively switching between the two.