JPS6216479B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a voltage hold circuit.

MOS transistors, especially integrated MOS transistors, have various types of parasitic capacitance.Although there are ways to actively utilize parasitic capacitance, the presence of parasitic capacitance is generally not welcomed. The parasitic capacitance includes the capacitance C _GS between the gate electrode and the source electrode, the capacitance C _GD between the gate electrode and the drain electrode, the junction capacitance C S between the source electrode and the substrate, and the capacitance C _S between the drain electrode and the substrate. There is a junction capacitance C _D between. Capacity C _GS , C _GD
is the parasitic capacitance C _iG due to side diffusion (a phenomenon in which the diffusion layer wraps around during ion implantation)
It is determined by the capacitance _COX , which is determined by the thickness and area of the gate oxide film, depending on _S , C _iGD and the manner in which the channel is formed.

When MOS transistors having the various parasitic capacitances described above are used as switching means in a sample-and-hold circuit, they have the disadvantage of causing level fluctuations.

FIG. 1 shows a conventional sample and hold circuit, and FIG. 2 shows a time chart. In the figure, TR10, DCO
is an enhancement type MOS transistor, TR10 is the main transistor for sample and hold, and DCO is a dummy transistor to be described later. First, during sampling, the strobe (clock) signal _φ1 activates the MOS transistor TR1.
0 is turned on, and the input V _i is sampled by the capacitor C. During hold, the strobe signal _φ1 is set to “0” and the MOS transistor TR10
Turn off. The capacitor C holds the charging voltage at this time. The relationship between the strobe signal _φ1 and the terminal voltage V _C of the capacitor C is as shown in FIG. That is, starting from the time when φ ₁ =1, V _C rises and reaches V _C =V _i after a time constant. However, when the transistor TR10 turns off in the direction of _φ1 being "0", the configuration becomes such that the parasitic capacitance _CGD is connected in parallel to the capacitor C, and a part of the electric charge charged in the capacitor C is transferred to the parasitic capacitance. C Transfer to _GD (charge share). The voltage drop amount ΔV _C due to this charge sharing is ΔV _C =C _GD・V _C /C+C _GD ≒C _GD・V _C /
C...(1) becomes. This ΔV _C is clearly a circuit error.

The value of ΔV _C will be considered below. In order to shorten the charging time, the on-resistance of TR10 must be set to several hundred ohms or less, and the channel ratio W/L of TR10 must be designed to be extremely large. For example, if W/L=6, L=4μm, W=24μm
m, and C _GD = approximately 0.008 pF. In this way, increasing W also increases _CGD . Also, in order to reduce the error C _GD・V _C /C, it is sufficient to increase C, but the normal
There are limits to creating a monolithic sample-and-hold circuit using LSI integrated circuit technology;
It is about 10pF. For example, C _GD =0.01pF, C=
If it is 20pF, ΔV _C will be 0.05%. The sample and hold circuit output is usually input to an AD converter. However, the above numbers are based on 10-bit AD
In the case of a converter, it corresponds to 1/2LSB and cannot be ignored as an error.

In order to reduce the amount of variation mentioned above, a dummy transistor DCO is provided on the output side. The transistor DCO is composed of an enhancement type MOS transistor, has a channel width that is half the width of the channel of TR10, and has a configuration in which the drain end and the source end are short-circuited. The gate is controlled by a signal φ ₁ ', which is an inverted signal of φ ₁ . In this case, the capacitance of the dummy transistor DCO when viewed from the output terminal of the capacitor C is _CGD . However, with this method, parasitic capacitance fluctuates due to device dimensions and process variations, and there is a limit to compensation for voltage fluctuations.

Therefore, a chopper type comparator as shown in FIG. 3 also has similar drawbacks. In Figure 3, TR1 to TR6 are EMOS switches, DC1 to DC
4 is a dummy EMOS transistor, _C0 to _C3 are coupling capacitors, A1 to A5 are amplifiers consisting of E/DMOS inverters, _φS and _φC are separate two-phase clocks,
V _I is the input analog voltage, V _R is the reference voltage, and C _SO is the parasitic capacitance. Figure 4 shows a time chart.

TR1, TR3 to TR6 are turned on at the timing of "1" level of φ _S (sampling cycle), and the inputs of amplifiers A1 to A4 are bias voltage V _B
is set to Therefore, C _{O (} V _I - V _B )
is charged. Next, TR2 is turned on at the timing of the "1" level of φ _C (comparator cycle), and the input side potential of the amplifier A1 changes from V _B by V _R -V _I. This fluctuating voltage is amplified by amplifiers A1 to A5, and the logic amplitude level of the A5 output is determined according to the polarity of V _R -V _I. Naturally, interval T ₁ is the sampling interval, interval T ₂
is the comparison interval.

If there are no dummy transistors DC1 to DC4,
As shown in Figure 4c, the interval T ₃ where φ _S = φ _C = “0”
Then, the input side voltage of the amplifier A1, that is, the bias voltage V _B , decreases by ΔV _B =-C _GD · V _B /C _SO (2) due to charge sharing. In order to reduce this ΔV _B , dummy transistors DC1 to DC4 are provided. However, for the same reason as mentioned above, sufficient compensation cannot be obtained due to variations in capacitance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage hold circuit that further reduces fluctuations in hold voltage due to parasitic capacitance.

The gist of the present invention is to connect a plurality of MOS transistors with different channel ratios (channel widths) in parallel, and to switch from an on state to an off state stepwise in descending order of channel ratio. This minimizes the drop in holding voltage due to charge shear. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 5 is a diagram showing an embodiment of the present invention.

The sources and drains of the EMOS transistors TR11 and TR12 are connected in parallel, and the strobe signal φ ₁ -1 drives TR11, and the strobe signal φ ₁ -0 drives TR12. A dummy EMOS transistor DC5 driven by the strobe signal φ ₁ -1' is provided on the output side. TR11 and TR12 are configured such that the channel ratio of TR11≫the channel ratio of TR12. Therefore, parasitic capacitance C _GD1 of TR11 ≫ parasitic capacitance C _GD2 of TR12, and TR11
The on-resistance of TR12 is the on-resistance of TR12.

FIGS. 6a and 6b show the control procedure, and FIG. 7 shows a time chart. First, according to Figure 7 a and b, TR
11, Turn on TR12. Then, the sixth
Turn TR11 from on to off as shown in Figure a. At this time, if TR12 were not present, a voltage drop of ΔV _C would occur in the output V _C due to charge sharing as shown in Figure c. However, by providing TR12, e
As shown in the figure, the output V _C temporarily drops, but since TR12 remains on,
It rises as if by a time constant of (ON resistance of TR12) x C. Then, when φ ₁ -0 becomes "0", TR12 turns from on to off, charge sharing occurs again, and V _C changes in this way. At this time, as shown in Figure 6b, the parasitic capacitance C
_GD2 has an influence, but since C _GD2 is set small, the amount of charge share itself is small, and the drop in voltage level is small. Incidentally, since the overall on-resistance can be made small while keeping the charge shear small, the charge time (pre-charge time) can be made sufficiently short regardless of the charge shear.

The embodiments of the invention described above can be applied to numerous circuits. FIG. 8 shows an embodiment applied to the chopper type comparator shown in FIG. FIG. 9 is a partial operation explanatory diagram, FIG. 10 is an embodiment diagram of a timing signal generation circuit that generates a timing control signal, and FIG.
FIG. 1 is a time chart of the embodiment shown in FIG.
The difference in the configuration in Figure 8 from the configuration in Figure 3 is TR3
~TG1 and TS1 connected in parallel instead of TR6
~The point is that TG4 and TS4 are provided. TS1 and TS
1. The relationship between TG2 and TS2,..., TG4 and TS4 is the same as the relationship between TR11 and TR12 in FIG. That is, a magnitude relationship is attached to the channel ratio. Strobe signal φ ₁ −2 to the gates of TG1 to TG4, control signal φ ₁ −1 to the gates of TS1 to TS4, control signal φ ₁ − to the gate of TR1
0, control signal φ ₂ to the gate of TR2 -0, DC1
~The control signal φ ₂ −1 to the gate of DC4 is the 11th
It has a timing relationship as shown in the figure. The circuit for obtaining this timing relationship is the generating circuit shown in FIG.

The generation circuit in FIG. 10 includes time delay inverters 52, 53-1, 53-2, 54-1, 54-
2, 56, 57, 55-1, 55-2 and Noah Gate 50-1, 50-2, 50-3, 50-4,
It consists of AND gate 51. The generating circuit is designed to obtain the relationship shown in FIG. 11 based on the clock CK. That is, φ ₁ −2,
φ ₁ -1, φ ₁ -0 are time τ ₁ from clock CK.
φ ₁ -1 has a pulse width τ ₂ larger than that of φ ₁ -2. φ ₁ -0 has a pulse width τ ₃ larger than that of φ ₁ -1. φ ₂ −1 is φ ₁ −
It lags behind 0 by τ ₄ . Further, φ ₂ -0 is the output of the AND gate 51 which receives φ ₂ -1' and φ ₂ -1 as inputs. φ ₂ -0 has a delay of time τ ₅ from φ ₂ -1.

In the circuit configuration of FIG. 8, the operation of the inverter (amplifier) A1 will be explained in FIG. 9 a, b,
It is shown in c. In Fig. 9a, inverter A1
is composed of a driver EMOS transistor TE1 and a load EMOS transistor TD1. C _S1 and C _S2 are parasitic capacitances. Figure b is TG1
is off, TS1 is on, and inverter A1 is operating. Both R _e and R _l are on-resistances. Figure c shows the state when both TG1 and TS1 are off. The reduction in the amount of decrease in the output voltage due to this configuration follows the same process as the operation of the embodiment shown in FIG.

FIG. 12 shows an example in which the embodiment of the present invention is applied to the input stage of the comparator shown in FIG.
EMOS transistor TR driven and controlled by φ ₁ -0' and φ ₂ -0' in parallel to TR1 and TR2
1' and TR2' are newly added. Timing relationship between φ ₁ -0 and φ ₁ -0', φ ₂ -0 and φ ₂
The timing relationship with -0' is the same as in FIG. 5, and the operation is also the same.

FIG. 13 is a modification of FIG. 8, including a drive EMOS transistor TE2, a load EMOS transistor TD2, and an EMOS transistor TG5, TG.
6, TG7, TG8, TS9, TS10, TS11,
Consists of TS12. 100 is a bias voltage supply line. TG5 to 8 and TS9 to TS12 have different channel ratios as described above.
The difference between FIG. 13 and FIG. 8 is whether the bias is self-biased or externally biased, and other aspects are basically the same.

According to the above embodiment, two MOS transistors are used, but the number may be expanded to two or more.

According to the present invention, a voltage hold circuit without voltage fluctuation could be provided.

[Brief explanation of the drawing]

Figure 1 is a diagram of a conventional example, Figure 2 is a time chart,
FIG. 3 is another conventional example diagram, FIG. b, c, d, e
is a time chart, FIG. 8 is another embodiment of the present invention, FIGS. 9 a, b, and c are operation explanatory diagrams, FIG. 10 is a partially detailed embodiment diagram, and FIG.
FIG. 12 and FIG. 13 are diagrams of other embodiments.
TR11, TR12...EMOS transistor, V _i
...Analog input voltage, DC5...For dummy
EMOS transistor.

Claims (1)

[Claims] 1 A plurality of MOS transistors with mutually different channel ratios are provided in parallel between the analog voltage application terminal to which the analog voltage to be held is applied and the input terminal of the capacitance component for hold, and the plurality of MOS transistors are connected during hold. A voltage hold circuit comprising means for charging the analog voltage to the hold capacitance component by sequentially turning it on and off in descending order of channel ratio.