JP2771158B2 - Clock generator - Google Patents

Description

The present invention relates to an MIS field effect transistor circuit,
In particular, the present invention relates to a clock generator capable of outputting an output signal boosted above a power supply. [Prior Art] Generally, an MIS type field effect integrated circuit device is controlled by some external clock, but has an internal delay circuit, generates some internal clocks, and controls internal operation. It is usual to do. In general, the output of the internal clock has a power supply potential (Vcc) at a high level and a ground potential (V _G ) at a low level. However, for example, in the case of an N-channel MIS type field effect integrated circuit device, a clock generator whose high-level output potential is boosted to a power supply potential (Vcc) or more may be required. This is an N-channel MIS type field effect transistor (MISFE
Power supply potential (V)
When cc) is applied, the output potential, that is, the potential of the source terminal, increases only up to the maximum of the power supply potential (Vcc) -the threshold voltage (V _T ) of the driver transistor.
As a clock supplied to the gate of the MISFET for charging the contact you want to charge a certain contact to the power supply potential (Vcc), the power supply potential (Vcc) + MISFET clock generator capable of high-level output V _T more than the potential of the Is required. For example, in the case of a dynamic RAM using an N-channel MOS FET, a word line or the like is often boosted to a power supply potential or higher, since the purpose is to charge (write) the memory cell capacity to the power supply potential. In many cases, the potential of the data transfer gate is boosted to a level equal to or higher than the power supply potential. As a result, the transfer speed can be improved as well as the final potential after charging. FIG. 3 illustrates a conventional example of a clock generator that outputs a high level higher than the power supply potential in the case of the above-described dynamic RAM. Q _{1 to} Q ₁₁ are N-channel MOSFETs, and C ₁ and C ₂ are capacitive elements φ _P
The high level of the clock in the standby, the phi _IN input clock, phi _2, phi ₃ is output step-up clock. In the dashed line
MOSFET group D is a delay circuit of one, standby time keeps the contacts N ₂ to a high level by phi _P, after a delay circuit in the case where the input clock phi _IN changes from the low level to the high level, the contacts N ₂ It has the function of lowering the potential of the device to a low level. FIG. 4 shows a waveform diagram when the clock generator of FIG. 3 is activated. When φ _IN changes to a high level (Vcc), N ₂ is kept at a high level in advance as described above, so that MOSFET Q ₆ is turned on, contact N rises according to φ _IN and MOSFETs Q ₈ , Q ₁₀
Will be turned on. However, contact N ₂ is lowered at time t ₁ after the time delay phi _IN there is also increased, until the time t ₁ for a low level, MOSFET Q _9, Q ₁₁ is also turned on,
This time, the contact N _1, .phi.out includes a MOSFET Q ₈ and Q ₉ also Q ₁₀
The ratio of the ON resistance of Q ₁₁ is appropriately set, thereby maintaining the low level. That is, in this period, the potential difference across the capacitive element C ₁ is preferably would be charged to a power supply voltage, and then lowered contact N ₂ at time t _1, MOSFET Q _9,
Q ₁₁ is the potential of the contact N ₁ is increased by turning off. Contact N for MOSFET Q ₆ is turned off in the same manner at this point is a floating, capacitor element C ₁ functions as a bootstrap capacitance, the potential of the contact N is lifted above the power supply potential. Also φout at the same time the contact N ₁ starts to rise starts to increase, there is also the gate potential of the MOSFET Q ₁₀ (contact N) indicates the power potential + V _T above, ultimate potential at the power supply potential. Further, at time t ₂ , φ ₂ rises and MOSFET Q
_{When 7} is turned on, the potential of the contact N drops to the ground potential, the MOSFETs Q ₈ and Q ₁₀ are turned off, and φout is in a floating state at a high potential. Then or almost simultaneously, φ
Φou floating due to the rise of ₃
The potential of t is further raised, and a high level higher than the power supply potential is output. [Problems to be Solved by the Invention] The conventional clock generator described above requires
When boosted by _3, it has a number of drawbacks to drop the potential of the contact N to the ground potential by MOSFET Q _7. First, it is not suitable for high-speed operation. That is, when the time interval between φ _IN and φ ₂ becomes short, the potential of the contact N rises through the MOSFET Q ₆ as φ _IN rises, but before reaching the sufficient potential, the MOSFET Q ₇ It will start dropping toward the ground potential. as a result
Contact N ₁ , φout due to insufficient gate level of MOSFET Q ₈ , Q ₁₀
While φ ₃ rises dull potential of φout does not rise enough
However, there is a possibility that the result will not be increased to a predetermined potential. In such a situation, MO
It becomes sensitive to fluctuations due to manufacturing variations in V _T and β of SFET, variations in characteristics deteriorating pending. Second, if the Rikubasu the contact output φout was present, the contact N after phi ₂ is raised at the ground potential,
Even if φout abnormally drops due to leak current, there is no bus to charge for compensation. Therefore, in a mode in which it is necessary to maintain φout at a high level for a long time, the probability of occurrence of a characteristic failure increases. Third, there is a disadvantage that φout is slightly reduced by the total capacitance C _S when the contact N is lowered to the ground potential. [Means for Solving the Problems] A clock generator according to the present invention comprises an MIS having a drain connected to a power supply terminal and a source connected to an output terminal.
Means for clamping a gate potential of the MIS field effect transistor to a potential of the power supply terminal before the boosting circuit is activated in a clock generator in which the field effect transistor forms a driver and has a booster circuit at an output terminal. It is characterized by having. Next, the present invention will be described with reference to the drawings. First
The figure shows a circuit diagram of one embodiment of the present invention. Almost in the same manner as in FIG.
₁ to Q ₁₂ are N-channel MISFET, C _1, C ₂ is the capacitance element, phi _P is at the high level of the clock in the standby, the phi _IN input clock, phi ₃ is a step-up clock. FIG. 2 shows a waveform diagram when the clock generator of this embodiment is activated. After the input clock φ _IN rises, the potential of the contact N is boosted to the power supply potential or higher by the capacitive element C ₁ , and the operation of each part up to the point where φ out rises to the power supply potential is exactly the same as the description of the conventional example. It is. phi ₃ is increased, the contact N ₄ at a time t ₃ when boosting the φout than the power supply potential even when the power supply potential Vcc + V
The potential at the contact N, which has been boosted to _T or more and has been at the power supply potential Vcc + _VT or more, is clamped to the power supply potential. [Effects of the Invention] As described above, the present invention provides a
Rather than ground potential the potential of the contact N _3, for clamping to the power supply potential, even jammed between clock phi _IN and the clock phi _3, while the potential of the contact N ₃ as described in the prior art does not sufficiently rise Φout does not stay at a fatal low level as a result,
t is maintained at Vcc- _VT or more. Therefore, among manufacturing variations such as _VT and β, φ
Also packed between _IN -.phi ₃ falling into fatal outcome is facing high-speed operation without. Further, even if a leak bus exists at the contact of φout, the contact N ₃
The potential of is at the power supply potential rather than ground potential, MOSFET Q ₁₀ is turned on when φout falls to the power supply potential -V _T, will be to compensate for leakage current, as in the conventional example, until catastrophic potential It does not descend. Also compared with the conventional example, since the amplitude of the contact N ₃ during .phi.out boost is small, the small effect of the withdrawal by the coupling capacitance C _S of the contact N ₃ and .phi.out. Further, since the potential of the contact N3 is clamped to the power supply voltage and φout is boosted by the same internal signal, high-speed operation can be realized. In this case, since the output φout drives the word line, the load is reduced. Since the capacitance is large and the potential rise is slightly delayed, the output signal does not leak from the output terminal to the power supply.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment, FIG. 3 is a circuit diagram showing a conventional example, FIG. The figure is a waveform diagram for explaining the operation of the conventional example. _{Q 1 ~Q 12 ...... MOSFET, C} 1, C 2, C 3 ...... capacitive element, C _S ...... parasitic capacitance elements, N ₁ ~N ₄ ...... contact name, φ _IN ...... input clock, φout ...... An output clock, φ _P ... A clock that is at a high level during standby, and φ ₂ , φ ₃ ... A clock for boosting, respectively.

Claims (1)

(57) [Claims] A transistor connected between a power supply terminal and a word line; a capacitor having one end connected to the word line; and driving the gate of the transistor at a first timing to be larger than a power supply voltage so that the word line is driven. First control means for driving to a power supply voltage; and at a second timing after the first timing, the level of the other end of the capacitor is set to a power supply voltage to drive the word line to a power supply voltage or higher, and A second control means for clamping a gate potential of the transistor to a potential of the power supply terminal.