JP3303761B2 - Boost circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a booster circuit incorporated in a semiconductor integrated circuit or the like and a method of controlling the booster circuit.

[0002]

2. Description of the Related Art A D-RAM (Dynamic-Random Access Memory), which is a kind of semiconductor memory (storage element), generally has an NMOS (N-channel Metal Oxide Semimic) as a memory cell transistor.
Onductor) transistors (NMOS field effect transistors) are often used.

When writing information of logic "1" to a memory cell in such a DRAM, an external power supply supplied from outside is applied to a gate electrode of a transfer transistor of the memory cell in order to eliminate a threshold loss of the memory cell transistor. It is necessary to apply a voltage higher than the voltage.

Therefore, in such a semiconductor device requiring a voltage higher than the external power supply voltage, a high voltage generating circuit for boosting the external power supply voltage to generate a high voltage is provided therein. Generally, such a high voltage generating circuit performs a pumping operation on the capacitance to generate a high voltage.

[0005]

FIG. 4 is a connection diagram showing an example of a conventional booster circuit. FIG. 5 is a timing chart showing how the waveform of each part of the booster circuit shown in FIG. 4 changes. In the configuration shown in FIG.
Detects the boosted voltage VXD. When the boosted voltage VXD falls below an arbitrary level, the detection signal OSUP becomes active (high level).

When the detection signal OSUP goes high, NM
The OS transistor 44 is turned on, and the voltage determined by the resistance dividing section 45 becomes a PMOS (P-channel Metal Oxide).
The voltage is applied to the gate electrode of a transistor (PMOS field effect transistor) 46, and the transfer gate 47 is turned on.

At this time, the connection point 50 is fixed to the ground voltage, and the connection point 53 is fixed to the power supply voltage. Further, the NMOS transistor 48 and the PMOS transistor 49 that have stopped the ring oscillator 43 are turned off.

At the same time, the ring oscillator 43 generates a pumping clock VBOS input to the pumping step-up unit 42 by the voltages at the connection points 50, 53 and 54 determined by the drain voltage of the PMOS transistor 46 and the voltages of the current control units 51 and 52. I do.

That is, when the ring oscillator 43 is not operating, the connection points 50 and 53 are fixed to the ground voltage or the power supply voltage, respectively. However, when the detection signal OSUP is turned on, the NMOS transistor 48 and the PMOS transistor 49 are turned off. Become.

Immediately after the transfer gate 47 is turned on, the voltages at the connection points 54 and 50 are once reduced to a level close to the ground voltage by the wiring capacitance ratio. After that, the first pumping clock VBOS is output in the process of obtaining a voltage corresponding to the drain voltage of the PMOS transistor 46 and the levels of the current control units 51 and 52.

The output of the pumping clock VBOS has an arbitrary constant cycle after the voltage at the node 54 is stabilized. However, the above configuration has a problem that the first output is delayed.

After the drop of the boosted voltage VXD, it is better that the time until the drop is detected and the voltage is boosted by pumping is shorter, so that the first first pumping clock VBOS is particularly slow.

The present invention has been made under such a background, and provides a booster circuit that outputs a pumping clock at a high speed when a decrease in boosted voltage is detected, and a method of controlling the booster circuit. The purpose is.

[0014]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, the first capacitor is charged repeatedly by a pumping operation based on an input clock. Pumping means for generating a boosted voltage, a voltage detecting means for generating a detection signal when the boosted voltage falls below a preset reference value, and a clock for generating the clock at a predetermined period together with the generation of the detection signal. ; and a generation unit, the clock generating means, together with just the detection signal generator generates the clock in a short period than the predetermined period, a control terminal for controlling the cycle of the clock, to the control terminal Is before
Amplifying the detection signal and controlling the voltage by resistance division
Received by the gate electrode of the insulated gate field effect transistor.
The drain of the insulated gate field effect transistor
And a third terminal having one end connected to the output terminal of the voltage detecting means.
2 is connected to the other end of the capacitor . According to the second aspect of the present invention, the pumping means generates a boosted voltage by repeatedly charging the first capacitor by a pumping operation based on an input clock, and the boosted voltage is set in advance. Voltage detection means for generating a detection signal when the reference value falls below
Clock generating means for generating the clock having a predetermined frequency together with the generation of the detection signal, wherein the clock generating means generates the clock having a frequency higher than the predetermined frequency for a predetermined period from the generation of the detection signal. And a control terminal for controlling the frequency of the clock, wherein the control terminal amplifies the detection signal and has a resistor.
The voltage controlled by the division is transferred to an insulated gate field effect transistor.
Insulated gate field effect received at the gate electrode of the transistor
And the output of the voltage detecting means.
The other end of the second capacitor, one end of which is connected to the
It is characterized by being continued . Further, in the invention according to claim 3, the clock generating means outputs the control terminal.
The insulated gate field effect transistor is a ring oscillator receiving a gate electrode, the driving current of which is controlled based on the force .

[0015]

DETAILED DESCRIPTION OF THE INVENTION First Embodiment Hereinafter, the present invention will be described. FIG. 1 is a connection diagram illustrating a configuration of the booster circuit according to the first embodiment of the present invention. FIG. 2 is a timing chart showing how the waveform of each part of the booster circuit shown in FIG. 1 changes.

In FIG. 1, reference numeral 1 denotes a voltage detection circuit.
The voltage detection circuit 1 detects the voltage of the boosted voltage VXD and activates the detection signal OSUP (high level) when the boosted voltage VXD falls below an arbitrary level.

When the detection signal OSUP goes high, NM
The OS transistor 4 is turned on, the voltage determined by the resistance dividing unit 5 is applied to the gate electrode of the PMOS transistor 6, and the PMOS transistor 6 is turned on.

When the PMOS transistor 6 is turned on, the transfer gate 7 is turned on, thereby fixing the connection point 10 to the ground voltage and the connection point 13 to the power supply voltage. In this way, the NMOS transistor 8 and the PMOS transistor 9 that have made the ring oscillator 3 inactive are turned off.

At the same time when the NMOS transistor 8 and the PMOS transistor 9 are turned off, the voltage at the node 14 is temporarily increased by the coupling capacitance 15. This prevents a temporary voltage drop due to the capacitance ratio when the connection points 14 and 10 are connected.

The voltages at the connection points 14, 13, and 10 are
Drain voltage and current control unit 1 of S transistor 6
A voltage determined by the voltages 1 and 12 is reached, whereby the first pumping clock VBOS input to the pumping step-up unit 2 is generated from the ring oscillator 3 at high speed. Therefore, the speed from the drop of the boosted voltage VXD to the recovery of the boosted voltage VXD to the original voltage is increased.

B. Second Embodiment FIG. 3 is a connection diagram showing a configuration of a booster circuit according to a second embodiment of the present invention. In FIG. 3, reference numeral 21 denotes a voltage detection circuit. The voltage detection circuit 21 detects the voltage of the boosted voltage VXD, and activates the detection signal OSUP (high level) when the boosted voltage VXD falls below an arbitrary level.

When the detection signal OSUP goes high, NM
The OS transistor 24 is turned on, and the voltage determined by the resistance divider 25 is applied to the gate electrode of the PMOS transistor 26, and the PMOS transistor 26 is turned on.

When the PMOS transistor 26 is turned on, the transfer gate 27 is turned on, thereby fixing the connection point 30 to the ground voltage and the connection point 33 to the power supply voltage. Thus, the NMOS transistor 28 and the PMOS transistor 29 that have made the ring oscillator 23 inactive are turned off.

NMOS transistor 28 and PMOS
At the same time that the transistor 29 is turned off, the capacitor 3
5, the voltage at the connection point 34 is temporarily increased.
As the capacitor 35, for example, in a semiconductor integrated circuit, a conductive layer is formed as one electrode, and a semiconductor region below the conductive layer is formed as the other electrode. Is increasing. Such a configuration prevents a temporary voltage drop due to the capacitance ratio when the connection points 34 and 30 are connected.

The voltages at the connection points 34, 33, 30 are
Drain voltage and current control unit 3 of S transistor 26
The voltage reaches the voltage determined by the voltages 1 and 32, whereby the ring oscillator 23 generates the first pumping clock VBOS input to the pumping step-up unit 22 at high speed. Therefore, the speed from the drop of the boosted voltage VXD to the recovery of the boosted voltage VXD to the original voltage is increased.

As described above, according to the present invention, pumping means for generating a boosted voltage by repeatedly charging the first capacitor by a pumping operation based on an input clock, In a booster circuit including a voltage detection unit that generates a detection signal when the voltage falls below a preset reference value and a clock generation unit that generates a clock having a predetermined period together with the generation of the detection signal, The period of the clock generated by the generating means is controlled to be shorter than a predetermined period. Further, in a booster circuit in which the period of the clock generated by the clock generator decreases in proportion to the voltage value of the detection signal, the output terminal of the voltage detector and the control terminal are connected by the second capacitor. When a voltage drop is detected, a boosting circuit that outputs a pumping clock at high speed and a control method of the boosting circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a connection diagram illustrating a configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing how a waveform of each part of the booster circuit shown in FIG. 1 changes.

FIG. 3 is a connection diagram illustrating a configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 4 is a connection diagram illustrating an example of a conventional booster circuit.

FIG. 5 is a timing chart showing how the waveform of each part of the booster circuit shown in FIG. 4 changes.

[Explanation of symbols]

 1, 21, 41 Voltage detection circuit 2, 22, 42 Pumping booster 3, 23, 43 Ring oscillator 4, 24, 44 NMOS transistor 5, 25, 45 Resistance divider 6, 26, 46 PMOS transistor 7, 27, 47 Transfer gates 8, 28, 48 NMOS transistors 9, 29, 49 PMOS transistors 10, 30, 50 Connection points 11, 31, 51 Current control units 12, 32, 52 Current control units 13, 33, 53 Connection points 14, 34, 54 Connection point 15 Coupling capacitance 35 Capacitor OSUP detection signal VXD Boost voltage

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/07 G11C 11/413 H01L 21/822

Claims (3)

(57) [Claims] 1. A pumping means for generating a boosted voltage by repeatedly charging a first capacitor by a pumping operation based on an input clock, and providing a boosted voltage when the boosted voltage falls below a preset reference value. Voltage detection means for generating a detection signal, and clock generation means for generating the clock having a predetermined period together with the generation of the detection signal, wherein the clock generation means has a period shorter than the predetermined period immediately after the generation of the detection signal in addition to generating the clock has a control terminal for controlling the cycle of the clock, before
The control terminal amplifies the detection signal and performs resistance division.
More controlled voltage with insulated gate field effect transistor
Insulated gate field effect transformer received at the gate electrode of the
The drain of the transistor and the output terminal of the voltage detecting means.
The other end of the second capacitor to which one end is connected is connected
Boosting circuit, characterized in that that. 2. A pumping means for repeatedly charging a first capacitor by a pumping operation based on an input clock to generate a boosted voltage, and comprising: a booster for generating a boosted voltage when the boosted voltage falls below a preset reference value; Voltage detection means for generating a detection signal; and clock generation means for generating the clock having a predetermined frequency together with the generation of the detection signal, wherein the clock generation means performs the predetermined time period from the generation of the detection signal. A control terminal for generating the clock having a frequency higher than the frequency and controlling the frequency of the clock; the control terminal increasing the detection signal;
Insulated gate type for voltage controlled by width and resistance division
The insulating gate received at the gate electrode of the field effect transistor
The drain of the gate type field effect transistor and the voltage detection
A second capacitor having one end connected to the output terminal of the informing means
The booster circuit is connected to the other end of the booster. 3. The control terminal according to claim 2, wherein
3. The booster circuit according to claim 1, wherein the booster circuit is an insulated gate type field effect transistor gate electrode receiving type ring oscillator whose drive current is controlled based on the output of the booster circuit.