JPS62163349A - Chip carrier for electronic element - Google Patents

Chip carrier for electronic element

Info

Publication number
JPS62163349A
JPS62163349A JP528986A JP528986A JPS62163349A JP S62163349 A JPS62163349 A JP S62163349A JP 528986 A JP528986 A JP 528986A JP 528986 A JP528986 A JP 528986A JP S62163349 A JPS62163349 A JP S62163349A
Authority
JP
Japan
Prior art keywords
plating
recessed section
exposed
acceptor
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP528986A
Other languages
Japanese (ja)
Inventor
Takeshi Kano
武司 加納
Toshiyuki Yamaguchi
敏行 山口
Kaoru Mukai
薫 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP528986A priority Critical patent/JPS62163349A/en
Publication of JPS62163349A publication Critical patent/JPS62163349A/en
Pending legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)

Abstract

PURPOSE:To improve the reliability of the electrical connection of an electronic part chip and a printed wiring board by a method wherein a recessed section is formed to one-side surface of a laminated board, a plating acceptor containing materials is applied in said recessed section, a plating acceptor is exposed to the inner surface of said recessed section, and an exposed surface is plated to shape a plating layer. CONSTITUTION:A recessed section is formed to one-side surface of a laminated board, in which a required number of resin impregnated base materials impregnated with a woven fabric, a nonwoven fabric, a mat or paper consisting of an inorganic fiber, such as glass, asbestos, etc. an organic synthetic fiber such as acryl or a naturals fiber such as cotton or these combination base material are superposed and metallic foils are stacked, laminated and molded on the upper surface and/or lower surface of the resin impregnated base materials, or a metal-base laminated board in which one part of the resin impregnated base materials is replaced with a metallic plate. Resin paste, resin varnish, etc. containing a plating acceptor, such as palladium, gold, silver, copper, etc. are applied into said recessed section, the plating acceptor is exposed to the inner surface of the recessed section through mechanical treatment, chemical treatment by chromic acid, etc., ultraviolet treatment previously making anthraquinone, etc., be contained as a photosensitizer, etc., and an exposed surface is electroless-plated or the upper section of the exposed surface is electroplated, thus forming a plating layer.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、ICパッケージなどのような電子素子の実装
基板として用いられる電子素子用チップキャリアに関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a chip carrier for electronic devices used as a mounting substrate for electronic devices such as IC packages.

〔背景技術〕[Background technology]

ICパッケージなどのような電子素子は、半尋体チリプ
などの電子部品チップをリードフレームに縁り付けた状
態で樹脂封止や気密制止してパッケージングすることに
よって行われる。そしてこのような電子素子にあって、
端子tの増加に伴うて電子部品チップを支持するキャリ
アとしてのリードフレームの替わりにプリント配線板を
用いる試みがなされているが、電子部品チップとプリン
ト配線板との電気的接続信頼性が低く、ワイヤポンディ
ング、ダイポンディング時に問題が多発していた。
BACKGROUND ART Electronic devices such as IC packages are manufactured by packaging an electronic component chip such as a semicircular chip attached to a lead frame and sealed with resin or airtight. And in such electronic devices,
With the increase in the number of terminals t, attempts have been made to use a printed wiring board instead of a lead frame as a carrier for supporting electronic component chips, but the reliability of the electrical connection between the electronic component chip and the printed wiring board is low. Problems frequently occurred during wire bonding and die bonding.

[発明の目的] 本発明の目的とするところは、電子部品チップとプリン
ト配線板との電気的接続信頼性に優れた電子素子用チッ
プキャリアを提供することKある。
[Object of the Invention] An object of the present invention is to provide a chip carrier for an electronic device that has excellent electrical connection reliability between an electronic component chip and a printed wiring board.

〔発明の開示〕[Disclosure of the invention]

本発明は81層板の片側表面に凹部を設け、該凹部内に
鍍金受容物質含有材料を塗布後、該凹部内面に鍍金受容
物質を露出させ、露出面に獣舎を施して鍍金層を形成し
たことを特徴とする電子素子用チップキャリアのため電
子部品チップの電気的接続信頼性を著るしく向上せしめ
ることができたもので、以下本発明の詳細な説明する。
In the present invention, a recess is provided on one surface of an 81-layer board, and after coating a material containing a plating receptive substance in the recess, the plating receptive substance is exposed on the inner surface of the recess, and a coating is applied to the exposed surface to form a plating layer. The present invention will be described in detail below.The present invention will be described in detail below.

本発明にm−る積層板としては、積層板用樹脂としてフ
ェノール樹脂、クレゾール樹脂、エボキキシ樹脂、不飽
和ポリエステル樹脂、メラミン樹月旨、ポリイミド、ボ
リフ゛タジエン、ポリアミド、ポリアミドイミド、ポリ
スルフォン、ポリブ千しンテレフタレート、ポリエーテ
ルエーテルケトン、弗化摘信等の瓜独、変性物、ン昆合
吻等が用められ、ガラス了スベス)Wの無機チλ維やポ
リエステル、ポリアミド、ポリビニルアルコール、アク
リル等の有機合戎住維−や木綿等の天然繊維から々る織
布、不織布、マ・フト或は紙又はこれらの組合せ基材を
含浸してなる樹脂含浸基材を所要枚数重ね、更にその上
面及び又は下面に金属箔を重ね積層成形してなる積ti
→板や樹脂含浸基材の一部を金属板と置換してなる金円
ベース@層板の片側表面にザグリ加工、穴あけ加工等の
任意手段で凹部を設け、次いで該凹部内((パラジウム
、金、銀、銅等の鍍金受容物實を官有する樹脂ペースト
、樹脂フェス等を塗布後、磯檎的処理やクロム酸等によ
る薬品処理や予じめ酸化チタン、アンスラキノン類等ヲ
感光勿漬として官有させておく紫外線処理等で凹部内面
に鍍金受容物笛を露出させ、露出面を無電解鍍金又は更
1Cその上に嵐気鍍金を施して玉金層を形成させ電子素
子用チップキャリアを得るものである。
In the laminate according to the present invention, resins for the laminate include phenolic resin, cresol resin, epoxy resin, unsaturated polyester resin, melamine resin, polyimide, polybutadiene, polyamide, polyamideimide, polysulfone, polybutylene resin, etc. Polyesters, modified products, and combinations of sinter terephthalate, polyether ether ketone, fluoride, etc. are used, as well as inorganic fibers such as glass, smooth, polyester, polyamide, polyvinyl alcohol, and acrylic. Layer the required number of resin-impregnated base materials impregnated with woven fabrics, non-woven fabrics, mats, paper, or combinations of these materials made from natural fibers such as organic synthetic fibers, cotton, etc., and then Laminated Ti made by layering metal foil on the top and/or bottom surface
→ Create a recess on one side surface of the gold circle base @layer board by replacing a part of the plate or resin-impregnated base material with a metal plate, by any means such as counterboring or drilling, and then inside the recess ((palladium, After applying a resin paste, resin face, etc. that contains plating receptors such as gold, silver, copper, etc., it is treated with sulfuric acid, chemical treatment with chromic acid, etc., and pre-sensitized with titanium oxide, anthraquinone, etc. A plating receptor pipe is exposed on the inner surface of the concave part by ultraviolet treatment, etc., and the exposed surface is electroless plated or further 1C plating is applied on top of it to form a gold layer to form a chip carrier for electronic devices. This is what you get.

以下本発明を実施・ダ1にもとづいて説明する。The present invention will be explained below based on the first implementation.

実施例 エポキシ樹脂ワニスに厚さ0.2 mmのガラス布を樹
脂量が45!M % (JJ下蛍に係と記す)になるよ
うに含浸、乾燥して得た耐脂含浸基vr8枚を1ねた上
、下面に厚さ35ミクロンの銅箔を夫々配役した積層体
を成形圧力so r:yi 、17n℃で90分間積1
成形して厚さ1.6 flのガラス布基材エポキシ樹脂
積層板を得、次に該積層板の所要位置にザグリ加工で深
さQ、 7 Mの凹部を設け、凹部内1c 0.1 %
の塩化パラジウム含有ニトリルゴム変性エポキシ(支)
脂ペーストを塗布後、クロム酸処理で凹部内面に塩化パ
ラジウムを露出させた後、露出面を無、11解鍍金して
銅鍍金を形成し1子素子用チツプキヤリアを得た。
Example: Glass cloth with a thickness of 0.2 mm was coated with epoxy resin varnish and the amount of resin was 45! A laminate was prepared by placing 8 sheets of the grease-resistant impregnated base vr obtained by impregnating and drying it so that M % (denoted as JJ Shimotaru) and then placing copper foil with a thickness of 35 microns on the bottom surface of each layer. Molding pressure sor: yi, 90 minutes at 17nC 1
A glass cloth base epoxy resin laminate with a thickness of 1.6 fl was obtained by molding, and then a recess with a depth Q of 7 M was provided at the required position of the laminate by counterboring, and the inside of the recess was 1 cm 0.1 cm. %
Palladium chloride-containing nitrile rubber modified epoxy (base)
After applying the fat paste, palladium chloride was exposed on the inner surface of the recess by chromic acid treatment, and then the exposed surface was plated to form copper plating to obtain a chip carrier for a single element.

比較例 実施例と同じプリプレグA8枚を重ねた上、下面に厚さ
35ミクロンの銅箔を夫々配役した積層体を成形圧力5
0’v’d 、170℃で90分間積層成形して厚さ1
.6flのガラス布基材エポキシ樹脂積層板を得1次に
該積層板の所要位置てザグリ加工で深さ0.7Mの凹部
を設け、凹部内面を通常のスルホール鍍金工程に従い、
鍍金核の塗布、活性化により銅鍍金層を形成し電子素子
用チップキャリアを得た。
Comparative Example A laminate consisting of 8 sheets of prepreg A stacked together, each with a 35 micron thick copper foil on the bottom surface, was molded under a molding pressure of 5.
0'v'd, laminated at 170℃ for 90 minutes to a thickness of 1
.. A 6fl glass cloth base epoxy resin laminate was obtained. First, a recess with a depth of 0.7M was provided by counterboring the laminate at the desired position, and the inner surface of the recess was subjected to a normal through-hole plating process.
A copper plating layer was formed by applying and activating a plating core to obtain a chip carrier for an electronic device.

〔発明の効果〕〔Effect of the invention〕

実施例及び比較例の電子素子用チップキャリアに半魂体
チップをワイヤポンディング、ダイポンディングした結
果は第1表で明白なように本発明のものの性能はよく、
本発明の電子素子用チップキャリアの優れていることを
確認した。
The results of wire-bonding and die-bonding of semi-intrusive chips to the chip carriers for electronic devices of Examples and Comparative Examples are as shown in Table 1. As is clear from Table 1, the performance of the present invention was good;
It was confirmed that the chip carrier for electronic devices of the present invention is excellent.

Claims (1)

【特許請求の範囲】[Claims] (1)積層板の片側表面に凹部を設け、該凹部内に鍍金
受容物質含有材料を塗布後、該凹部内面に鍍金受容物質
を露出させ、露出面に鍍金を施して鍍金層を形成したこ
とを特徴とする電子素子用チップキャリア。
(1) A recess is provided on one surface of the laminate, a material containing a plating receptive substance is applied inside the recess, the plating receptive substance is exposed on the inner surface of the recess, and the exposed surface is plated to form a plating layer. A chip carrier for electronic devices featuring:
JP528986A 1986-01-13 1986-01-13 Chip carrier for electronic element Pending JPS62163349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP528986A JPS62163349A (en) 1986-01-13 1986-01-13 Chip carrier for electronic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP528986A JPS62163349A (en) 1986-01-13 1986-01-13 Chip carrier for electronic element

Publications (1)

Publication Number Publication Date
JPS62163349A true JPS62163349A (en) 1987-07-20

Family

ID=11607080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP528986A Pending JPS62163349A (en) 1986-01-13 1986-01-13 Chip carrier for electronic element

Country Status (1)

Country Link
JP (1) JPS62163349A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318646A (en) * 1986-07-11 1988-01-26 Asaka Denshi Kk Element part for printed board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318646A (en) * 1986-07-11 1988-01-26 Asaka Denshi Kk Element part for printed board

Similar Documents

Publication Publication Date Title
JPS62163349A (en) Chip carrier for electronic element
JP5645047B2 (en) Package board for mounting semiconductor device, its manufacturing method and semiconductor package
JP2010103520A (en) Semiconductor element mounting package substrate and method for manufacturing the same
JPS62163348A (en) Chip carrier for electronic element
JPS58210691A (en) Method of producing metal foil-lined laminated board
KR101168825B1 (en) Package substrate for mounting semiconductor element and method for manufacturing the package substrate
JPS63264342A (en) Copper plated laminate and its manufacture
JP3725489B2 (en) Wiring board manufacturing method
JPS6390872A (en) Printed circuit board
JPH0428152B2 (en)
JP3644045B2 (en) Manufacturing method of multilayer electronic component mounting substrate
JPS6390873A (en) Manufacture of metallic base circuit board
JPS6390897A (en) Manufacture of multilayer interconnection board
JPH03249A (en) Preparation of electric laminated sheet
JPH0336315B2 (en)
JPS6390871A (en) Printed circuit board
JPS63265494A (en) Multilayer interconnection board
JPS6370488A (en) Manufacture of metal base board
JPS62132392A (en) Metal base wiring substrate
CN112349599A (en) Manufacturing method of chip substrate
JPS6281793A (en) Manufacturing laminated board for printed circuit board
JPH01235293A (en) Manufacture of electric laminated board
JPH03246A (en) Preparation of electric laminated sheet
JPH0239486A (en) Manufacture of metal core printer substrate for bending
JPH05206648A (en) Multilayer printed wiring board