JPS62162867U - - Google Patents
Info
- Publication number
- JPS62162867U JPS62162867U JP5085586U JP5085586U JPS62162867U JP S62162867 U JPS62162867 U JP S62162867U JP 5085586 U JP5085586 U JP 5085586U JP 5085586 U JP5085586 U JP 5085586U JP S62162867 U JPS62162867 U JP S62162867U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- holes
- row
- conductive
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Combinations Of Printed Boards (AREA)
Description
第１図〜第３図は本考案の１実施例に係り、第
１図は要部断面図、第２図Ａ〜Ｃは製造過程を示
す要部斜視図、第３図は接合された基板の簡略化
した斜視図、第４図および第５図は各々本考案の
異なる実施例を示す要部断側面図、第６図は従来
例を示す要部側面図である。
１……第１の基板、２……スルーホール、３…
…導電パターン、３ａ……導電部、４……半田、
５……第２の基板、６……導電パターン。
Figures 1 to 3 relate to one embodiment of the present invention, with Figure 1 being a sectional view of the main parts, Figures 2A to C being perspective views of the main parts showing the manufacturing process, and Figure 3 being the joined substrates. FIGS. 4 and 5 are sectional side views of main parts showing different embodiments of the present invention, and FIG. 6 is a side view of main parts showing a conventional example. 1...First board, 2...Through hole, 3...
...Conductive pattern, 3a...Conductive part, 4...Solder,
5... Second substrate, 6... Conductive pattern.
Claims (1)
成すると共に、このスルーホール列に沿つて切断
を行なつて第１の基板の端面においてスルーホー
ル内壁の導電部を露呈させ、この第１の基板の各
スルーホール内壁の導電部と第２の基板の平面上
に形成した導電パターン群とを半田付けし、第１
と第２の基板をその基板平面同志が所定角度をも
つて電気的・機械的に接続したことを特徴とする
印刷基板の接合構造。 A plurality of through holes are formed in one row in the first substrate, and the conductive portions of the inner walls of the through holes are exposed at the end surface of the first substrate by cutting along the row of through holes. The conductive part on the inner wall of each through hole of the second substrate is soldered to the conductive pattern group formed on the plane of the second substrate, and
and a second board are electrically and mechanically connected with their flat surfaces at a predetermined angle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5085586U JPS62162867U (en) | 1986-04-07 | 1986-04-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5085586U JPS62162867U (en) | 1986-04-07 | 1986-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62162867U true JPS62162867U (en) | 1987-10-16 |
Family
ID=30874593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5085586U Pending JPS62162867U (en) | 1986-04-07 | 1986-04-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62162867U (en) |
-
1986
- 1986-04-07 JP JP5085586U patent/JPS62162867U/ja active Pending