JPS62159451A - Circuit assembly - Google Patents

Circuit assembly

Info

Publication number
JPS62159451A
JPS62159451A JP52186A JP52186A JPS62159451A JP S62159451 A JPS62159451 A JP S62159451A JP 52186 A JP52186 A JP 52186A JP 52186 A JP52186 A JP 52186A JP S62159451 A JPS62159451 A JP S62159451A
Authority
JP
Japan
Prior art keywords
circuit
elements
wiring board
package
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP52186A
Other languages
Japanese (ja)
Inventor
Bunichi Tagami
田上　文一
Yutaka Watanabe
裕 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52186A priority Critical patent/JPS62159451A/en
Publication of JPS62159451A publication Critical patent/JPS62159451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Abstract

PURPOSE:To perform a circuit assembly having various functions by mixing circuit packages for storing elements which direct the main surfaces of elements toward a circuit substrate side and which direct it toward opposite side to increase a range of selecting the elements. CONSTITUTION:A circuit package 3 is of the type for directing the main surface of the element toward the opposite side to a circuit substrate 1. A circuit package 4 is of the type for directing the main surface of the element toward the substrate 1 side. The connecting portion shapes and the profile shapes of the packages 3, 4 are unified. Thus, a range of selecting the elements is increased to perform circuit assembly having various functions.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は集積回路素子を格納した回路パッケージを搭載
する回路アセンブリに関し、特に異種類の集積回路素子
を格納する回路パッケージを複数個任意に配置して搭載
するのに好適な回路アセンブリに関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a circuit assembly equipped with a circuit package storing integrated circuit elements, and particularly relates to a circuit assembly in which a plurality of circuit packages storing different types of integrated circuit elements are arbitrarily arranged. The present invention relates to a circuit assembly suitable for mounting on a vehicle.

〔発明の背景〕[Background of the invention]

従来の回路アセンブリは、例えば特開昭５８−１１６７
５５号公報に記載されるように複数個の集積回路素子の
一部をそれぞれ独立した回路パッケージに格納した状態
で配線基板に搭載し、他の一部をチップ状態で同じ配線
基板に搭載するものである。しかして、異種類の回路素
子から成る回路パッケージを混在して搭載する場合に問
題となる配置の任意性あるいは組立工程の共通化等につ
いては全く配慮されていなかった。Conventional circuit assemblies are disclosed in, for example, Japanese Patent Application Laid-Open No. 58-1167.
As described in Publication No. 55, a part of a plurality of integrated circuit elements is mounted on a wiring board while each of them is housed in an independent circuit package, and another part is mounted in the form of a chip on the same wiring board. It is. However, no consideration was given to the arbitrariness of the arrangement or the standardization of the assembly process, which would be a problem when circuit packages consisting of different types of circuit elements are mixed and mounted.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、異種類の集積回路素子を格納した回路
パッケージを任意の配置で混在搭載することを可能にし
、また組立工程の共通化を可能にした回路アセンブリを
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit assembly that allows circuit packages containing different types of integrated circuit elements to be mounted in a mixed manner in any desired arrangement, and also allows for common assembly processes.

〔発明の概要〕[Summary of the invention]

本発明は、入出力ピンを有する配線基板に集積回路素子
を格納した複数の回路パッケージを搭載する回路アセン
ブリにおいて、集積回路素子を格納する回路パッケージ
として素子主表面を配線基板との接続側に向けるものと
非接続側に向けるものを素子の種類により使い分け、か
つこれらの回路パッケージの接続部形状及び外形状を統
一化するものであり、機能の多様化に加え組立工程の共
通化や部品配置の自由化を図るものである。The present invention provides a circuit assembly in which a plurality of circuit packages storing integrated circuit elements are mounted on a wiring board having input/output pins. This method uses different types of elements, one facing the other and the other facing the non-connecting side, depending on the type of element, and standardizing the shape and external shape of the connecting part of these circuit packages.In addition to diversifying functions, it also makes it possible to standardize assembly processes and improve component placement. This is aimed at liberalization.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例について図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図（Ａ）、（Ｂ）は本発明の一実施例を示すもので
、（Ａ）は平面図、（Ｂ）は（Ａ）のＢ−Ｂ’断面図で
ある。同図において、１はセラミック多層配線基板、２
はその端子ピン、３と４は回路パッケージ、５は回路パ
ッケージ３．４に格納された集積回路素子である。こ−
で、集積回路素子５の回路パッケージとの非接触面を主
表面ということにする。回路パッケージ３は素子主表面
を配線基板１とは反対側に向けたタイプのものであり、
回路パッケージ４は素子主表面を配線基板１側に向けた
タイプのものである。回路パッケージ３のタイプは熱放
散性がよいため、例えば高速大電力のＥＣＬ素子を格納
した回路パッケージに好適である。また、回路パンケー
ジ４は、高密度性を主眼とした高集積低電力の０ＭＯ８
素子を格納した回路パッケージに好適である。FIGS. 1A and 1B show an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line BB' in FIG. 1A. In the figure, 1 is a ceramic multilayer wiring board; 2 is a ceramic multilayer wiring board;
are its terminal pins, 3 and 4 are circuit packages, and 5 is an integrated circuit element housed in the circuit package 3.4. This
Here, the surface of the integrated circuit element 5 that is not in contact with the circuit package will be referred to as the main surface. The circuit package 3 is of a type in which the main surface of the element faces opposite to the wiring board 1,
The circuit package 4 is of a type in which the main surface of the element is directed toward the wiring board 1 side. Since the type of circuit package 3 has good heat dissipation properties, it is suitable for, for example, a circuit package containing a high-speed, high-power ECL element. In addition, the circuit pancage 4 is a highly integrated low power 0MO8 with a focus on high density.
Suitable for circuit packages containing elements.

大電力のＥＣＬ素子を格納した回路パッケージは一般に
大形となるが１回路パッケージ３のタイプとすることに
より集散散性がよくなるため、小形化が可能になる。ま
た、高集積低電力の０ＭＯ８素子を格納した回路パッケ
ージ４は大形チップが適用できる利点がある。これらの
ことより、回路パッケージ３，４はその外形形状を統一
化することが容易である。A circuit package that stores a high-power ECL element is generally large in size, but by using the one-circuit package 3 type, the convergence and dissipation properties are improved, so that the package can be made smaller. Further, the circuit package 4 storing highly integrated and low power 0MO8 elements has the advantage that a large chip can be applied. For these reasons, it is easy to unify the external shapes of the circuit packages 3 and 4.

本実施例では、回路パッケージ３と４の間で、外形形状
のみならずその接続部の形状も統一して標準化を図って
いる。In this embodiment, not only the external shape but also the shape of the connecting portion between the circuit packages 3 and 4 are unified and standardized.

一般に、回路アセンブリの用途により使用する回路素子
が異なり、高速性を主眼とする部分には高速電力のＥＣ
Ｌ素子を、高密度性を主眼とする部分には高集積低電力
の０ＭＯ８素子を使用し、かつ、これらを１つの回路ア
センブリに混在して搭載できる様にすることで種々の機
能の回路アセンブリが実現可能になる。こ＼で留意する
ことは、機能の多様化に加えて組立工程の共通化や部品
配置の自由度を高めることが重要である。このためには
、種々の集積回路素子を格納する回路パッケージを統一
化することが有効である。すなわち、　　ｌ配線基板と
の接続部形状及び外形形状を統一することで、組立設備
の標準化、配線基板の標準化及びこれに伴なう配線基板
上の部品配置の自由度の拡大が図れる。In general, the circuit elements used differ depending on the purpose of the circuit assembly, and high-speed power EC is used for parts where high speed is the main focus.
By using highly integrated low-power 0MO8 L elements in parts where high density is the main focus, and by allowing these elements to be mixed and installed in one circuit assembly, it is possible to create circuit assemblies with various functions. becomes possible. What to keep in mind here is that in addition to diversifying functions, it is important to standardize assembly processes and increase the degree of freedom in parts placement. For this purpose, it is effective to unify circuit packages that house various integrated circuit elements. That is, by unifying the shape and external shape of the connecting portion with the wiring board, it is possible to standardize assembly equipment, standardize the wiring board, and thereby expand the degree of freedom in arranging components on the wiring board.

なお、本実施例はアテシャルピンタイプのセラミック配
線基板を用いた一例であり、他のリードフレームタイプ
の基板が可能であることは言うまでもない。また、ＬＣ
Ｃの配置も一例である。It should be noted that this embodiment is an example in which an attial pin type ceramic wiring board is used, and it goes without saying that other lead frame type boards are possible. Also, L.C.
The arrangement of C is also an example.

〔発明の効果〕〔Effect of the invention〕

以上述べた如く、本発明によれば、入出力ピンを有する
配線基板に複数個の集積回路素子を搭載する回路アセン
ブリにおいて、素子を格納する回路パッケージとして素
子主表面を配線基板側に向けるものと反対側に向けるも
のを混在して使用できるため、素子選択の範囲が広く種
々の機能の回路アセンブリが可能になる共に、これらの
回路パッケージの形状を統一することで、組立設備の標
準化や配線基板の標準化が可能となり生産性の高い回路
モジュールとすることができる。As described above, according to the present invention, in a circuit assembly in which a plurality of integrated circuit elements are mounted on a wiring board having input/output pins, the main surface of the element is directed toward the wiring board side as a circuit package for storing the elements. Since it is possible to use a mixture of those facing the opposite side, it is possible to have a wide range of element selection and to assemble circuits with various functions.By unifying the shape of these circuit packages, it is possible to standardize assembly equipment and improve wiring board design. This makes it possible to standardize circuit modules with high productivity.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）は本発明の一実施例を示す回路アセンブリ
の平面図、第１図（Ｂ）は第１図（Ａ）のＢ−Ｂ’線断
面図である。 １・・・セラミック多層配線基板、　２・・・端子ピン
、３．４・・・回路パッケージ、　５・・・集積回路素
子。 ｉ、７きFIG. 1(A) is a plan view of a circuit assembly showing one embodiment of the present invention, and FIG. 1(B) is a sectional view taken along the line BB' of FIG. 1(A). DESCRIPTION OF SYMBOLS 1...Ceramic multilayer wiring board, 2...Terminal pin, 3.4...Circuit package, 5...Integrated circuit element. i, 7ki

Claims (3)

【特許請求の範囲】[Claims] （１）集積回路素子を格納する複数の回路パッケージを
入出力ピンを有する配線基板に搭載する回路アセンブリ
において、一の回路パッケージは前記集積回路素子の主
表面が配線基板との接続側に向き、他の回路パッケージ
は前記集積回路素子の主表面が前記配線基板との非接続
側に向いてることを特徴とする回路アセンブリ。(1) In a circuit assembly in which a plurality of circuit packages storing integrated circuit elements are mounted on a wiring board having input/output pins, one circuit package has the main surface of the integrated circuit element facing the connection side with the wiring board, Another circuit assembly is characterized in that the main surface of the integrated circuit element faces a side not connected to the wiring board. （２）前記一の回路パッケージと他の回路パッケージは
、前記配線基板との接続部形状が統一されていることを
特徴とする特許請求の範囲第１項記載の回路アセンブリ
。(2) The circuit assembly according to claim 1, wherein the one circuit package and the other circuit package have the same shape of a connecting portion with the wiring board. （３）前記一の回路パッケージと他の回路パッケージは
、外形々状が統一されていることを特徴とする特許請求
の範囲第１項記載の回路アセンブリ。(3) The circuit assembly according to claim 1, wherein the one circuit package and the other circuit package have the same external shape.
JP52186A 1986-01-08 1986-01-08 Circuit assembly Pending JPS62159451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52186A JPS62159451A (en) 1986-01-08 1986-01-08 Circuit assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52186A JPS62159451A (en) 1986-01-08 1986-01-08 Circuit assembly

Publications (1)

Publication Number Publication Date
JPS62159451A true JPS62159451A (en) 1987-07-15

Family

ID=11476070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52186A Pending JPS62159451A (en) 1986-01-08 1986-01-08 Circuit assembly

Country Status (1)

Country Link
JP (1) JPS62159451A (en)

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