JPS62158390U - - Google Patents

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Publication number
JPS62158390U
JPS62158390U JP1986046790U JP4679086U JPS62158390U JP S62158390 U JPS62158390 U JP S62158390U JP 1986046790 U JP1986046790 U JP 1986046790U JP 4679086 U JP4679086 U JP 4679086U JP S62158390 U JPS62158390 U JP S62158390U
Authority
JP
Japan
Prior art keywords
counter
signal
circuit
outputs
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986046790U
Other languages
Japanese (ja)
Other versions
JPH04311Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986046790U priority Critical patent/JPH04311Y2/ja
Publication of JPS62158390U publication Critical patent/JPS62158390U/ja
Application granted granted Critical
Publication of JPH04311Y2 publication Critical patent/JPH04311Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図はデコーダ設定値内のときに秒修正スイツチを
操作した場合のタイムチヤート図、第3図はデコ
ーダ設定値外のときに秒修正スイツチを操作し、
分カウンタをダウンカウント状態にて分表示の修
正を行なう場合のタイムチヤート図、第4図はデ
コーダ設定値外のときに秒修正スイツチを操作し
、分カウンタをアツプカウント状態にて分表示の
修正を行なう場合のタイムチヤート図。 12……発振器、14……分周回路、16……
秒カウンタ、20……分カウンタ、24……時カ
ウンタ、28……メイン回路、30……修正可能
スイツチ、32……秒修正スイツチ、34……分
修正スイツチ、40……第1アンド回路、42…
…第2……第2アンド回路、44……第3アンド
回路、46……インバータ、52……進み誤差判
別回路、58……第1フリツプフロツプ、60…
…第1パルスカウンタ、62……ダウン指定回路
、66……第2フリツプフロツプ、70……カウ
ント方向切換回路、72……第2パルスカウンタ
、76……復帰回路。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure shows a time chart when the second correction switch is operated when the decoder setting value is within the value, and Figure 3 shows the time chart when the second correction switch is operated when the decoder setting value is outside the decoder setting value.
Figure 4 is a time chart when the minute counter is in the down count state and the minute display is corrected.Figure 4 is a time chart when the minute counter is in the up count state and the minute display is corrected by operating the second correction switch when the decoder setting value is outside. A time chart for when doing this. 12... Oscillator, 14... Frequency dividing circuit, 16...
Second counter, 20... Minute counter, 24... Hour counter, 28... Main circuit, 30... Modifiable switch, 32... Second correction switch, 34... Minute correction switch, 40... First AND circuit, 42...
...Second...Second AND circuit, 44...Third AND circuit, 46...Inverter, 52...Leading error discrimination circuit, 58...First flip-flop, 60...
...First pulse counter, 62...Down designation circuit, 66...Second flip-flop, 70...Count direction switching circuit, 72...Second pulse counter, 76...Return circuit.

Claims (1)

【実用新案登録請求の範囲】 一定周期の出力信号を出力する発振器と該発振
器の出力を別の一定周期の基準信号に変える分周
回路と、 該基準信号をカウントして時刻信号を形成する
秒カウンタ、分カウンタ及び時カウンタと、 前記秒カウンタのカウント値をクリアする秒修
正スイツチと、 を少なくとも具えている電子時計において、 前記分カウンタをアツプダウンカウンタを用い
て構成すると共に、 前記分カウンタのカウント値が予め設定された
範囲内のときに前記秒修正スイツチが操作される
と進み誤差判別信号を出力する進み判別回路と、 前記分カウンタのカウント値が予め設定された
範囲外のときに前記秒修正スイツチが操作され、
且つ、該秒修正スイツチの操作後一定時間内に、
前記分修正スイツチが操作されない場合にはダウ
ン指定信号を出力するダウン指定回路と、 前記アツプダウンカウンタを通常はアツプカウ
ント状態に維持し、前記進み誤差判別信号若しく
はダウン指定信号の何れかが出力された場合には
ダウンカウント状態にするカウント切換信号を出
力するカウント方向切換回路と、 前記アツプダウンカウンタがダウンカウント状
態に切り換えられた後、前記分修正スイツチが一
定時間操作されない場合にはアツプダウンカウン
タをアツプカウント状態に戻すカウント方向復帰
信号を出力するカウント方向復帰回路と、 を設けたことを特徴とする後退修正機能付電子時
計。
[Claims for Utility Model Registration] An oscillator that outputs an output signal with a constant period, a frequency divider circuit that converts the output of the oscillator into another reference signal with a constant period, and a second circuit that counts the reference signal to form a time signal. An electronic watch comprising at least a counter, a minute counter, an hour counter, and a second correction switch for clearing the count value of the second counter, wherein the minute counter is configured using an up-down counter, and the minute counter is configured using an up-down counter. an advance determination circuit that outputs an advance error determination signal when the second correction switch is operated when the count value is within a preset range; The seconds correction switch is operated,
And, within a certain period of time after operating the seconds correction switch,
a down designation circuit that outputs a down designation signal when the minute correction switch is not operated; and a down designation circuit that normally maintains the up/down counter in an up counting state and outputs either the advance error determination signal or the down designation signal. a count direction switching circuit that outputs a count switching signal to turn the up-down counter into a down-counting state when the up-down counter is switched to the down-counting state; What is claimed is: 1. An electronic timepiece with backward correction function, comprising: a count direction return circuit that outputs a count direction return signal for returning the clock to an up-count state;
JP1986046790U 1986-03-28 1986-03-28 Expired JPH04311Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986046790U JPH04311Y2 (en) 1986-03-28 1986-03-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986046790U JPH04311Y2 (en) 1986-03-28 1986-03-28

Publications (2)

Publication Number Publication Date
JPS62158390U true JPS62158390U (en) 1987-10-07
JPH04311Y2 JPH04311Y2 (en) 1992-01-07

Family

ID=30866781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986046790U Expired JPH04311Y2 (en) 1986-03-28 1986-03-28

Country Status (1)

Country Link
JP (1) JPH04311Y2 (en)

Also Published As

Publication number Publication date
JPH04311Y2 (en) 1992-01-07

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