JPS62153996A - Panel unit for electronic musical apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application-j] This invention particularly relates to a panel device for an electric musical instrument using an illuminated switch.

``Prior Art'' On the operation panel of an electronic musical instrument, illuminated switches may be used as various switches such as a tone setting switch or an effect setting switch. In a panel device using this illuminated switch, a circuit for detecting the on/off state of each switch is required, and at the same time, a circuit for detecting the on/off state of each switch is required.
I) A circuit for driving the illumination means consisting of (light emitting diode) or the like is required.

[Problems that the invention cannot solve] By the way, in a conventional panel device using an illuminated switch, the circuit for detecting the on/off state of the switch and the circuit for driving the illumination means are separate. (For example, see Japanese Unexamined Patent Publication No. 59-104696), which makes the structure of the panel device complicated and increases the price.

Therefore, this invention has a simplified circuit configuration! Our first objective is to provide a panel device for electric musical instruments that is designed to be used as an electronic instrument.

In addition, in this specification, [-Illuminated switch-1 and J
In this case, it is not only necessary to have a switch with a built-in illumination device, but also to have a display element such as an LED near the switch.

``Means for Solving the Problem 1'' The invention provides a plurality of switches, a display means provided corresponding to each of these switches 1, and display means for displaying the operating status of the switches; A matrix circuit having a plurality of column lines and a plurality of row lines, wherein the display means corresponding to the switches described in i'iij are inserted at the intersections of the column lines and the row lines. , the first (, ·) !, which drives the column line (or batting line) of the 7-trix circuit, and a dynamic T stage at l, and nij 7
Paste the data obtained on the i+ line ('8 (full line)) of the Torino base circuit to the memory L stage and the line of the matrix circuit ('' no (b line) 4) 1iii
, i convex ic! Depending on the data stored in the iQ means (-
1. Drive 4/, 20th) drive means; − (, O7i +1 [Action 1 This invention detects the state 4 of each switch.
The 7-trisock circuit for 4-digit storage is shared by the drive for the front and small stages, and the configuration is in-cylinder.

] Embodiment 1 As described above, referring to the drawings (Explanation 4-7 in Embodiment 4 of the present invention), a panel device PS is applied to the market. rShows the structure of the musical instrument!
This is a diagram. In this figure, I tJ, CI)U
(Central processing unit), 2 is CI) [Ij('IM, 3 is 1?ΔM for data storage) in which the program (b-gram used in 11 is stored. As shown in Figure 2, the area of 1 hide E1~3
゜8 Hyde switch data area SW E, 8
Part-time job Ba Sofu γJ, rear B-C, warging area WO1? K is provided respectively. 4.5 is a data bus and an address bus, 6 is a timer, and this timer 6 generates an interrupt signal 'r' every time a certain period of time elapses.
IM l (see FIG. 3 (c)) is output to CPU I. 7 is a 1/4 frequency divider circuit, and interrupt signal i'
l M I l/41. : Frequency division and interrupt signal TrM
2 (see Figure 3 (a)) and output to CI) UI.

Note that the interrupt signals 1" I M I and 'I" IM
2 occur at the same time, the interrupt signal TIM2 is prioritized and the interrupt signal TIM2 is not processed. 8 is a tone generator (musical tone forming circuit), which turns on/off the keyboard guitar supplied from CP LJ l.
A musical tone signal is formed based on the on/off information of the panel switch and the on/off information of the panel switch corresponding to the off operation, and is output to the sound nostem 9. A sound no steno 9 generates a musical tone signal outputted from the tone generator 8 as a musical tone.

Next, an embodiment of the present invention will be described.
I'll take a look and explain. 4゛, 11 (f In a matrix circuit, one kite has eight column lines RI to It8 and eight row lines L.
a l ~ l, a8 and these row lines Cal ~ La8
Eight row lines L b I to 1. are arranged in parallel to each other.
1) 8, column lines R1-R8 and row lines 1al-1, a8
Panel switches 13a, 13a, inserted at the intersections of
- LEI for illumination inserted at the intersection of column lines RI to R8 and row lines 1 b l to Lb8) I 3b, l 3
1+, . . . and a resistor 15 inserted in the lead between these T and E D I 3 b. In this case, the panel switch 13alJ is a switch-on/release-off type switch. Also, 1, I> I)
I 311 is for displaying the operating states of the panel switches 13a arranged in parallel in the figure. The decoder & latch 16 is composed of a latch that reads data on the data bus 4 when a signal S1 is supplied to its C7-1 terminal I7, and a decoder that decodes the output of this latch. Each output end of the decoder corresponds to the column line r? +-118 should be connected to one end of each. , the address decoder I7 connects the address decoder I7 to the address decoder I7 via the address bus 5.
/suata l) When I is supplied, it is an Oro decoder that outputs 1 and SL. L r>I)+・− noise circuit I5) is transistor 2 (] −1 to 20
-8 and a latch 22, the transistor 20
Each of -1 to 20-8 = Lucta is each row line L b l to L
b Connected to each end of 8. address day 1
- The address data 1 is sent to the address data 1 via the address bus 5.
)2 is supplied, latches the signal S2220)o
l" 3iW rL Output 4-B. This signal S2 causes the data on the data bus 4 to be read into the latch 22. The input port 25 is composed of 8-hit latches, and its input end is connected to the row line La1. ~ La8, and the output data thereof is supplied to the data bus 4. When the address decoder 26 is supplied with the address data II) 3 via the address bus 5, the address decoder 26 outputs the signal "rS3".
is output to the 1-node terminal 17 of the human-powered boat 25. The data obtained on the row lines La1 to La8 are read into the input capos 1 and 25 by this signal S3.

Next d, l+M ++k d J,':l city r%',:
' 2: i (7') Refer to the movement 1'1 in Figure 3, small 4' Hasugi diagram, and figures 4 to 7, small 4' (: I'Ill's movement) vl-chart jjjj L , Please explain 4'.

Upper 4-, interrupt z+ from timer 6, (,j fcy'
If the output is A], then we will explain step 4. In this case, i"i, C1), step Sa in Fig. 4.
Go to t, address bus 5 hair]・shi・sl) 2,
Data to data bus 4 l-0,1 (0, (], -0)
I will output it from time to time. Address bus 5 hair tresf 5-ta 2 or output S), A1, response decoder 2: (from Il, < TI, (q2 outputs), according to this signal S2), Data output to data bus 4 [0
1 is loaded into latch 22. Then, the transistors 20-1 to 20-8 are cut off. 4-
I') #), Valley 1, 1.: l') I 3 The drive of h is stopped. Next, CI' ml I tJ,
The switch scan process of step Sa2 is performed. Figure 5 shows the process of this switch scanning process >1< to
Proceeding to this switch scan process, as the data I in the top 4, rear E3 in Figure 2, ]01 or setting i-
'Roll 1 (Step S b I ). Next, when the process proceeds to step Sb2, the address data DI is transferred to the address bus 5.
The data S C'I' R (FIG. 2) in Eliato] 2 is output to the data bus 4 from time to time. According to Goi 1,
A signal S1 is output from the address decoder 17, and this signal S+ causes the data S C
T R is read, and a "do" signal (II level signal) is output from the output terminal corresponding to this data S C'l' It.

Now, if the data S CT 11 is [11 (hereinafter, this case will be explained as an example), the decoder &
A "1" signal is output from the output terminal <1> of the latch 16 to the column line R1. Next, when the process advances to step Sb3, address data l)3 is output to the address bus 5.

This causes the address decoder 26 to output a signal S3, and this signal S3 causes the input data to be sent to the manual boat 25 in parallel according to the on/off state of each panel switch 13a connected to the column line R1. Loaded. For example, when only the switch 13a connected between the row line L a I and the column line It + is in the on state, data "1, 0..., 0" (8 hits) is input to the input board. 2
5, and switch 13 between row line L a I and column line RI, and between row line 1, a2 and column line 1 (b).
When a or J( is on, the data “1, 1.
0.・, 0" (8 hzu) is read. Then, 4 or -ta is output to 12'-tahas4.
reactor. Next, Sfu-tsubu! If you go to Eb41, there will be a human capo)
- The data in 25 is written in the buffer area 111i corresponding to SCn 'r': (FIG. 2). For example, in the case of data S CRi' or 111, f(i ++ 戊S
Write in W1') (+). Next step 81
Proceeding to step 15, data S Ci' in area I.
R is incremented, which results in the same result.
``i'' + 7 or 12''. Next step 51)6
Proceeding to step 3, it is determined whether the data SC'T' R is "9" or not. If the result of this judgment is rYl-C8I (proceeds to f step Sb7, the data S Ci'I, for example, 111 or PI is written into the area "I'l.]2,
Further, in the case of 1-N (jl), the step Sb7 is jumped and the process proceeds to step Sb8. In this case, the determination result is 1N01, and the process proceeds to step 51)8. Step S
At b8, data 1 is incremented by 1, and thus becomes data 1 or 111.

Next, proceeding to step Sh9, it is determined whether take 1 is 141 or not. In this case, the judgment result is not "NO"), and go to step 5))2.

Next, the process of step Sl]2 is performed, and in this case, since the data S Ci''lj is [21,
``I'' is output from the output terminal <2> of the data I-data & latch 16 (A1).Next, proceeding to step Sh3, the column line R
The on/off state of each panel switch 13a connected to 2 is written into the input port 25, and then when the process proceeds to step Sb4, the data in the input port 25 is written to the buffer J, Tl(l>). Let's go.

Next, proceeding to step S b [i, data S Ci'
When R becomes 131 and the process then proceeds to step Sb8 via step Sb6, data I becomes [2j, and then the process returns to step Sb2 again via step Sh9.

Thereafter, the same process is repeated, and as a result, the column line 11
The on/off state of each panel switch 13a connected to 1-114 is determined by the area SW in the buffer area BE.
Write sequentially to D (b) to SwDc4). next,
Step 51) j, -(-t'-ta8C'1)
blasphemy (ka151 and na C), then \'su-7-...knob',
'r 1+ 8 L no Shojo Tanuki makes 7・-Yu I 1.
4: To Groto, Sufu-NojS1) 9's 'l'-111
1'li Yuri ga l YE', S mira 0, Figure 4 (7)
If・- Return to Chin.

Go to the routine in Figure 4 [ml, step...lpSa:
(α) Do something. 4゛ na i') 1 Baatressune ゛-91〕l to address bus 5, soil noni, J, rear I.]1 inside α)-71-ta I? Ci' I? (Second
) has been sent to Data No. 4 for a long time, and as a result, Data! ? Set in CI"R or differential latch 16. Next, proceed to steering knob Sa4, address data 1]2 or address bus 5, and data 11.
4 data SWMII, M (b1C1
For example, when data l?

This step Sa4 is 111! ), the data SW MEM ((<Ci' I
E) 1) Read 1, temporarily stop 1j by processing step Sal, and 111 open L) 8 17F, DI 3 b drive. Part 1. and return to the main routine.

Next, in order to output the interrupt signal TIM I again, the driving of L E I 311 is -
The on/off state of each panel switch 13a connected to the column lines R5, R6, R7, and R8 is the area S W E (5
).

Write sequentially into 5WE(6), S~E(7), swtr, and (8). Thereafter, each time the interrupt signal 'I'' IM+ is output, the process described in )-- is repeated.

Next, the case where the interrupt signal 'I' I M 2 is output from the frequency dividing circuit 7 will be explained. In this case, C.P.
[Processing in step 11 first proceeds to step Scl in FIG. 6, where data RCT I'? is incremented.

Through this process, the data RC'T' Tl or, for example, "
2” and Zuro. Next, when the process advances to step Sc2, it is determined whether the data RC'I'R is [9]. If the result of this judgment is 1-YES or 1, the process advances to step Sc3 and the data It CT It is set to 1-11. If the result of judgment in step Sc2 is rNOJ, step Sc3 is skipped. Ste Tsubu Sc4
Proceed to. In the case of the l-notation example, the determination result in step Sc2 is [N01], and the process advances to step Sc4. Ste Tsubu S
At c4, go to address data Dl or address number 5,
Also, output the data 11 C'I" Rl 2-1 to the data bus 4. As a result, the data 1tcT1
1r21 is read into the decoder & latch 16, and as a result, a "do" signal is output to the column line R2.Next, when the process advances to step Sc5, the address data [)2 is transferred to the address bus 5, and as shown in FIG. Data SWMEM (RC"r"
lj ) (if ko(7), data SWMI'>M(2))
are output to the data bus 4, and then the process returns to the main routine. When the process of step Sc5 is performed,
Data SWMEM (2) is read into the latch 22, and Jim;
Then, LEDI3h connected to column line R2 is driven. That is, for example, data SWMEM (2) is “
1, 1, 0.・If it is 0'', transistors 20-1 and 20-2 are each turned on (), and as a result,
Between column line R2 and row line Lhl, column line 1e2 and row line Lb2
l l>I) l : (h or lit 4). Furthermore, the data It e l' R or [21 [
), the output signal 1 (or output signal 1 +
, Tari line 1 (b, R: (~I is 8 yes LI~I] m "0
°'Believe in ゛, Shi8ka・ζ, +ll line Ill, R3
~ There is no LED I3b connected to I1 or drive I1.

This, j, interrupt signal i, H'1゛INi 2, frequency divider circuit 7, 1', slope 1, OK, -?゛-ta RCi' +7 is an inter-member!・Sai 1, then c1 The data Rc'I''R is 1-4-column lines 171 to 1 (
Connect to 8 terminal L E l'l +3 h or data S W M l-: M (b? CI'!?)
Driven on the basis of Now, interrupt signal i, 71'
If l M 2 is shown in Figure 3 (a) and 4-mono and 4゛, then
The column lines R1 to R8 are driven at the timing shown in FIG. 4゛rope t'), each L I: 1) I
3h should be driven intermittently for each column line.

Note that the driving period '1' of 1, IE I) I 3 b is, for example, 125 m5ec (l 00 It z).

On the other hand, as mentioned above, the interrupt signal TIM+
or is output from timer 6, -・Il, L E I
) l 3 b is activated or deactivated, and panel switch 1
The on/off state of 3a is read. The interrupt signal 1' I M I is shown in Figure 3 (c).
'2, line line I
The driving quiminter (f) of tI is actually 4'9 in FIG. Note that the panel switch l,'(aO
)-4 ON/OFF state reading〆jlJ, short time 1jl-c
Since each line/t can be done, interrupt (b□-)'1'1
N11 ()) 'l: Read data of 1/1j to f+j', -) Nishijiro (see Figure 5 l! ().

How many columns of data should be read into the interrupt node 11+j of the interrupt signal +s 'r + h4+?
: rz3b's / (small or t') rank or not J, I,
' -j (bi(7 must be decided.

Also, I detoured to 111j. L sea urchin, 73 trusts including discount 10+;
'l'' l M 1 and 4], and i' l M 2 generate 1 at the same time, the interrupt signal 1' l M + is processed. (see t1)
.

Next, as shown in FIG.
114-ro. CI) jl I +J, 1. Steps 4 to 5 are shown in the diagram, except when performing the above-mentioned C) included knob processing.
(b1-5 (Repeat the process of b4?14'Ro.Ma4
-, Step 8 (In b1, scan the key switch installed in the old keyboard of the keyboard to detect the on/off state,
Next, in the working area W (-1t
Write t +< (Figure 2). Next step 5 (b
When proceeding to step 2, it is checked bit by bit whether the data indicating the on/off state of the panel switch 13a written in the buffer area r3E has changed compared to the previous execution of step 5 (b2). Then, if there is a bit changing from "0°' to "1", the corresponding data SWIVIEM(+) to SWMEM(8) in the switch data area SWE is checked. Rewriting is performed (step 5d3).

For example, the second pid of the data indicating the on/off state of each switch 13a connected to the column line R1 is "0-"1.
Suppose that it changes to . This means that the panel switch 13a-1 shown in FIG. 1 is turned on.
It's true. In this case, the second bit of the data SWMEM(+) is inverted in step S (b3).As a result, if L E D l 3b-1 in FIG. 1 has been on, it is turned off. , and if it is off, it will be turned on.Next, if you proceed to step 5 (b4) in Figure 7,
Data SWME in the working area ~ Information about the keys in I
M(+) to SWMICM(8) are each output to the l·-nnoenerator 8. Then, the process returns to step Sdl.

Note that the above embodiment is based on Pu[Nokura! , the processing may be performed by hardware. Further, a multistage illuminated switch may be used instead of the on/off switch 13a. In addition, in the L period embodiment, the row line La
Although the row lines LhI-Lb8 and the row lines LhI-Lb8 are provided separately, the row lines LbI-Lb8 may not be provided and the row lines LaI-La8 may be made common.

"Effects of the Invention" As explained in Section 1, according to the invention, the 7-tricks circuit for detecting the on/off state of the switch is shared by the drive of the display means, so that the circuit configuration is improved. is placed inside the cylinder, which has the effect of lowering the price.

[Brief explanation of drawings]

Figure 1 does not show the configuration of one embodiment of the present invention; Figure 2 shows the same embodiment; The figure is I, E +') I 311
4 to 7 are flowcharts 1 for explaining the operation of the same embodiment. 11...7 trix circuit, 13a... panel switch, 131)... L r> I), 16... decoder & ludge, 19... L ED l' live circuit, 25... human powered boat. Applicant 1] This Musical Instrument Manufacturing Co., Ltd.

Claims (1)

[Claims] (a) a plurality of switches; (b) display means provided corresponding to each of these switches to display the operating status of these switches; (c) a plurality of column lines and a matrix circuit having a plurality of row lines, wherein the switch and the display means corresponding to the switch are inserted at the intersections of the column lines and the row lines; (d) column lines of the matrix circuit; (e) a storage means for temporarily storing data obtained on the row lines (or column lines) of the matrix circuit; (f) first driving means for driving the row lines (or column lines) of the matrix circuit; A panel device for an electronic musical instrument, comprising: second driving means for driving (or column lines) according to data stored in the storage means.