KR930010719A - Color Mimic Circuit for Color Program Execution - Google Patents

Color Mimic Circuit for Color Program Execution Download PDF

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Publication number
KR930010719A
KR930010719A KR1019910020390A KR910020390A KR930010719A KR 930010719 A KR930010719 A KR 930010719A KR 1019910020390 A KR1019910020390 A KR 1019910020390A KR 910020390 A KR910020390 A KR 910020390A KR 930010719 A KR930010719 A KR 930010719A
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KR
South Korea
Prior art keywords
color
video memory
color mode
output
start address
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KR1019910020390A
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Korean (ko)
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KR940006837B1 (en
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박오찬
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정몽헌
현대전자산업 주식회사
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Priority to KR1019910020390A priority Critical patent/KR940006837B1/en
Publication of KR930010719A publication Critical patent/KR930010719A/en
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Publication of KR940006837B1 publication Critical patent/KR940006837B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/87—Regeneration of colour television signals
    • H04N9/89—Time-base error compensation
    • H04N9/896—Time-base error compensation using a digital memory with independent write-in and read-out clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음No content

Description

칼라프로그램 실행을 위한 칼라 모방회로Color Mimic Circuit for Color Program Execution

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 칼라 모방 회로의 구성도.1 is a block diagram of a color imitation circuit according to the present invention.

제2도는 본 발명에 의한 칼라 모방 회로의 실행시 화면을 표시하는 비디오 메모리의구성도.2 is a configuration diagram of a video memory for displaying a screen upon execution of a color imitation circuit according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1,2 : 래치 3 : 비디오 메모리1: 2 latch 3: video memory

10 : 칼라모드 상태 인식부 20 : 칼라모드 비디오 메모리 구별부10: color mode state recognition unit 20: color mode video memory distinguishing unit

30 : 비디오 메모리 시작번지 지정부 B1,B2,B3 : AND 게이트30: Video memory start address designation part B1, B2, B3: AND gate

B4,B5,B6 : 배타적 OR 게이트 B7 : OR 게이트.B4, B5, B6: exclusive OR gate B7: OR gate.

Claims (4)

한글카드를 이용한 칼라 프로그램을 실행하기 위한 칼라모방회로에 있어서, 화면을 표시하는 비디오 메모리수단(3), 그래픽 데이타와 입출력신호(/IOW)를 입력으로 하여 칼라 프로그램 실행을 위해 칼라 모드를 인식시켜주는 칼라모드 상태 인식수단(10), 상기 칼라모드 상태 인식수단(10)에 연결되고 메모리 시작 번지 지정신호(PAGE#)를 입력으로 하여 상기 비디오 메모리수단(3)의 시작번지를 지정하는 비디오 메모리시작번지 지정수단(30), 상기 칼라모드 상태 인식수단(10)과 상기 비디오 메모리 시작번지 지정수단(30)에 연결되고 라스터 어드레스신호(RA0,RA1)와 텍스트 상태신호(/TXT)를 입력으로 하여 칼라모드인 경우상기 비디오 메모리수단(3)의 시작번지를 지정하여 메모리 어드레싱을 다르게 하는 칼라모드 비디오 메모리 구별수단(20), 및 상기 칼라 모드 비디오 메모리 구별수단(20)과 비디오 메모리 시작번지 지정수단(30)의 출력과 메모리 지정신호(/CRTCRAS)와 리프레쉬 메모리 어드레스 신호(MA8 내지 MA11)를 입력으로 상기비디오 메모리수단(3)으로 비디오 메모리 번지 지정 어드레스 신호(DRA0 내지 DRA6)를 출력하는 래치수단(2)으로 구성되는 것을 특징으로 하는 칼라 모방 회로.In a color imitation circuit for executing a color program using a Hangul card, the video memory means (3) for displaying a screen, graphic data and input / output signals (/ IOW) are input to recognize a color mode for color program execution. A video memory is connected to the color mode state recognition means 10 and the color mode state recognition means 10, and inputs a memory start address designation signal PAGE # to designate a start address of the video memory means 3; It is connected to a start address designation means 30, the color mode state recognition means 10, and the video memory start address designation means 30, and inputs raster address signals RA0 and RA1 and text status signals / TXT. In the color mode, the color mode video memory distinguishing means 20 for differentiating memory addressing by designating a start address of the video memory means 3, and the color mode. Video memory means (3) and video memory start address designation means (30) and the output of the memory designation signal (/ CRTCRAS) and the refresh memory address signal (MA8 to MA11) as input to the video memory means (3) And a latch means (2) for outputting address designation address signals DRA0 to DRA6. 제1항에 있어서, 상기 칼라모드 상태인식 수단(10)은 그래픽 데이타와 입출력신호(/IOW)를 입력으로 하는 래치(1)로 구성되는 것을 특징으로 하는 칼라모방회로.2. The color mimic circuit according to claim 1, wherein said color mode state recognition means (10) comprises a latch (1) for inputting graphic data and input / output signals (/ IOW). 제1항에 있어서, 상기 비디오 메모리 시작번지 지정수단(30)은 상기 칼라모드 상태 인식수단(10)의 출력과 메모리 시작번지 지정신호(PAGE#)를 입력으로 하는 논리합 수단(B7)으로 구성되는 것을 특징으로 하는 칼라모방회로.2. The video memory start address designating means (30) according to claim 1, wherein the video memory start address designating means (30) comprises an output of the color mode state recognizing means (10) and a logical sum means (B7) for inputting a memory start address designating signal (PAGE #). Color imitation circuit, characterized in that. 제1항에 있어서, 상기 칼라모드 비디오 메모리 구별수단(20)은 상기 라스터 어드레스 신호(RA0,RA1)를 입력으로 하는 제1배타적 논리합 수단(B4), 상기 칼라모드 상태인식 수단(10)과 제1배타적 논리합 수단(B4)의 출력을 입력으로 하는 제1논리곱수단(B3), 상기 제1논리곱수단(B3)의 출력과 상기 라스터 어드레스신호(RA0)를 입력으로 하는 제2배타적 논리합수단(B5), 상기 제1논리곱수단(B3)의 출력과 상기 라스터 어드레스신호(RA1)를 입력으로 하는 제3배타적 논리합수단(B6), 상기 제2배타적 논리합수단(B5)의 출력과 텍스트 상태신호(/TXT)를 입력으로 하는 제2논리곱 수단(B1), 및 상기 제3배타적 논리합 수단(B6)의 출력과 텍스트 상태신호(/TXT)를 입력으로 하는 제3논리곱 수단(B2)으로 구성되는 것을 특징으로 하는 칼라모방회로.2. The color mode video memory distinguishing means (20) according to claim 1, wherein the color mode video memory distinguishing means (20) comprises: first exclusive logical sum means (B4) for inputting the raster address signals (RA0, RA1) and the color mode state recognition means (10); First logical multiplication means B3 for inputting the output of the first exclusive OR means B4, second exclusive input for output of the first logical multiplication means B3 and the raster address signal RA0. Logic sum means (B5), the output of the first logical multiplication means (B3) and the third exclusive logic sum means (B6) for inputting the raster address signal (RA1), the output of the second exclusive logic sum means (B5). And second logical multiplication means B1 for inputting the text status signal / TXT, and the third logical multiplication means for inputting the output of the third exclusive OR means B6 and the text status signal / TXT. A color imitation circuit comprising: (B2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020390A 1991-11-15 1991-11-15 Circuit for color emulation KR940006837B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910020390A KR940006837B1 (en) 1991-11-15 1991-11-15 Circuit for color emulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910020390A KR940006837B1 (en) 1991-11-15 1991-11-15 Circuit for color emulation

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KR930010719A true KR930010719A (en) 1993-06-23
KR940006837B1 KR940006837B1 (en) 1994-07-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448483B1 (en) * 1996-12-30 2005-01-26 엘지전자 주식회사 Digital computing system using removable ram/rom as portable sub storage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448483B1 (en) * 1996-12-30 2005-01-26 엘지전자 주식회사 Digital computing system using removable ram/rom as portable sub storage

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KR940006837B1 (en) 1994-07-28

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