JPS62152268A - Image signal processor - Google Patents

Abstract

PURPOSE:To execute the processing area control of plural image processing circuits and the designation of plural areas with the circuit of one system by providing a memory to store main scanning address data for the area designation and address data to show the data address. CONSTITUTION:The output of a flip-flop 17 controls multiplexers 11, 14 and 15 so that RAMa12 can be a writing condition and RAMb13 can be a reading condition. When a CPU writes the data from the minimum address of the RAMa12 to the RAMa12 in the small sequence of a main scanning address and completes to write them, the output 34 of a flip-flop 18 is inverted by a RAM data renewing completing signal 35. An address data part 25 of the data read from the RAMa12 is respectively inputted to AND gates 7, 8 and 9. Processing circuits 1, 2 and 3 execute the different processing according to the fact that the output of the AND gates 7, 8 and 9 is '1' or '0'. By renewing the data of the RAMa12 or the RAMb13 with the prescribed timing, the CPU executes the designation of the area in the sub-scanning direction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing device for processing a rask scan image signal.

2. Description of the Related Art In recent years, there has been a need for faster processing and simpler hardware in image signal processing apparatuses that perform various types of processing on large amounts of image data.

When processing image signals in a desired area of an image differently from areas other than the area, area detection means is required to notify the processing circuit whether the image signal being processed is within the area or not. . When a plurality of processing circuits are serially connected in a pipeline, and when setting the processing area of each processing circuit, the number of the area detecting means and the area setting means for setting the processing area is equal to the number of the plurality of processing circuits. Generally, it is provided.

An example of the conventional image signal processing device mentioned above will be described below with reference to the drawings.

FIG. 4 is a block diagram of a conventional image processing device. Fourth
In the figure, 51 is an image signal processing circuit that processes an image signal 61 and outputs the processed image signal 62, and 66 is a CPU.
The data bus 54.56 is a latch that holds data from the CPU, and the data bus 53.55 compares the data from the launch 54.56 with the main scanning address 68 indicating the position of the image signal in the main scanning direction, and outputs a match signal 64.56. 67, and 52 is an RS flip-flop that outputs a signal 63 which is set and reset by the outputs of the comparators 53 and 55.

The operation of the image signal processing device configured as above will be described below.

Latch 54 holds the starting main scan address of the desired image area, and launch 56 holds the ending main scan address of said image area. When the main scanning address 68 and the starting main scanning address 65 of the image area, which is the output of the latch 54, match, the comparator 53 outputs a match signal 64 and causes the RS flip-flop 52 to enter. The output of the RS flip-flop 52 is input to the processing circuit 58.
1 performs necessary image processing on the image area. The comparator 55 outputs a match signal 67 and resets the RS free knob flop 52 when the main scanning address 68 and the end main scanning address 69 of the image area, which is the output of the launch 56, fail.

A processing circuit 51 controlled by the output 63 of the RS flip-flop completes the necessary image processing for said image area. Area specification in the sub-scanning direction is performed by the CPU rewriting the main-scanning addresses for area specification in the latches 54 and 56 when the image signal 61 enters a desired sub-scanning area. (For example, Japanese Unexamined Patent Publication No. 189772/1982) Problems to be Solved by the Invention However, in the above configuration, a plurality of image processing circuits that process various image signals are serially connected in a pipeline. In this case, a circuit for specifying the processing area is required for each processing circuit, and when setting multiple areas in the main scanning direction, the number of latches and comparators shown in Figure 2 increases, so the scale of the hardware becomes large. It had the problem of becoming

In view of the above-mentioned problems, the present invention provides an image processing apparatus in which image processing circuits are serially connected in a pipeline manner, in which processing area control of each processing circuit is realized by simple hardware.

Means for Solving the Problems In order to solve the above problems, the image processing apparatus of the present invention is provided with a memory that stores main scanning address data for specifying an area and destination data indicating the destination of the data.

Effect: By providing the memory, the present invention can control the processing areas of a plurality of image processing circuits and designate a plurality of areas using a single circuit.

Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit for controlling a processing area of an image processing apparatus according to the present invention. In Figure 1,
1 is a processing circuit that processes the image signal 21a, 2 is a processing circuit that processes the image signal 21b, 3 is a processing circuit that processes the image signal 21C, and 4, 5.6 is a control that controls the processing circuits 1, 2.3. T4 flip-flops 7 and 8°9 output signals, respectively, and T4 flip-flops. 5.
6 is an AND gate that outputs a toggle signal, 1° is a comparator that compares a part of the output of the multiplexer 11 with the main scanning address 24, and outputs a match signal 23; 11 is a RAM a 12 or RAM M b 13 A multiplexer 16 selects the read data, a counter 16 counts the one-defeat signal 23 and outputs the read address 29 of RAMa or RAMb, and 3o selects the RAMa 12 or R
A CPU address bus (not shown) specifies the write address of AMb13, 31 is RAMa12 or RAM
b cPU data bus that transfers the write data of 13, 14.15 is a multiplexer that selects the write address, write data, and continuation address of RAMa12 or RAMb13, 35 is the RAM data update end signal output by the CPU, 18 is the RAM 33 is a sub-scanning synchronizing signal which is a negative pulse indicating the start of main scanning of the image signal 21; 17 is an output 3 of T and flip-flop which is toggled by the data update end signal 35;
4 is launched by the sub-scanning synchronizing signal 33, and outputs control signals for the multiplexers 11, 14, and 15, and is a flip-flop.

FIG. 2 shows the contents of data written to RAMa12 or RAMb13 in FIG. 1.

The lower focus is a main scanning address that sets the processing area, and the upper bit is destination data indicating which processing circuit the main scanning address of the lower bit is valid for, and the processing circuit for which the main scanning address is valid. Set the bit to "1".

The operation of the embodiment of the present invention configured as described above will be described below.

Now, the output of flip-flop 17 is RAM a 1
Assume that the multiplexers 11, 14, and 15 are controlled so that RAMb13 is in the write state and RAMb13 is in the read state. That is, the addressing of RAM a 12 is done by the CPU.
The write data is written by the address bus 30 of the CP.
Sent from U. RAMb address specification is counter 1
6, and the multiplexer 11 outputs RA
Select the output data of M b 13.

The CPU writes the data shown in FIG. 2 to the RAMa 12 in order of decreasing main scanning address, starting from the smallest address of RAMa. C
When PU finishes writing data to RAMa12,
An AM data update end signal 35 is output. The RAM data update end signal 35 inverts the output 34 of the flip-flop 18. Flip-flop 17 is a flip-flop.
The output 34 of the flop 18 is latched in synchronization with the sub-scanning synchronization signal 33, and the signal 32 is outputted to the multiplexer 11.
14. Control 15 and write RAMb13, RA
Ma12 is placed in the read state. The counter 16 is set by the sub-scanning synchronization signal 33, indicates the minimum address of the RAM a 12, and reads data from the RAM a 12.

The data read from RAM a 12 passes through the multiplexer 11, and the main scanning address portion 26 of the data read from RAM a 12 is input to the comparator 10. The comparator 10 compares the main scanning address 24 of the image signal 21 and the main scanning address portion 26 of the data read from the RAM a 12, and outputs a coincidence signal 23 when they match. Match signal 23 is counter 1
6 is incremented and the next read address 29 of RAMa 12 is output. The destination data portion 25 of the data read from RAMa is input to AND gates 7, 8, and 9, respectively. AND gates 7.8.9 each gate the match signal 23 with the destination data 25, and the output of each AND gate is input to a flip-flop 4.5.6, each connected to a processing circuit 1.2.3. be done. After being reset by the sub-scanning synchronizing signal 33, the flip-flops 4, 5, 6 are reset by the sub-scanning synchronizing signal 33, and then the flip-flops 7, 8, 9
A toggle signal is outputted to the processing circuits 1, 2.3, respectively. Processing circuits 1 and 2.3 are AND gates 7.8
．． Different processing is performed depending on whether the output of 9 is "1" or "0".

The CPU specifies an area in the sub-scanning direction by updating data in RAM a 12 or RAM b 13 at a predetermined timing.

FIG. 3 shows an embodiment of an image processing circuit (corresponding to processing circuit 1.2.3 in FIG. 1) used in a digital copying machine or the like.

In FIG. 3A, the area designation signal 43 is 'I' for the human image signal 40.
It is passed only when J, and the processed image signal 11 is output. Similarly, in B, only the area designation signal 43 of "1" is inverted. In C, two slice levels 55 and 56 are selected by a multiplexer 54 based on the area designation signal 43, and a comparator 53 compares the input image signal 40 with the selected slice level 57 to binarize the image signal.

As described above, the present invention provides a system for specifying an area by providing a memory that stores a main scanning address for specifying an area and destination data indicating which image processing circuit the main scanning address is valid for. A circuit can control multiple image processing circuits.

Effects of the Invention As described above, the present invention allows a plurality of image processing circuits to be controlled by a single system of area specification circuits, so even when there are many image processing circuits, the scale of the hardware can be reduced. . Further, since the destination data is used when specifying the same area to two or more image processing circuits, there is no need to set the same area data in each image processing circuit. Moreover, even if there are many areas designated in the main scanning direction, the scale of the hardware does not need to increase.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit for controlling the processing area of the image processing device according to the present invention, and FIG. 2 is a block diagram showing the RAM shown in FIG. 1.
Figure 3 is a circuit diagram of an embodiment of an image processing circuit used in a digital copying machine, etc.;
The figure is a block diagram of a conventional image processing device. 1.2.3...-Image processing circuit, 4. 5. 6
．． 18... Toggle flip flop, 12.
13. Old... RAM, 10.53... Comparator, 16... Counter, 21, 61...
...Image signal, 24.68...Main scan address, 30...CPU address bus, 31.66...
. . . CPU7'-TAHAS, 33 . . . Sub-scanning synchronization signal, 35 . . . RAM data update end signal, 11.14.15.54 . . . Multiplexer. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 Figure 2 -------~ Figure 3 Figure 4, s/

Claims (1)

[Claims] A plurality of image signal processing circuits are serially connected in a pipeline, and main scanning address data indicating an area to be processed in the main scanning direction and main scanning address data are transmitted to which processing circuit among the plurality of image signal processing circuits. 1. An image signal processing device, comprising: a memory for storing destination data indicating whether the destination data is valid for the image signal processing device.