JPH0351010B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an information processing device, and more particularly to a memory content processing method of a main storage device in an information processing device.

Prior Art As a processing method for storing information from an arithmetic processing unit to a main memory device, the so-called so-called method is generally used because the arithmetic processing unit can move on to the next processing step without waiting for the completion of storing the information. A store buffer is used. In other words, the store request output from the arithmetic processing unit is temporarily stored in the store buffer, at which point the arithmetic processing unit starts the next process, and from this store buffer, the main storage device is checked to see if it can be sent. The store request will be sent later.

By the way, when a store request is sent from an arithmetic processing unit, if a copy of the storage location of the main storage device where the store data of this store request is to be stored exists in the buffer memory, a copy of this storage location is stored using the store data. It will be necessary to update. Therefore, in this type of information processing device, in addition to the above-mentioned store buffer for synchronizing the sending timing of store requests from the arithmetic processing unit to the main storage device, another store buffer is used for synchronizing the timing of updating the buffer memory by the store request. It is set up independently.

Therefore, there is a drawback that two store buffers are required, resulting in an increase in hardware.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can reduce hardware by providing a single request store buffer having a main memory flushing function and a buffer memory flushing function.

Configuration of the Invention According to the present invention, a main storage device, a buffer memory that temporarily stores the contents of the main storage device,
an arithmetic processing unit that generates store request information consisting of store data and a store address for instructing data writing to the main storage device; an information processing apparatus that includes means for detecting whether the store request information is stored in the store request information and generating storage presence display information, the store buffer having a plurality of entries capable of storing a plurality of store request information; a display buffer having a plurality of entries provided correspondingly and capable of storing the storage presence/absence display information; and a display buffer having a plurality of entries capable of storing the storage presence/absence display information; a writing means for sequentially writing to corresponding entries in the buffer;
a first reading means for sequentially reading the contents of the entries in the store buffer and sending them to the main storage device asynchronously with the occurrence of the store request; and a correspondence between the store buffer and the display buffer asynchronously with the occurrence of the store request. A second reading means sequentially accesses the contents of the entries and sends the contents of the corresponding entry of the store request to the buffer memory only when the entry contents of the display buffer at that time indicate that storage is present. An information processing device is obtained.

Examples Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
1 is an arithmetic processing unit, 2 is a main memory, 3 is a store data buffer section, 4 is a store address buffer section, 5 is an address array of the buffer memory, and 6 is a data array of the buffer memory. Also, 7
is a store data register, 8 is an address register, 9 is a data array write register, 10 to 12
1 is a selector, 13 and 14 are comparators, and 15 is a control unit.

FIG. 2 is a diagram showing a specific example of the store data buffer unit 3 and store address buffer unit 4 in FIG. 1, where 3-1 is a store data buffer, 3a is a write pointer, and 3b and 3c are read pointers. , 4-1 is a store address buffer, and 4-2 is a buffer memory sweep display buffer.

The operation of the embodiment of the present invention will be described in detail below using FIGS. 1 and 2.

First, regarding the read operation, when a read request is issued from the arithmetic processing unit 1, the read address is stored in the address register 8 via the selector 10, the address array 5 is indexed by the output, and the comparator 14 Then, it is detected whether the corresponding block exists in the data array 6 (hereinafter referred to as read FDB). At the same time, based on the output of the address register 8, the comparator 13 detects whether a store request with the same address exists in the store buffer (hereinafter referred to as a store address match).

If a read FDB is detected and no store address match is detected, data array 6
The corresponding data is read out from and sent to the arithmetic processing unit 1. If a read FDB is not detected and a store address match is not detected, a read address is sent from the address register 8 to the main storage device 2 via the selector 12, the corresponding block is read, and the read data is subjected to arithmetic processing. The signal is sent to the device 1 and stored in the data array write register 9 via the selector 11, so that the data array 6 is updated. If a store address match is detected, the read address is held in the address register 8 until the corresponding entries in the store address buffer 4-1 and store data buffer 3-1 are flushed out, and after the above flushing is performed. The above read operation is performed.

Regarding the store operation, a store request is issued from the arithmetic processing unit 1, a store address is stored in the address register 8 via the selector 10,
On the other hand, the store data is stored in the store data register 7. The address array 5 is indexed by the output of the address register 8, and the comparator 14 determines whether the corresponding block exists in the data array 6 (hereinafter referred to as store).
FDB) is detected, and the information is stored in the entry of the buffer memory sweep display buffer 4-2 specified by the write pointer 3a, and at the same time, the information is stored in the entry of the store address buffer 4-1 from the address register 8. The store address and store data from the store data register 7 are respectively stored in the entries of the store data buffer 3-1, and the write pointer 3a is incremented.

With the above operations, the arithmetic processing device 1 assumes that the store request has been processed and moves on to the next process.

The following two store buffer operations are performed asynchronously with the above operation. The first operation is the main memory 2
If it is a purge operation and a request can be sent to the main storage device 2, the first read pointer 3b
The store data of the entry in the store data buffer 3-1 specified by is sent to the main storage device 2, and the store address of the entry in the store address buffer 4-1 is sent to the main storage device 2 via the selector 12. and the first read pointer 3b is incremented.

The second operation is a sweep operation to the buffer memory, and if the entry of the buffer memory sweep display buffer 4-2 specified by the second read pointer 3c does not indicate a store FDB, the second read pointer 3c Only increments are done. The above entry indicates the store FDB,
If the buffer memory can be updated, the store address, which is the entry of the store address buffer 4-1 indicated by the second read pointer 3c, is stored in the address register 8 via the selector 10;
Store data, which is an entry in store data buffer 3-1, is stored in data array write register 9 via selector 11, and address register 8
The contents of data array write register 9 are stored in the entry of data array 6 specified by the output of .

Effects of the Invention As described above, according to the present invention, since one store buffer is provided with a main memory cleaning function and a buffer memory cleaning function, it is possible to reduce the hardware of an information processing device. This has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing details of the store buffer of FIG. 1. Explanation of symbols of main parts, 1...Arithmetic processing unit,
2...Main storage device, 3...Store data buffer section, 4...Store address buffer section, 5...Address array, 6...Data array, 7...Store data register, 8...Address register, 9
...Data array write register.

Claims (1)

[Claims] 1 A main storage device, a buffer memory that temporarily stores the contents of the main storage device, and an operation that generates store request information consisting of store data and a store address for instructing the main storage device to write data. An information processing device including a processing device, and means for detecting whether or not corresponding store data is stored in the buffer memory in response to generation of the store request, and generating storage presence/absence display information, a store buffer having a plurality of entries capable of storing a plurality of pieces of the store request information; a display buffer having a plurality of entries provided corresponding to the respective entries and capable of storing the storage presence/absence display information; writing means for sequentially writing corresponding store request information and corresponding storage presence/absence display information into corresponding entries of the store buffer and the display buffer in response to each of the above; A first reading means for reading and transmitting the data to the main storage device sequentially accesses the contents of the corresponding entries in the store buffer and the display buffer asynchronously with the occurrence of the store request, and reads the contents of the entry in the display buffer at that time. An information processing device comprising: second reading means for sending the contents of the entry corresponding to the store request to the buffer memory only when the stored request is indicated.