JPH0488446A - Store buffer controller - Google Patents

Abstract

PURPOSE:To prevent the delay of the transmission of a reply signal to a data request part by sweeping data out of a store buffer until data which is the factor of a address coincidence is eliminated when the coincidence is detected. CONSTITUTION:An address comparison part control circuit 103 asserts a timing signal 121 when the virtual address of data is stored in a virtual address register 117, and an in-page address comparison part 101 detects an address coincidence. When the address coincidence is detected, the reply signal 123 is not sent out, an address comparison part 103 asserts a timing signal 122, and a physical address comparison part 102 detects an address coincidence. Data in a store data register 105 and a store data register 106 are swept out to a main storage until the data which is the factor of the address coincidence is eliminated, and then the reply signal 123 is sent out of a reply transmission part 104. Consequently, the delay of the transmission of the reply signal is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a store buffer control device for main memory writing.

[Conventional technology]

Conventionally, this type of store buffer control device includes a store buffer that holds a plurality of pairs of operation results in an operation execution unit and storage addresses for the operation results in main memory, and a data request unit that stores data in the main memory. A first address register that stores the read address output when making a request, and a second address register that receives the output of the first address register one clock later.
has an address register, and detects a match between each address stored in the address section of the store buffer and only a portion of the address stored in the first address register,
If an address match is not detected, a reply signal is sent to the data request unit at the next clock, and if an address match is detected, the data in the store buffer is flushed to the main memory, and the data that caused the address match is flushed out. It sends a reply signal after receiving the message.

[Problem to be solved by the invention]

In the conventional store buffer control device described above, a match is detected between each address stored in the address field of the store buffer and only a portion of the address stored in the first address register, and if a match is detected, the store is The data in the buffer is flushed out to the main memory, and after the cause of the address match is flushed out, a reply signal is sent to the data request unit, so even if part of the address matches but the whole address does not match, This has the drawback that the sending of a reply signal to the requesting section is delayed until the data that caused the address match is flushed out to the main memory, resulting in a drop in performance.

[Means for Solving the Problems] A store buffer control device according to a first aspect of the present invention includes a store buffer that holds a plurality of pairs of an operation result in an operation execution unit and a storage address of the operation result on a main memory; a first address register that stores a read address output when the data request unit requests data from the main memory;
a second address register that receives the output of the address register one clock later; and a first address register that detects a match between each address stored in the address section of the store buffer and only a portion of the address stored in the first address register. address comparison means, and one clock after the first address comparison means detects an address match, checks the overall match between each address stored in the address section of the store buffer and the address stored in the second address register. If an address match is not detected between the second address comparing means that performs the comparison and the first address comparing means, a reply signal is sent to the data requesting section at the next clock, and the first address comparing means detects that the address matches. If the pressure is detected, the second address comparison means waits for the comparison result, and if the second address comparison means does not detect an address match, a reply signal is sent in the next tarok, and the second address is compared with the second address comparison means. When an address match is detected, the data in the store buffer is flushed out to the main memory, and after the data that caused the address match is flushed out, a reply signal is sent out.

A store buffer control device according to a second aspect of the present invention includes a store buffer that holds a plurality of pairs of calculation results in the calculation execution unit and storage addresses of the calculation results on the main memory, and a data request unit for the main storage. a first address register that stores a read address output when requesting data;
a second address register that receives the output of the address register one clock later; and a first address register that detects a match between each address stored in the address section of the store buffer and only a portion of the address stored in the first address register. address comparison means, and one clock after address match detection by the first address and comparison means, the entire match between each address stored in the address section of the store buffer and the address stored in the second address register. a second address comparison unit that performs detection; an address comparison unit control unit that controls whether or not address matching detection is performed in the first address comparison unit depending on the type of request from the data request unit; In the case of a request for which address matching is detected by the comparing means, if address matching is not detected by the first address comparing means, a reply signal is sent to the data requesting section at the next clock, and the first
If the address comparison means detects an address match, the second address comparison means waits for the comparison result, and if the second address and comparison means do not detect an address match, a reply signal is sent at the next clock. , when an address match is detected by the second address and the comparing means, the data in the store buffer is flushed out to the main memory, and after the data that caused the address match is flushed out, a reply signal is sent, and the first In the case of a request for which address matching is not detected by the second address comparing means, if no address matching is detected by the second address comparing means, a reply is sent at the next clock, and if the address matching is not detected by the second address comparing means. If the pressure is detected, the data in the store buffer is flushed out to the main memory, and after the data that caused the address match is flushed out, the reply sending means is provided for transmitting a reply signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention.

The buffer storage control device of this embodiment includes an intra-page address comparison unit 101. It has a physical address comparison section 102, an address comparison section control circuit 103, and a reply sending section 104.

In the figure, store data register 105. The store data register 106 is a register for storing write data 107 from a data sending unit such as an arithmetic execution unit to the main memory.
9 and the contents of the store data register 105 or 106 selected by the selector 110 are written to the main memory.

Similarly, store address register 111. The store address register 112 is a register for storing the physical address 113 corresponding to the write data 107, and the physical address 113 is written according to the specification of the address write pointer 114, and the store address register is selected by the address read pointer 115 and the selector 116. The contents of 111 or 112 are sent to main memory.

The virtual address register 117 is a register that stores the virtual address sent from the address sending unit.The page address part is converted from a virtual address to a physical address by the TLB 118, and the address part in the page is directly stored in the physical address register 119. Stored.

The intra-page address comparison unit 101 compares whether the intra-page address part of the store address register 111 or 112 indicated by the address comparison register selection circuit 120 and the intra-page address part of the virtual address register 117 match. This is done according to the timing signal 121 given from the circuit 103.

Similarly, the physical address comparison unit 102 stores the store address register 111 or 112 indicated by the address comparison register selection circuit 120 and the physical address register 1.
A comparison is made to see if the physical addresses stored in the addresses 19 and 19 match in accordance with a timing signal B112 given from the address comparison section control circuit 103.

In the address comparison unit control circuit 103, the virtual address of the data requested to be read is stored in the virtual address register 117.
When the address is stored in the page, the timing signal 121 is asserted, and the intra-page address comparison unit 101 performs address matching detection. And if this result does not show an address match,
A reply signal 123 is sent from the reply sending unit 104 to the data requesting unit.

On the other hand, if the comparison result detects an address match, the reply signal 123 is not sent, and the address comparison section 103 asserts the timing signal 122, thereby causing the physical address comparison section 102 to detect an address match.

As a result, if no address match is detected, the reply signal 12 is sent from the reply sending unit 104 at the next clock.
3 is sent and if an address match is detected, store data register 105゜store data register 106
After sweeping out the data in the main memory until the data that caused the address match is exhausted, the reply sending unit 104
A reply signal 123 is sent from.

FIG. 2 is a block diagram showing an embodiment of the second invention.

The buffer storage control device of this embodiment also includes the page own address comparison unit 201. It has a physical address comparison section 202, an address comparison section control circuit 203, and a reply sending section 204.

In the figure, store data register 205. The store data register 206 is a register for storing write data 207 from a data sending unit such as an arithmetic execution unit to the main memory.
9 and the contents of the store data register 205 or 206 selected by the selector 210 are written to the main memory.

Similarly, store address register 211. The store address register 212 is a register for storing the physical address 213 corresponding to the write data 207, and the physical address 213 is written according to the designation of the address write pointer 214, and the store address register is selected by the address read pointer 215 and the selector 216. The contents of 211 or 212 are sent to main memory.

The virtual address register 217 is a register that stores the virtual address sent from the address sending unit.The page address part is converted from a virtual address to a physical address by the TLB 218, and the address part within the page is stored as is in the physical address register 219. be done.

The intra-page address comparator 201 compares whether the intra-page address part of the store address register 211 or 212 indicated by the address comparison register selection circuit 220 matches the intra-page address part of the virtual address register 217, and the address comparison part control circuit This is done according to the timing signal 221 given from 203.

Similarly, the physical address comparison unit 202 selects the store address register 211 or 212 indicated by the address comparison register selection circuit 220 and the physical address register 21.
A comparison is made to see if the physical addresses stored in the addresses 9 and 9 match in accordance with the timing signal B222 given from the address comparison section control circuit 203.

In the address comparison unit control circuit 203, the in-page address comparison unit 200 receives the command 224 from the command sending unit.
In step 1, it is decoded to determine whether the request is for address match detection or not, and if it is a request for address match detection in the in-page address comparison unit 201, it is read and compared and the virtual address of the requested data is determined. When the address is stored in the virtual address register 217, the timing signal 221 is asserted, and the intra-page address comparing unit 201 performs address matching detection.

If this result does not indicate address matching, a reply signal 223 is sent from the reply sending unit 204 to the data requesting unit. On the other hand, if the comparison result indicates that the addresses match, the reply signal 223 is not sent and the address comparison unit 2
When the timing signal 222 is asserted at 03, address matching detection is performed in the physical address comparison section 202.

As a result, if no address match is detected, a reply signal 22 is sent from the reply sending unit 204 at the next clock.
3 is sent, and if an address match is detected, the store data register 205. After the data in the store data register 206 is flushed to the main memory until the data that caused the address match is exhausted, the reply signal 223 is sent from the reply sending unit 204.

On the other hand, if the request does not perform address match detection in the intra-page address comparison unit 201, the timing signal 221 is negated and the physical address of the data requested to be read is set to the physical address register 201.
9, the timing signal 222 is asserted.

As a result, the intra-page address comparison section 201 does not perform address match detection, and only the physical address comparison section 202 performs address match detection.

As a result, if an address match is not detected, the reply signal 223 is sent from the reply sender 204 at the next clock, and if an address match is detected, the store data register 205. After sweeping out the data in the store data register 206 until the data that caused the address match disappears, a reply signal 22 is sent from the reply sending unit 204.
3 is sent.

〔Effect of the invention〕

As explained above, in the first aspect of the present invention, when a match is detected between each address stored in the address section of the store buffer and only a portion of the address stored in the first address register, the next clock compares each address stored in the address field of the store buffer with the entire second address register, and if a match is detected, the data in the store buffer is replaced with the data that caused the address match. By flushing out data until it is exhausted, there is an effect of improving performance by preventing a delay in sending a reply signal to a data requesting unit when there is no need to flush data from the store buffer to the main memory.

Furthermore, the second invention controls whether or not to perform matching detection between each address stored in the address section of the store buffer and only a portion of the address stored in the first address register, depending on the type of request. This has the effect of improving performance by preventing unnecessary delays in reply signals for requests that do not require matching in part of the address.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the first invention, and FIG. 2 is a block diagram of an embodiment of the second invention. 101.201...Intra-page address comparison section, 102
．． 202...Physical address comparison section, 103°203.
...Address comparison unit control circuit, 104.204...Reply sending unit, 105, 106, 205°206...
Store data register, 107, 207...Write data, 108.208...Data write pointer,
109,209...Data read pointer, 110,
116, 210, 216...Selector, 111, 11
2,211,212...address register, 113.
213...Physical address, 114.115.21,4
, 215...address write pointer, 117, 21
7...Virtual address register, 118.218...
TLB, 119, 219...physical address register,
120, 220...address comparison register selection circuit,
121, 122.221222... timing signal, 123, 223... reply signal, 224... command.

Claims (1)

[Scope of Claims] 1. A store buffer that holds a plurality of pairs of calculation results in the calculation execution unit and storage addresses of the calculation results in main memory, and a data request unit that requests data from the main storage. a first address register that stores the read address output when the store buffer is loaded; a second address register that receives the output of the first address register one clock later; a first address comparing means for detecting a match between the address and only a part of the address stored in the first address register; a second address comparing means for detecting an overall match between each address stored in the section and the address stored in the second address register; and an address match must be detected by the first address comparing means. For example, a reply signal is sent to the data requesting section at the next clock, and if address matching is detected by the first address comparing means, the comparison result by the second address comparing means is waited for, and the reply signal is sent to the data requesting section. If the comparison means does not detect an address match, a reply signal is detected at the next clock, and if the second address comparison means detects an address match, the data in the store buffer is flushed to the main memory and the address matches. 1. A store buffer control device comprising: a reply sending means for sending a reply signal after the data that caused the problem is swept out. 2. A store buffer that holds a plurality of pairs of operation results in the operation execution unit and storage addresses of the operation results on the main memory, and a store buffer that is output when the data request unit requests data from the main memory. In an information processing device having a first address register that stores a read address and a second address register that receives an output of the first address register one clock later, each address stored in the address section of the store buffer and a first address comparing means for detecting a match between only a part of the address stored in the first address; a second address comparison means for detecting a match between each address stored in the address register and the entire address stored in the second address register; an address comparison unit control means for controlling whether or not to perform address match detection at said first address comparison means; If not, a reply signal is sent to the data requesting unit at the next clock, and if an address match is detected by the first address comparing means, the second address comparing means waits for the comparison result, and the second If an address match is not detected by the second address comparison means, a reply signal is sent at the next clock, and if an address match is detected by the second address comparison means, the data in the store buffer is flushed to the main memory. A reply signal is sent after the data that caused the address match has been flushed out, and in the case of a request in which the first address comparing means does not detect a match, the second address comparing means detects an address match. If not detected, a reply is sent at the next clock, and if an address match is detected by the second address comparing means, the data in the store buffer is flushed to the main memory, and the data that caused the address match is flushed out. 1. A store buffer control device comprising: a reply sending means for sending out a reply signal after receiving a reply signal.