JPS6267649A - Store processing system for cache memory controller - Google Patents

Abstract

PURPOSE:To eliminate reset of a store address by providing a hit level buffer to store hit information of the object address of store operation. CONSTITUTION:When store operation is accepted, the object address of an address register 10 is stored in a store address buffer 60 and address arrays 20 and 21 of individual levels are referred to detect whether the object address is registered in a cache memory or not by comparators 30 and 31. If it is registered, a hit signal is outputted from comparators 30 and 31 and is stored in a hit level buffer 61, and the operation is terminated on a basis of contents of buffers 60 and 61, and store data stored in a store data buffer 62 is swept out to the cache memory. Consequently, it is unnecessary that the address of the buffer 60 is set again to the register 10 to detect hit after data is stored in the buffer 62 in case of this sweeping-out, and the sweeping-out processing is performed at a high speed without hindering the succeeding operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control device, and in particular stores store data, which is cache memory update data, in a store buffer, and then stores it using free time or the like. The present invention relates to an improvement in a cache memory control device configured to flush stored data in a buffer to a cache memory.

[Conventional technology]

Conventionally, in this type of cache memory control device, as shown in FIG. The set store address is stored in the store address buffer 60. Later, when the corresponding store data is prepared and transferred by the calculation unit, it is stored in the store data buffer 762. At this point, the store data is flushed to the main memory and the address arrays (AAO, AAI) 20, 21 and data array (DAO .

DAI) 40.41 is started by the control unit 50 to flush to the cache memory.

When flushing to the cache memory, since Canon's memory is usually composed of multiple levels (Figure 2 shows the case of 2 levels), it is important to check whether flushing to the cache memory is necessary, that is, for store operations. It is necessary to check whether the target address is registered in the address array 20.21 and at the same time to check in which level of the address array it is registered.

Therefore, when flushing is activated by the control unit 50, the store address is read from the store address buffer 60 and stored in the address register 10 through the selection circuit 16, and at the next timing, the cache memory's level 0 and level 1 addresses Arrays 20 and 21 are referenced at the same time, and comparators 30 and 31 check whether or not the store address is registered, and if it is detected that the store address is registered, a hit signal 301 or 302 is output.

The hit signals 301 and 302 are stored in the write permission register 14 for the data array of the cache memory via the control section 50. At the same time, store data buffer 62
The store data read from the store address buffer 60 is stored in the write register 13, and the data array address part of the store address read from the store address buffer 60 is stored in the data array address register 12 via the selection circuit 15. The write permission register 14 is at level 0. It consists of 2-bit write permission bits that store each level 1 hint signal, and if the target address of the store operation is not registered in any of the address arrays of the cache memory, both of the above write permission bits are The bit becomes "0", and the flushing write) is not executed. On the other hand, if the target address of the store operation is registered in any address array of the cache memory, the write permission bit corresponding to the registered level becomes "1", and the write register 13 is written to the data array of that level. The stored data will be flushed out. In this way, flushing to the cache memory is performed according to the given data array address, store data, and write permission bit.

[Problem that the invention attempts to solve]

The above-described conventional cache memory control device does not refer to the address arrays 20 and 21 when receiving a target address for a store operation, but refers to the data array 40 after the store data has been prepared in the store data buffer 62. .41, the address array 20.21 is referenced, so it is often necessary to set the store address once stored in the address buffer 60 in the address register IO again. However, the address register 10 is not a register that stores only store addresses, but also stores the load address during a load operation, so if a load operation is accepted, it may be necessary to wait for the execution of the load operation. There is a drawback that a user is forced to choose whether to wait for the storage data to be flushed out or to wait until the stored data is flushed out. Another drawback is that two machine cycles are required to read the address array and register the store data in the data array in order to flush out the store data.

The present invention solves these conventional problems, and its purpose is to store the store address in the address register 10 when flushing the store data to the cache memory.
The purpose is to eliminate the need to refer to the 7-dress array by resetting the 7-dress array.

[Means for solving problems]

In order to achieve the above object, the present invention provides a Canon memory control system comprising a cache memory that is composed of a plurality of levels and stores a copy of the main memory, and a store buffer that temporarily stores the target address and target data of a store operation. In the store processing method in the device, a hit helper sofa is provided which stores the result of detecting whether or not the target address of the store operation is registered in the cache memory for each level at the time of accepting the store operation. The content of the hit level buffer is referred to at the timing of registering target data from the store buffer to the cache memory to obtain the level of the cache memory to be registered.

[Effect]

When a store operation is accepted, whether or not the target address of the store operation set in the address register is registered in the cache memory is checked for each level of the cache memory, and the results are stored in the hit level buffer. When the store data is later flushed out to the cache memory, the level of the cache memory to be registered is obtained from the contents of the hit level buffer.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, and 11
10 is an operation register that stores an operation for the data array access stage, and 10 is an address register that stores an address for the above operation. Further, 12 is a data array address register in which a part of the address (data array address) of the above-mentioned operation required by the data arrays 40 and 41 is stored via the selection circuit 15. The operation information set in the operation register 11 is sent to the control section 50 and decoded, thereby controlling each section to execute the operation.

When a store operation is accepted in the operation register 11, the address arrays 20 and 21 are simultaneously accessed by the set address portion of the store address written in the address register 10. In this embodiment, the cache memory has two levels, and a level 0 address array 20 and a level 1 address array 21 are prepared. Similarly, there is a level 0 data array 40 and a level 1 data array 41. The comparator 30 checks the match between the key address read from the level 0 address array 20 and the key address part of the address register 10, and the comparator 31 checks the match between the key address read from the level 1 address array 21 and the address register. 10 is checked, and it is detected whether the store address of the address register 10 is registered in the cache memory corresponding to each level.

If registration is detected, a hit signal 301°3 is output from the comparator 30 or the comparator 31 depending on the level.
11 is output. These hint signals 301 and 311 are stored in the hit level buffer 61 at the same time as the store address of the address register 10 is stored in the store address buffer 60. When this is finished, in this stage, the store operation is made to wait until the store data is sent from the arithmetic unit, and during this time, load operations and the like are executed one after another.

After the corresponding store data is sent from the arithmetic unit and stored in the store data buffer 62, the flushing to the cache memory is restricted. Activated by I[1 section 50.

In this case, the low level information @ (each hit signal of level O and level I) 611 is read from the hit level buffer 61 and sent to the control section 50. The control unit 50 determines whether or not the cache memory will be used in the incoming operation in the next cycle, and if it can be used in the store operation, connects the human level information 611 to the connection 501.
The data is sent to the write permission register 14 via . At the same time, store data is sent to the write register 13 via connection 621,
Among the addresses stored in store address buffer 60, the data array address is sent to data array address register 12 via connection 60I1 selection circuit 15. Note that the selection circuit 15 is controlled by the control unit 50 so that the connection 601 is selected at a timing when store data can be flushed from the store buffer to the cache memory.

The write permission register 14 has a capacity of 2 bits, bit O corresponds to a level O write instruction, and pin 1 corresponds to a level 1 write instruction. If the corresponding address is not registered in any level of the reference result of the address array 20.21 at the time of receiving the store operation, both the hint signals 301 and 311 are turned off, so the value stored in the write permission register 14 is becomes “00”. Therefore, writing is not performed to either level 0 or level 1. Conversely, if there is a hit in the address array 20 of Bell O, the value stored in the write permission register 14 is "01".
Then, the store data is stored in the level 0 data array 40, and if there is a hit in the level 1 address array 21, the value of the write permission register 14 becomes "10" and the store data is stored in the level 1 data array 41.

Note that the store operation is completed by flushing to the cache memory, transferring the store address and store data to the main memory, and executing the store to the main memory. In flushing to main memory, the contents of hit level buffer 61 are ignored.

〔Effect of the invention〕

As explained above, the present invention refers to the address array and stores the hit information in the hit level buffer when receiving the target address of the store operation, so that store data prepared later is stored in the cache memory. At the time of flushing, the level of the data array to be registered can be known by referring to the human level buffer mentioned above.
It is no longer necessary to set the store address in the address register again and refer to the address array when the store data is flushed to the cache memory, as in the conventional case, and the frequency of interrupting the execution of subsequent operations can be reduced. Therefore, there is an effect that store operation performance can be improved. Furthermore, since there is no need to refer to the address array when flushing out stored data, there is an effect that the flushing can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional cache memory control device. In the figure, 10 is an address register, 11 is an operation register, 12 is a data array address register, 13 is a write register, 14 is a write permission register,
20 is a level O address array, 21 is a level 1 address array, 40 is a level 0 data array, 41 is a level 1 data array, 50 is a control section, 60 is a store address buffer, 61 is a hit level buffer, 62
is the store data buffer.

Claims (1)

[Claims] In a store processing method in a cache memory control device having a cache memory configured from a plurality of levels and storing a copy of the main memory, and a store buffer temporarily storing a target address and target data of a store operation. , a hit level buffer is provided to store the result of detecting whether or not the target address of the store operation is registered in the cache memory for each level at the time of receiving the store operation, and the target data of the store operation is stored in the store buffer. A store processing method in a cache memory control device, characterized in that the cache memory level to be registered is obtained by referring to the contents of the hit level buffer at the timing of registering in the cache memory.