JPH04232550A - Coincidence processing controller - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a memory request by preventing temporary interruption of the normal memory request processing at the time of coincidence processing between data contents of a main memory and a data buffer. CONSTITUTION:When coincidence between a coincidence processing address 109 and addresses in address arrays 5 and 12 is detected by a comparator 14 and the execution of coincidence processing is necessary, the coincidence processing address is stored in V bit address registers 16 and 17 corresponding to V bit buffers 6 and 13 indicating effective bits for address arrays 5 and 12. V bit buffers 6 and 13 are accessed by the address stored in address registers 16 and 17 to clear their contents, and the invalidating processing is performed. Since the address for invalidating processing and the address to read out address arrays and V bit buffers are separated from each other, it is unnecessary to suppress the request address and the coincidence processing address, and the access efficiency of address arrays is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matching processing control device in an information processing device, and more particularly to a matching processing control device for matching the contents of a data buffer that holds a partial copy of data in a main memory with the contents of the main memory. Regarding.

0002

2. Description of the Related Art As shown in FIG. 2, a conventional coincidence processing control device includes an address selector 1 which selects a part of a request address 101 and an address 111 of an address array B by a coincidence signal 118, and a request address 10.
1 and an address register 2 for the address array A that sets a selected address 102 which is the output of the address selector 1, and a RAM that is accessed by the address 103 which is a part of the output of this address register 2. (A) 5 and this address array 5
V bit 6 of a register file configuration that stores a V bit indicating whether the contents of the file are valid or invalid.

Further, upon receiving the match signal 118, the V bit data register 3 sets "0" and outputs the V bit write data 107 which is the write data of the V bit 6, and the V bit data register 3 sets "1" to output the V bit write data 107, which is the write data of the V bit 6. A V-bit write enable register 4 outputs a V-bit write enable 108 which is a write enable signal for
and a comparator 7 that uses the output 105 of address array 5 and the output valid signal (V bit) 106 of address array 5 to determine a match signal 117.

Further, an address selector 8 selects a part of the match processing address 109 and the address 111 of the address array (B) 12 using a match signal 118, and a selection address 110 which is the output of the address selector 8 and a part of the match processing address 109 are selected. Validity of the contents of the address array 12 of the address register 9 for the address array 12 to be set in part and the address array (B) 12 accessed by the address 111 which is part of the output of this address register 9; V bit 13 of a register file configuration that stores a V bit indicating invalidity.

Furthermore, upon receiving the coincidence signal 118, "
0” is set to write data of V bit 13.
V bit data register 10 outputs bit write data 115 and V bit write enable 116 is set to “1” and is a write enable signal for V bit 13.
a V bit write enable register 11 that outputs
Comparison data 112 and output 113 of address array 12
and address array 12 valid signal (V bit) 114
a comparator 14 that determines a match signal 118 using
and a request suppression circuit 15 that outputs an address array access suppression signal 119 that suppresses the match processing address 109.

Next, the operation will be explained. The request address 101 and the match processing address 109 are sent asynchronously, and normally the match signal 118
is "0", the address selector 1 selects the request address 101, and the address selector 8 selects the match processing address 109.

However, at a certain timing, if the output 113 of the address array 12 read by the address 111 matches the comparison data 112 and the valid signal 114 of the address array 12 is "1", the comparison In the device 14, the coincidence signal 118 is “1”.
” is output.

In this case, it is necessary to invalidate the contents of address array 12 indicated by address 111. This is the V bit 1 indicated at address 111.
The content of 3 may be set to "0".

[0009] Also, regarding the address array 5 which stores the same contents as the address array 12, the address 111
In order to invalidate the contents indicated by , it is necessary to set the contents of address 111 of V bit 6 to "0". The above operation is realized by the following method.

■Since “0” is written to V bits 6 and 13, the match signal 118 =
When the value becomes 1, the request suppression circuit 15 outputs the address array access suppression signal 119 as 1, and requests the request address 101 and the match processing address 1.
09 will be suppressed.

■ Since the match signal 118 = 1,
Address 111 is selected in address selectors 1 and 8.

■At the next timing, the selected address 102 is stored in the address register 2, the selected address 110 is stored in the address register 9, and the V bit data registers 3 and 10 are stored.
The inverted signal of the match signal 118 1 is set in the V bit write enable registers 4 and 11, and the match signal 118 1 is set in the V bit write enable registers 4 and 11, respectively.

[0013] ■ At the timing of ■ above, V bits 13 and 6
Address array valid signals 114 and 106 are both “0” because “0” is written to address 111 of
0”.

■The address array valid signal 1 is activated by the above ■.
14 becomes "0", the V-bit write enable register 11 and address selector 8 in the comparator 14 become "0", and the address array access inhibit signal 119 in the request inhibit circuit 15 also becomes "0".

That is, the inhibition of the request address 101 and the match processing address 109 is released, and the match signal 11 is also released in the address selectors 1 and 8.
8 = 0, request address 101
and match processing address 109 are selected, so at the next timing, 101 is stored in address register 2.
However, the match processing address 109 is stored in the address register 9.
are set respectively and return to normal operation.

In this conventional matching processing control device, matching processing and normal request processing must be suppressed when invalidating the information in the address array when the matching processing address matches the information in the address array. When match processing addresses successively match information in the address array, there is a problem that the access efficiency of the address array in normal requests deteriorates, resulting in a decrease in performance, and a problem that the processing capacity of the match processing decreases.

[0017]

OBJECTS OF THE INVENTION An object of the present invention is to provide a coincidence processing control device that can improve address array access efficiency and coincidence processing performance.

[0018]

According to the present invention, there is provided a request processing address array that stores request addresses for processing a memory request, the contents of a data buffer that holds a copy of a portion of data in a memory, and the contents of the memory. a match processing address array that stores addresses for match processing; a match processing address register that receives match processing addresses; a result of indexing the match processing address array based on the address contents of this address register; and the address of the address register. and a comparison means for comparing the content with the content, and when a match is detected by the comparison means, invalidating the content of the match processing address array corresponding to the matched address and changing the corresponding content of the request processing address array. a matching processing control device for an information processing device, the matching processing control device including a means for invalidating said address arrays for request processing and matching processing, said device being provided corresponding to said request processing address array and said matching processing address array, and determining whether each content of the corresponding address array is valid or invalid; first and second valid bit buffers that store valid bits shown in the table; and a valid bit buffer address register that stores the address contents of the match processing address register when a match is detected by the comparing means.
A first control means that controls access to the first valid bit buffer using the request address in normal times, and controls clearing of corresponding bits by accessing the first valid bit buffer according to the contents of the valid bit buffer address register during match processing. Then, access to the second valid bit buffer is controlled by the contents of the match processing address register in normal times, and during match processing, access is controlled by the contents of the valid bit buffer address register to control clearing of the corresponding bit. A matching processing control device is obtained, which is characterized in that it includes a second control means.

[0019]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. In the figure, only the parts that are different from the conventional example shown in FIG. 2 will be explained.

V-bit buffer address registers 16 and 17 that store write addresses during match processing corresponding to V-bit buffers 6 and 13, respectively, and a match suppression detection circuit 18 that suppresses matching detection of comparison circuits 7 and 14; 19 have been added.

V-bit buffer address register 16
and 17 write the upper bit 111 of the address register 9 in response to the coincidence detection timing 118 of the comparison circuit 14, and both outputs 120 and 122 become the respective write addresses of the V bit buffers 6 and 13.

The match suppression detection circuit 18 checks whether the address 103 of the address register 2 matches the address 120 of the V-bit buffer address register 16, and detects a match or outputs the output valid signal 106 of the address array 5.
When is "0" (indicating that the output of the address array 5 is invalid), the match inhibition signal 121 is output as "1".

The comparator 7 checks whether the comparison data 104 and the output 105 of the address array 5 match, and when they match and the match inhibition signal 121 is "0", the match signal 1 is output.
17 is output as "1".

The match suppression detection circuit 19 detects the address 111
and the address 122 of the V-bit buffer address register 17, and a match is detected or a match is inhibited when the output valid signal 114 of the address array 12 is “0” (the output 113 of the address array 12 is invalid). The signal 123 is output as "1".

The comparator 14 checks whether the comparison data 112 and the output 113 of the address array 12 match, and outputs a match signal 118 as "1" when they match and the match inhibition signal 123 is "0".

Next, the operation will be explained. The match processing address 109 and the request address 101 are sent asynchronously, and the request address 101 is accepted by the address register 1, which outputs the address 103 and reads out the address array 5 and the V bit 6. , the match suppression detection circuit 18, and the match signal 117 in the comparator 7 are determined.

The match processing address 109 is received in the address register 9, and this register 9 receives the address 111.
is output, the address array 12 and the V bit 13 are read out, and a match signal 118 in the match inhibition detection circuit 19 and comparator 14 is determined.

During the above operation, address array 12 which is the content of V bit 13 read by address 111
The output valid signal 114 of is "1", and the address 122 and address 111 are detected in the match suppression detection circuit 19.
If no match is detected, the match suppression signal 12
3 is set to "0" and sent to the comparator 14. At that time,
Output 113 of address array 12 in comparator 14
When a match between the data 112 and the comparison data 112 is detected, the match signal 118 becomes "1".

In this case, it is necessary to invalidate the contents of the portions indicated by address 111 in address arrays 5 and 12. To disable it, address array 5
The part indicated by the address 111 of V bit 6 where the valid signal of the information of the address array 12 is stored and the V bit 13 where the valid signal of the information of the address array 12 is stored is set to "0".
Just do it.

As for its operation, the coincidence signal 118 is “
1", the V bit address registers 16 and 17 set the address 111 at the next timing, and the V bit data registers 3 and 10 set the match signal 11.
8, that is, set to "0", and the V bit write enable registers 4 and 11 output the match signal 118.
, that is, set "1".

Therefore, at the next timing, V bit 6
Regarding, address 120 is a write address, V bit write data 107 is write data, and V bit write enable 108 is a write permission signal. Also, regarding V bit 13, V bit address 122
is the write address, V bit write data 115 is the write data, V bit write enable 116 is the write signal, and “0” is stored in the part where the content with the match signal 118 in V bit 6 and V bit 13 set to “1” is stored. ”, matching processing address 109
The contents of address arrays 5 and 12, which are the same as , become invalid.

Even at this timing, the request address 101 and the match processing address 109 are being sent, but since the write address and read address are different for V bits 6 and 13, processing is performed as usual. . Furthermore, when the write address and the read address match, the match suppression detection circuits 18 and 19 set the match suppression signals 117 and 118 to "1", so that the comparators 7 and 14 respectively set the coincidence suppression signals 117 and 118 to "1". Since the match signals 117 and 118 become "0", it is a wasteful operation (for the match signal 118, writing "0" to V bits 6 and 13 to the same address,
Regarding item 7, it is possible to suppress reading processing of data that will become invalid at the next timing.

[0034]

As explained above, according to the matching processing control device of the present invention, a match between information in an address array and a sent matching processing address is detected, and the matching information in the address array is invalidated. In this case, the request address sent to access the address array and the matching processing address are not suppressed, so the access efficiency of the address array does not decrease, so the request and matching processing address are not suppressed. This has the effect of preventing a decline in processing capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a block diagram of a conventional matching processing control device.

[Explanation of symbols]

2 Request address register 3, 10 V bit data register 4, 11 V bit write enable register 5
Request processing address array 6, 13 V bit buffer 7, 14 Comparison circuit 9 Match processing address register 16, 17 V bit address register 18, 19
Match suppression detection circuit

Claims (1)

[Claims] 1. A request processing address array that stores request addresses for request processing for memory requests, and an address for matching the contents of a data buffer that holds a partial copy of data in memory with the contents of the memory. A match processing address array that stores a match processing address, a match processing address register that receives a match processing address, and a comparison that compares the result of indexing the match processing address array using the address contents of this address register and the address contents of the address register. means and
Information processing comprising means for invalidating the contents of the matching address array corresponding to the matched address and invalidating the corresponding contents of the request processing address array when a match is detected by the comparing means. A matching processing control device of the device, which is provided corresponding to the request processing address array and matching processing address array, respectively, and stores a valid bit indicating whether each content of the corresponding address array is valid or invalid. A second valid bit buffer, an address register for a valid bit buffer that stores the address contents of the match processing address register when a match is detected by the comparing means, and a valid bit buffer address register for storing the address contents of the match processing address register when a match is detected by the comparison means, and a a first control means that controls access based on the request address and controls clearing of a corresponding bit by accessing based on the content of the valid bit buffer address register during match processing; and for the second valid bit buffer; The second control means controls access according to the contents of the match processing address register during normal times, and performs clearing control of corresponding bits by accessing according to the contents of the valid bit buffer address register during match processing. A matching processing control device.