JPH052532A - Cache memory - Google Patents

Abstract

PURPOSE:To prevent a processor from being reduced at its performance due to a cache miss by utilizing an idle time of a processor for restoring data invalidated by cache coincidence processing. CONSTITUTION:The cache memory is provided with a data array 30 for storing the copy of data stored in a main memory, a copy address array 20 having an address array for storing address data and a copy of the contents of the address array, a detecting circuit 40 for comparing address data indicating a main storage address written by a cache coincidence processing request generated at the time of writing data in the main storage with the contents of the copied address array and judging coincidence between both the data, and an address buffer 50 for storing address data indicating the main storage address when the circuit 40 detects coincidence. During the idle time of the processor, the main storage data of the address indicated by the address data stored in the buffer 50 are written in the data array stored at the time of generating/ cache coincidence processing request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to the structure of a cache memory used in an information processing device.

[0002]

2. Description of the Related Art A conventional cache memory is a data array for storing a copy of data in a main memory, an address array for associating the contents of the data array with the contents of the main memory, and a copy having a copy of the contents of the address array. It consists of an address array.

The address array is indexed when a main memory read or write request is issued from the processor and is used for determining a cache hit or cache miss. The copy address array is dedicated to detecting the mismatch between the contents of the cache memory and the main memory, and is used as the main memory write address when a main memory write request from another processor or an input / output (I / O) device occurs on the memory bus. The copy address array is indexed to see if the cache memory has the data at that address.

An address array index in a main memory read or write request from a processor, and a cache memory in a cache match processing request required when a main memory is written from another processor or an I / O device. The index of the copy address array for detecting the mismatch with the contents of the main memory is usually performed asynchronously.

When a main memory read request from the processor is judged to be a cache miss, the main memory read data is registered in the cache memory, and this read data is written to the data array, and the address array and copy are made. The address used to read the main memory is written to the address array at the same time. When a cache hit is determined in the main memory write request from the processor, the write data to the main memory is written to the data array in order to register the write data to the main memory in the cache memory.

Further, if a cache hit is judged in the index of the copy address array in the cache match processing request, it indicates that a mismatch has occurred between the contents of the main memory and the contents of the cache memory. And the process of invalidating the corresponding address of the copy address array (resetting the valid bit) are performed at the same time.

Thereafter, when the processor comes to read this invalidated address, the data is read from the main memory and registered in the cache memory.

[0008]

In the above-mentioned conventional cache memory, when the address of the cache matching processing request hits, the data corresponding to the address is invalidated in the registration unit of the cache memory. A cache miss also occurs for a memory read request at this address, resulting in a decrease in processor performance.

[0009]

SUMMARY OF THE INVENTION A cache memory according to the present invention comprises a data array for storing a copy of data in a main memory, and an address for storing address data that associates the contents of the data array with the contents of the main memory. An array,
A copy address array having a copy of the contents of the address array; address data indicating an address of the main memory written by a cache match processing request that occurs when data is written to the main memory; The idle time of the processor is used, provided with a detection circuit that compares the contents and determines a match, and an address buffer that stores address data indicating the written address of the main memory when a match is detected by the detection circuit. Then, the data in the main memory at the address indicated by the address data stored in the address buffer is written to the data array stored at the time of the previous cache matching processing request.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cache memory of the present invention.

As shown in FIG. 1, the cache memory of this embodiment comprises an address register 10, a copy address array 20, a data array 30, a detection circuit 40 and an address buffer 50. Address register 10
Holds the cache coincidence address, and the copy address array 20 manages the correspondence with the address register 10 by storing a part of the memory access address indicated by the signal line 103. The data array 30 is indexed at the same time when the address value of the copy address array 20 is determined by the address register 10, and the signal line 3
The read data is sent out on 02. When registering data in the cache memory, the signal line 301 is used to write the data read from the main memory. The detection circuit 40 compares the content stored in the copy address array 20 with the content of the address register 10 and outputs a logical value "1" on the signal line 401 if the two match. This time is called a cache hit. Address buffer 50
Stores the contents of the address register 10 in the case of a cache hit by a cache match processing request on the signal line 501, and when the processor is not busy, that is, when the logical value on the signal line 502 is “0”, the memory is stored on the signal line 503. Output the read address.

Next, the operation relating to the present invention will be described. First, when the cache match processing request on the signal line 501 is the logical value “1”, the cache match processing address on the signal line 101 is held in the address register 10 and the signal line 10
4, the copy address array 20 and the signal line 105 simultaneously index the contents of the data array 30, and the detection circuit 40 detects the coincidence of the addresses. If the output of the detection circuit 40 is logic "0", a cache miss occurs and the series of operations ends here. Next, when the output of the detection circuit 40 is logic "1", a cache hit occurs and the contents of the copy address array 20 indicated by the signal line 104 are invalidated. The data array 30 corresponding to the contents of the copy address array 20 which is invalidated at this time
The contents of are also invalid. The address value invalidated by the signal line 102 is written in the address buffer 50. The address buffer 50 stores the content stored in the address buffer 50 as a memory read address on the signal line 503 when the processor busy signal on the signal line 502 has a logical value of “0” (when there is a vacancy in the processing of the processor). Output. The data corresponding to the address is read from the main memory by the output memory read address, and the content of the data array 30 indicated by the signal line 105 is rewritten using the signal line 301.

[0014]

As described above, in the cache memory of the present invention, the data invalidated by the cache matching process is restored by utilizing the idle time of the processor to prevent the processor performance from being deteriorated due to the cache miss. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cache memory of the present invention.

[Explanation of symbols]

 10 address register 20 copy address array 30 data array 40 detection circuit 50 address buffer

Claims (1)

Claim: What is claimed is: 1. A data array for storing a copy of data in a main memory, an address array for storing address data for associating the contents of the data array with the contents of the main memory, and the address. A copy address array having a copy of the contents of the array, address data indicating the address of the main memory written by a cache matching processing request that occurs when data is written to the main memory, and the contents of the copy address array. A detection circuit for comparing and determining a match; and an address buffer for storing address data indicating the written address of the main memory when the detection circuit detects a match The data in the main memory at the address indicated by the address data stored in the address buffer Cache memory and writes the data array stored at cache matching processing request.