JPS62152160A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce the size of picture element, increase the rate of aperture and reduce noise of fixed pattern of picture element by forming all the input/ output signal lines of unit bit and picture element regions on the self-line basis with the insulating film in the separation groove. CONSTITUTION:An input signal line 10 of picture element of a solid state image pickup device is extended in the row direction, it is then connected to a capacitance element C as an input part of unit bit u and the specified end part is connected to a vertical scanning circuit 15. A clock signal is input to the signal line 10 from a circuit 15. Moreover, a data signal line 11 is extended in the column direction, it is then connected to an amplifier AM as an output part of the bit u and a horizontal scanning circuit 14 is connected to the specified end part through the selective MISFETQ1, Q2. Only one of the FETQ1, Q2... is selected and is set conductive by this circuit 14, an optical output signal read to the data line 11 connecting such FETQ is input to a preamplifier 16 and it is then output from the amplifier 16. The size of picture element is reduced, rate of aperture is increased and noise of fixed pattern is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device having an amplification function for each pixel.

[Conventional technology]

9 to 11 are diagrams for explaining one pixel portion of a photodiode and a readout switch in a conventional solid-state imaging device having an amplification function, and FIG. 9 shows a schematic configuration of this solid-state imaging device. The plan view shown in FIG. 10 is as follows.
9 is a sectional view taken along the line A--A in FIG. 9, and FIG. 11 is an equivalent circuit diagram of FIG.

9 to 11, reference numeral 1 denotes an i-type semiconductor substrate, on which an n-type buried layer 2 is provided, and an n-type epitaxial layer M! on the n-type buried layer 2. I3 is provided. Note that in FIG. 9, the P- type semiconductor substrate 1 and the N4 type buried layer 2 are not shown in order to make the pixel configuration easier to see. A P type semiconductor region 6o is provided on the main surface of the p type epitaxial layer 3, and n° type semiconductor regions 901 and 902 are provided on the main surface of the p type semiconductor region 60, spaced apart from each other. The n''' type buried layer 2 has a power supply potential V c c
, for example, is set to 5V, and serves as a collector power supply for a bipolar transistor Q0 having the p° type semiconductor region 901 as an emitter, the p′ type semiconductor region 60 as a base, and the n− type epitaxial layer 3 as a collector. Further, a photodiode D is formed by the P44 type semiconductor region 60 and the n-type epitaxial layer 3. constitutes an n4 type semiconductor region 902 and P'''
The type semiconductor region 3 constitutes a capacitive element C8.

These capacitive element Go, transistor Q, and photodiode Do constitute one pixel of the solid-state imaging device. Further, in the n0 type semiconductor region 901, which is the emitter of the transistor Qo, there is a load resistance RL as shown in FIG.
is connected.

This type of solid-state imaging device is known, for example, from Japanese Patent Application No. 58-2397.
It is described in the specification of No. 67.

[Problem that the invention seeks to solve]

The n-type semiconductor regions 901 and 902 are formed by implanting n-type impurities such as phosphorus (P) and arsenic (As) into the p-type semiconductor by, for example, ion implantation using a resist mask after forming the p-type semiconductor region 60. It is introduced and formed on the surface of the region 60. Therefore, in the conventional solid-state imaging device as described above, the p' type semiconductor region 60 and the 1' semiconductor region 901.9
Since it is necessary to provide a margin for mask alignment during 02, there is a problem in that it is difficult to reduce the pixel size. Furthermore, there is also the problem that the light receiving size is restricted by wiring, etc., and the aperture ratio is kept small.

The present invention has been made to solve the above problems.

An object of the present invention is to reduce the pixel size of a solid-state imaging device,
Another object of the present invention is to provide a technology for increasing the aperture ratio, that is, a high-resolution solid-state imaging device that is highly integrated and has a higher number of pixels than the conventional one.

Another object of the present invention is to provide a technique for improving the image quality of a solid-state imaging device by reducing fixed pattern noise caused by variations in current amplification factors hFE of transistors of each pixel.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of one typical invention disclosed in this application is as follows.

That is, a plurality of unit bit regions are provided in a matrix on a semiconductor substrate of a first conductivity type, and a dividing groove is provided between each unit bit region on the semiconductor substrate to separate the unit bit regions, A first semiconductor region of a second conductivity type is provided at the upper end of each unit bit region to constitute a photodiode, and a second semiconductor region of the first conductivity type is provided at the first side surface of the upper end of the unit bit region. The second semiconductor region and the first semiconductor region constitute a capacitive element, and the jl
A third electrode of the first conductivity type is formed on the second side surface of the upper end of the t-th bit region.
A semiconductor region is provided to configure a 1-transistor, and a first wiring extending in one row direction is connected to one of the grooves between each unit bit region so that a plurality of potential bit regions constitute one pixel. A second interconnect extending in the column direction is provided in every groove of a predetermined number of grooves and connected to the capacitive element, and a second interconnect extending in the column direction is provided on every groove of a predetermined number of grooves between unit bit regions and connected to the transistor. The image quality is improved by reducing the pixel size, increasing the aperture ratio, and reducing fixed pattern noise.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, the circuit configuration of the pixel section of the solid-state imaging device of this embodiment will be explained using FIG. 4.

FIG. 4 is an equivalent circuit diagram of the pixel section of the solid-state imaging device of this embodiment.

In FIG. 4, reference numeral 10 denotes an input signal line, which extends in the row direction and is connected to a capacitive element C which is an input part of a unit bit U, which will be described later, and has a predetermined end connected to a vertical scanning circuit 15. It is connected. The vertical scanning circuit 15 is for applying a clock signal to each of the plurality of input signal lines IO. Reference numeral 11 denotes a data line, which extends in the column direction and is connected to the amplifier A, which is the output section of the unit pin +-U, and a predetermined end thereof is connected to the selection M I S FE.
It is connected to the horizontal scanning circuit 14 through TQl and Q2. The horizontal scanning circuit 14 includes a plurality of switches MT5FE
A predetermined switch MISF from TQ+, Q2...
ETQ is selected and made conductive, and the selected switch M
This is for inputting the optical output signal read out to the data line 11 to which the IS FETQ is connected to the preamplifier 16. RL is a load resistance, and this load resistance R
The potential difference between both ends of L is read out by the preamplifier 16 as an optical output signal of the data line 11.

W indicates one pixel, and the pixel portion of the solid-state imaging device of this embodiment is configured by repeatedly arranging this pixel W in the row and column directions. One pixel W consists of four unit bits U, and one unit bit I-
U consists of a photodiode D, a capacitive element C, and an amplifier A composed of one bipolar transistor. In one unit bit U, one electrode of the capacitive element C is connected to the input signal line 10, and the other '? The ri pole is connected to the photodiode D and the input side of the amplifier A. The output side of amplifier A is connected to data line 11. That is, one unit bit U is connected to input signal line 1
When a clock signal of 0 is input to the input side of the amplifier 80 through the capacitive element C, the photocharge accumulated in the photodiode D is amplified by the amplifier A, and is transferred to the data line 1.
1.

As mentioned above, by configuring one pixel W by four unit bits U, the optical output signals of these four unit bits U are mixed and averaged and output to the data line 11, so that each unit Of the bipolar transistors that make up the amplifier A of bit U? ! The current amplification factor hPE
It is possible to reduce fixed pattern noise in optical output reliability due to variations in optical output. This makes it possible to improve the image quality of the solid-state imaging device.

Next, the specific structure of the pixel W will be explained using FIGS. 1 to 3.

FIG. 1 is a perspective view of the pixel section of the solid-state imaging device of this embodiment. FIG. 2 is a plan view of the pixel section, and FIG. 3 is a cross-sectional view of the pixel section taken along the Δ-A cutting line shown in FIG. It is. Note that in order to make it easier to see the configuration of the pixel section, FIGS.
Insulating films other than the insulating film 5 in the isolation trench 4 are not shown.

The capacitive element C of the unit bit U shown in FIG.

A P° type semiconductor region 6 formed on the main surface of each n-type epitaxial layer 3 having a square plane and shaped like a rectangular prism, and the square-shaped n-type epitaxial region F! It consists of an n-type semiconductor region 8 formed on the side surface of the upper end of J3 on the side to which an input signal line 10 (to be described later) is connected. The photodiode D of the unit Pino I-U is
The front sheet is composed of an n-type epitaxial layer 3 and the p-type conductor region 6. The bipolar transistor constituting the amplifier AM of unit bit U has an n'-type semiconductor region 7 serving as an emitter formed on the side surface of the upper end of the n-type epitaxial layer 3 on the side to which an output terminal 9 (to be described later) is connected. , a p-type semiconductor region 6 serving as a base, and an n-type epitaxial layer 3 serving as a collector. rl.

The type semiconductor region 8 is provided apart from the rl' type semiconductor region 7. The collector is n-type epitaxial P! J
3 is connected to the upper power supply Vcc through the n° type buried layer 2.

For example, 5V is applied. As shown in FIG. 3, the cross-sectional shape of the p-type semiconductor region 6 is such that its side portions penetrate deeply into the n-type epitaxial layer 3, and its central portion is shallow. The n-type epitaxial layer 3 in which the P'' type semiconductor region 6 and the n0 type semiconductor region 7.8 are formed and has a rectangular prism-like shape will hereinafter be referred to as a unit bit region. trL bit area As shown in FIGS. 1 and 2, M unit bit areas are arranged in matrix on the H surface of the n-type buried layer 2, and each 1 to the region is f1° from the top surface of the epitaxial layer 3.
Embedding the mold!・It is separated by 1 minute by the deep branch groove 4 that reaches up to 1 j2. That is, the space between the areas of each unit pinot 1 is made up of nine M grooves 4 extending in the row direction and equinox grooves 4 extending in the column direction. In addition, Figures 1 and 3
The lead line of the separation 17ζ4 in the figure indicates the wall surface of the separation groove 4.

In this way, by separating the unit bit regions by the deep separation groove 4, the photocharge generated from the photodiode D does not flow into other photodiodes D, so that a high-quality image without crosstalk can be obtained. be able to.

In the isolation trench 4, an insulating film 5 made of a silicon oxide film formed by CVD, for example, is formed so that the side surface of the upper end of the n-type epitaxial layer 3 shaped like a unit bit region, that is, a square prism, is exposed. is embedded. Therefore, when one pixel section is viewed from above, as shown in FIG. 2, the insulating film 5 is provided between the unit bit regions like a net.

Each pixel W shown in FIG. 4 is composed of a set of four unit bit regions, and the predetermined four unit bit regions constituting the pixel are n-type epitaxial F! An output terminal 9 made of an n-type polycrystalline silicon layer is provided on the insulation film 5 between J3 and connected to the n-type semiconductor region 7 which is the emitter of the transistor.

In other words, one pixel is composed of four unit bit areas that are in contact with the output terminal 9. The output terminal 9 is for connecting the n-type semiconductor region 7, which is the emitter of the transistor, to the data line 11, and is also for connecting an n-type impurity such as phosphorus or arsenic to form the n-type semiconductor region 7. Used as a diffusion source. There is no level difference between the upper surface of the output terminal 9 and the upper surface of the unit bit region, that is, the ri-type epitaxial WJ3, and the surface is flat. Since the output terminal 9 is provided in the groove 4 between the four unit bit areas, its planar shape is cross-shaped, and the output terminal 9 has a cross-shaped planar shape. The layers are separated between adjacent output terminals 9. Therefore, the insulating film 5 in the one isolation trench 4 is exposed between the output terminals 9. Since it is formed on the side surface of the type epitaxial layer 3 to which the cross-shaped output terminal 9 is connected, the planar shape of the n° type semiconductor region 7 is L-shaped.

The input signal line 10 is made of, for example, an n-type polycrystalline silicon layer and is provided on the upper surface of the insulating film 5 in every other isolation trench 4 among the isolation trenches 4 extending in one row direction. In addition, the n-type semiconductor region 8 which is one electrode of the capacitive element C
It is connected to the side of the The input signal line 10 is the first
As shown in the figure and FIG. 2, the input signal aio of the epitaxial layer 3 is connected because it slightly protrudes toward the isolation trench 4 which extends in the row direction and also extends in the column direction. The planar shape of the n-type semiconductor region fIi8 formed on the side surface is shaped like a katakana square. Input signal line 1
0 protrudes a little in the column direction as described above, but is separated from the output terminal 9.

Therefore, the insulating film 5 is exposed between the input signal line 11 and the output terminal 9. Further, there is no step between the surface of the human input signal line 10 and the upper surface of the epitaxial layer 3, and the surface is flat.

As mentioned above, there is no level difference between the output terminal 9 and the upper surface of the Lj cotton wire 10 and the upper surface of the unit bit area.
Since the unit bit area, especially the upper surface of the photodiode, is not blocked by the output terminal 9 and the input signal line 10, the aperture ratio is increased.

Data 111 is made of an aluminum layer, and is provided extending in the column direction over every other separation groove 4 among the separation grooves 4 extending in the column direction, and is outputted through the connection hole 12. It is connected to the top surface of terminal 9. Therefore, the data line 11 is connected via the output terminal 9 to the n1 type semiconductor region 7 which is the emitter of the transistor. data line 1
1 and input signal line 10. Between the n' type semiconductor region 8 and the P' type semiconductor region 6, for example, phosphosilicate glass (PS) is used.
G) consists of absolute! It is insulated by the a film 13.

Next, a method for manufacturing the pixel portion of the solid-state imaging device of this embodiment will be explained using FIGS. 5 to 8.

5 to 8 are cross-sectional views of the same portion of the pixel portion as shown in FIG. 3 during the manufacturing process.

In the method of manufacturing the pixel portion of this embodiment, an n-type buried layer 2 is formed on a P-type semiconductor substrate l by a well-known technique, and an i-type epitaxial layer 3 is further formed thereon.

Next, the entire top surface of the n-type epitaxial layer 3 is oxidized,
A silicon oxide film 17, which will serve as an etching mask when forming the isolation trench 4 shown in FIG. 5, is formed on all two surfaces of the n-type epitaxial layer 3. Next, a resist film 18 is applied to the entire surface of the silicon oxide film 17, and this resist film 18 is used as an n-type epitaxial layer 3 in which the isolation trench 4 is formed.
pattern into a predetermined pattern by removing the upper part of the Next, the silicon oxide film 17 exposed from the resist film 18 is removed by etching.
F! Silicon dioxide v417 is patterned into a pattern for forming isolation grooves 4. Although the resist film 18 is shown in FIG. 5, the resist film 18 is removed after patterning the silicon oxide film 17. Next, the exposed portion of the i-type epitaxial layer 3 from the silicon oxide film 17 is vertically removed by anisotropic etching (for example, reactive ion etching) to form a deep layer trench that reaches the n-type buried layer 2. form 4.

After forming the isolation trench 4, the silicon oxide film 17 is removed.

Next, as shown in FIG. 6, an insulating film 5 is formed using, for example, a silicon oxide film formed by LPGVD so as to fill the inside of the trench 4. Then, as shown in FIG. At this time, the insulating film 5 is also formed on the upper surface of the n-type epitaxial layer 3. In other words, by forming the insulating film 5 sufficiently thickly on the n-type epitaxial layer Wj3, the inside of the layer separation trench 4 is filled with the insulating film 5. Next, as shown in FIG. 7, the insulating film 5 thickly formed on the n-type epitaxial layer 3 is gradually removed from its upper surface by reactive ion etching for 1 min.
E'j:' The insulating film 5 is left only inside 4.

At this time.

The insulating film 5 at the upper end of the isolation trench 4 is also removed.

The anisotropic etching etches the unnecessary insulating film 5 on the A-shaped epitaxial layer 3.

Next, a P-type impurity such as boron (B) is introduced into the upper end of the n-type epitaxial layer 3 by thermal diffusion to form a P-type semiconductor region 6. In this impurity introduction step,
Since the side surface of the upper end of the n-type epitaxial layer 3 is exposed, the n-type impurity is also introduced from the exposed side surface. Therefore, the P9 type half region 6 is formed deeper in the i-type epitaxial layer 3 at the peripheral portion than at the center.

Next, as shown in FIG. 8, a two-layer n-type polycrystalline silicon layer 19 for forming the output terminal 9 and input signal line 10 shown in FIGS. It is formed on the semiconductor region 6 and on the insulating film 5 in the isolation trench 4.

The polycrystalline silicon layer 19 is formed to have a sufficient thickness so as to fill the step between the upper surface of the P'' type semiconductor region 6 and the upper surface of the insulating film 5.

After this step, polycrystalline silicon layer 19 is etched from its upper surface by reactive ion etching to expose the upper surface of p'-type semiconductor region 6.

This etching removes the polycrystalline silicon layer 19.

It remains only on the insulating film 5 within the one isolation trench 4 so that there is no step difference between its upper surface and the p° type semiconductor region 6.

Next, the front 17 is etched using the resist 1-film.
! The polycrystalline silicon layer 19 is patterned into the pattern of the output terminal 9 and input signal line 10 shown in FIG. 1 and the second diagram. By this patterning, the output terminal 9 and the input line A 10 are completed.

Next, annealing is performed to eliminate n-type impurities contained in the output terminal 9 and the input signal line 10 made of the polycrystalline silicon layer.
For example, phosphorus or arsenic is introduced into the side surface of the p-type conductor region 6 where the output terminal 9 and the input silkworm 0 wire 10 are connected. Through this impurity introduction step, the n° type semiconductor region 8 which becomes the emitter of the transistor and the capacitance 'J? The rl' type semiconductor region 7 for forming the J child is completed. Next, for example, by CVD, rinsiligu 1~glass (PSG
) is formed on the entire surface of the semiconductor substrate 1. next.

A portion of the insulation 13 above the center of the output terminal 9 is selectively removed by etching to form a connection hole 12. Next, for example, by sputtering, the aluminum 3 is cut off?
! 1EJ l 3 is formed on the entire upper surface of this aluminum F! The data line 11 is patterned by dry etching using a mask made of a resist film, for example.
form.

As described above, for the insulating film 5 in the one-minute layer groove 4.

The essential parts of the imaging area, such as the P'-type semiconductor region 6, the n'-type semiconductor region 7.8, the output terminal 9, and the input signal line 10 constituting the unit bit, are all formed with self-alignment lines. Since it is not necessary to provide a mask alignment margin between the g film 5, the unit bit area, the output terminal 9, and the input signal line lO, the unit bit area, the output terminal 9. The input signal line 10 can be miniaturized. That is, it becomes possible to provide a high-resolution solid-state image sensor that is highly integrated and has a larger number of pixels than the conventional one.

Hereinafter, the present invention has been specifically explained based on examples. However, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Not even.

For example, in the embodiment described above, the output terminal 9 and the input signal terminal 10
Although the output terminal 9 and the input signal line 10 are formed of the polycrystalline silicon layer 19, the output terminal 9 and the input signal line 10 may be formed of a high melting point metal such as Mo, W, Ti, Ta, etc. or a silicide store of the high melting point metal.

Further, in the above embodiment, one pixel was configured by four unit bits, but the unit bit is an integer multiple of 2.
It is also possible to configure one pixel.

For example, when one pixel is composed of six Qt-order bit areas, the output terminal 9 is input so that the output terminal 9 shown in FIGS. 1 and 2 is connected to the six Qt-order bit areas. The signal a10 is made longer in the direction in which it extends. In this case, the data line 11 is extended over every second groove 4 of the grooves 4 in each column direction. The input g-cotton line 10 extends over every other 9-line i1'i'4, as in the previous embodiment.

〔effect〕

As explained below, according to the present invention, the following effects can be obtained.

(1) 9 chicks) 1]! Unit bit area for each expulsion within.

By forming all the important parts of one pixel area, such as the output terminal of the 1p-th bit and the input believe line, with self-aligned lines, there is no need for a mask alignment margin between them, so the unit pin 1-area, output It is possible to miniaturize the terminals and input wires. In other words, a high-resolution solid-state image sensor with high integration and an increased number of pixels than the conventional one is provided.

(2) By configuring one pixel with four unit bits, the output of one pixel becomes a mixture of the outputs of four unit bits and is averaged, so variations in the current amplification factor hp5 of the transistor of unit bits The fixed pattern noise caused by this can be reduced. From this, it is possible to improve the image quality of the solid-state imaging device.

(3) Since the space between each unit bit area is 9 times deep by 9 times, the photoelectric charge of 1 to 1 is not transferred to other unit bit areas, so
Image quality can be improved by preventing crosstalk.

(4) Since the output terminal and input signal line of the unit bit are formed flush with the upper surface of the unit bit area, the m-th bit area is not blocked from light by the output terminal and input signal line, so the unit bit area The aperture ratio can be increased.

In addition, scale-down measurement can be directly applied to the device structure of the present invention, so if the width of the pitch separation groove (1 to 2 μm in current technology) is reduced in the future, the resolution or aperture ratio will be further improved. be able to.

[Brief explanation of drawings]

1 is a perspective view of a pixel section of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a plan view of the pixel section, and FIG. 3 is a pixel section taken along the line A-A in FIG. FIG. 4 is an equivalent circuit diagram of the pixel portion, and FIGS. 5 to 8 are cross-sectional views of the pixel portion in the manufacturing process. FIG. 9 to FIG. 11 are diagrams for explaining problems in the pixel section of a conventional solid-state imaging device. In the figure, 1: semiconductor substrate, 2: -r1° type buried layer,
3... N-type epitaxial layer, 4... Separation trench, 5
, 13... Insulating film, 6... p' type semiconductor region, 7...
... n4 type semiconductor region, 8... n0 type semiconductor region, 9
...Output terminal of unit pitch 1-, 10...Rokukai a'';
f line, 11...data line, 12, connection hole 1, 14...
Horizontal scanning circuit, 15... Vertical scanning circuit, 16... Preamplifier, W... Pixel, U... Unit bit, C... Capacitive element, AM... Amplifier, D... Fo1-diode.

Claims (1)

[Claims] (1) A plurality of unit bit regions are provided in a matrix on a semiconductor substrate of a first conductivity type, and a separation groove is provided between each unit bit region on the semiconductor substrate to isolate the unit bit regions, A first semiconductor region of a second conductivity type is provided at the upper end of each unit bit region to constitute a photodiode, and a second semiconductor region of the first conductivity type is provided at the first side surface of the upper end of the unit bit region. a capacitive element is formed by the second semiconductor region and the first semiconductor region; a third semiconductor region of the first conductivity type is provided on the second side surface of the upper end of the unit bit region to form a transistor; A first wiring extending in the row direction is provided in every other groove among the grooves between the unit bit areas and connected to the capacitive element so that one pixel is configured in the unit bit area. . A solid-state imaging device, wherein second wirings extending in the column direction are provided on grooves every a predetermined number of grooves among the grooves between unit bit regions and are connected to the transistors.