JPS6233454A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide a solid-state image pickup device having a reduced pixel size and an increased opening factor, by taking out photo current generated from a photo diode formed by a semiconductor substrate with a first conductive type and a diffusion region with a second conductive type, from a wiring conductive member. CONSTITUTION:Since a polycrystalline silicon layer 5 to be used for wiring is formed on an element separating insulating film 3 in a trench 4, there does not exist height difference between the upper face of the epitaxial layer 2 and the upper face of the polycrystalline silicon layer 7, defining a planar surface. Moreover, since the trench 4 for separating between bits is deep so that it can reach the N<+> buried layer 1 passing through the epitaxial layer 2, the photo charges generated at each photodiode Dh can not flow into another bit. That is, the photo charges generated at each bit can be taken out as the photo charges within the bit, so that cross talk between bits can be eliminated to improve reliability of the solid-state image pickup device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device having an amplification function for each pixel.

[Background technology]

13 to 16 are diagrams for explaining one pixel portion of a photodiode and a readout switch in a conventional solid-state imaging device having an amplification function, and FIG. 13 shows a schematic configuration of this solid-state imaging device. 14 is a cross-sectional view taken along line A-A in FIG. 13, FIG. 15 is an equivalent circuit diagram of FIG. 13, and FIG. 16 is an operation of the solid-state imaging device shown in FIG. 13. FIG. 2 is a waveform diagram for explaining.

In FIGS. 13 to 16, 1 is an N+ buried layer, 2 is an N- epitaxial layer, 60 is a P+ diffusion layer,
901 and 902 are N+ diffusion layers. 1 is set to the power supply voltage, and becomes the collector power supply of the transistor QO, which has the P+ diffusion layer 901 as the emitter, the P+ diffusion layer 60 as the base, and the N- epitaxial layer 2 as the collector. The space between the base 60 and collector 2 of the transistor Qo also serves as a photodiode Do. 6. A junction capacitance CO is formed between the base 60 and the N+ diffusion M902. Also, transistor Q.

A load resistor RL is connected to the emitter (N+ diffusion layer) 901 as shown in FIG. This type of solid-state imaging device is described in, for example, Japanese Patent Application No. 58-239767.6 The operation of the solid-state imaging device will be described in conjunction with FIGS. 13 to 15 with reference to FIG. 16.

In FIG. 16, Wl is an address pulse from a shift register applied to N+ diffusion 902, the amplitude of which is set from the GND level to voltage V, .

When reading, the voltage v1. 1 and is set to GND level while photocurrent is being accumulated. W2 indicates the voltage at the base 60 of the transistor Qo.

W3 is the waveform of the emitter 901 of the transistor Qo and indicates the optical output voltage. First, address pulse W1
is set to V8 and reading is completed, the emitter 901 of the transistor QO is at the GND level,
The base 60 is then set to the diffusion potential V d p. Thereafter, when the address pulse W□ falls to the GND level, the voltage W2 drops by the voltage ■6 from the voltage VdP due to the coupling by the capacitor Co. This voltage drop v8 is determined by the ratio of the capacitance added to the base 60 of the transistor QO and the capacitance CO. Photodiode capacitance is Cph
, and other parasitic capacitances are C1, the voltage v8 is expressed as 1 equation (
% Formula % After this, the base potential gradually rises from Vdp-vg due to photocurrent, and the amount of photocharge generated during the accumulation time is Q.
ph, the increased voltage Vph can be expressed by the following equation (2).

Vph=Qph/ (Cph+Co+Ci) ・”・
It can be expressed as (2). Then, the voltage W2 of the transistor Qo base 60 immediately before the next readout is the voltage V
In the primary read that becomes d p V e + V ph, the address pulse W1 becomes the voltage v1. As it rises to I,
Since W2 increases by the voltage vll, the voltage Vd momentarily increases.
It rises to F+Vρh. This potential is transistor Q.

Since it is applied to the base of W2, charge flows as a base current, and eventually the potential of W2 is reset to voltage VdP. Therefore, a charge Qph corresponding to the voltage Vph is finally taken out. If the time constant of this extraction is τ, then the base current I8 is expressed by the first-order equation 4. The % current is the base current 8 multiplied by hFg.

It is taken out as the voltage across the load resistor RL.

The voltage waveform of this optical output is W3, and the optical output voltage Vou
t is expressed by linear equation (4).

Since the signal is multiplied and taken out, it has the great advantage of considerably improving the S/N ratio. However, there is a problem in that reducing the pixel size is expensive.

The reason for this is that there is an N+ diffusion layer 901 in the P+ diffusion layer 60.
, 902, it is necessary to provide a margin for mask alignment. Furthermore, there is also the problem that the light-receiving size is restricted by wiring and the like, and the separation area between pixels is not functioning, so the aperture ratio is kept small.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned problems, and its purpose is to provide a solid-state imaging device with a small pixel size and a large aperture ratio.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a separation groove for separating unit bits constituting one pixel is provided on a first conductivity type semiconductor substrate, an insulator is provided in the lower part of the separation groove, a wiring conductor is provided in the upper part of the separation groove,
A second conductivity type diffusion region is provided above the unit bit portion, and a first conductivity type high concentration diffusion region is provided in a region where the wiring conductor and the side surface of the unit bit portion are in contact with each other, and a first conductivity type semiconductor substrate is provided. and a solid-state image pickup with a small pixel size and a large aperture ratio, characterized in that the photocurrent generated from the photodiode formed in the second conductivity type diffusion region is extracted from the wiring conductor. It is a device.

[Structure of the invention]

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures for explaining an example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

1 is a plan view of a pixel in a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA in FIG. 1, and FIG. 3 is a sectional view taken along line AA in FIG. 4 is a sectional view taken along a cutting line, and FIG. 4 is an equivalent circuit diagram of FIG. 1. In addition,
In FIG. 1, insulating films other than the element isolation insulating film are not shown in order to make the configuration of one pixel easier to see.

1 to 4, 1 is an N++ buried layer, 2 is an N- type epitaxial layer, and 3 is an element isolation insulating film for isolating pixels.

In FIG. 1, the buried layer 1 and epitaxial layer 2 are not shown to make the structure easier to see. This element isolation insulating film 3 is provided inside a groove 4 (the lead line points to the wall surface of the groove 4) that penetrates the epitaxial layer 2. For this reason, the N- type epitaxial layer 2 is divided into a plurality of rectangular parts by the element isolation insulating film 4, as shown in FIG. 5 is an N++ polycrystalline silicon layer;
It is deposited on the upper surface of the element isolation insulating film 3 and provided in a pattern as shown in FIG. Further, the N+ type polycrystalline silicon layer 5 is provided at the upper end of the trench 4, and there is no height difference between it and the upper surface of the epitaxial layer 2 (it is flat).

These epitaxial layers 2. Polycrystalline silicon layer 5 and element isolation insulating film 3 exposed from polycrystalline silicon layer 5
A protective film 6 made of a silicon oxide film covers the upper surface of the device.

7 is a P+ type diffused layer, and 8 is an N+ type diffused layer.

N+ type scattered layer 8. It is formed near the surface where the polycrystalline silicon layer 5 and the sidewall of the epitaxial layer 2 are adhered. The P+ type diffusion layer 7 is formed on the upper surface of the epitaxial layer 2 and around the N+ type scattering layer.

The part indicated by 7A of the P" type diffusion layer 7 is the base, and the part indicated by N
The transistor Q shown in FIG. 4 is constructed by using the portion 8A of the + type scattering layer 8 as an emitter and the epitaxial layer 2 as a collector. To reduce the collector resistance, an N++ buried layer 1 is provided, and this N++ buried layer 1 is connected to the power supply voltage Vcc.

On the other hand, the part shown by 8B of the N+ type scattering layer 8 and the P
The portion indicated by 7B of the + type diffusion layer 7 forms a capacitor C, and the P+ type diffusion layer 7B and the epitaxial layer 2 constitute a photodiode Db. That is, the P+ type diffusion layer 7B.

One electrode of the capacitor C, and also the photodiode Dh
is the anode of Further, the P+ type diffusion layer 7B is integrally formed with the base of the transistor Q, that is, the P+ type diffusion layer 7A. Therefore, as shown in FIG. 4, one electrode of the capacitive element C and the anode of the photodiode Dh are connected to the base of the transistor Q without any wiring.

Of the polycrystalline silicon layers 5, the polycrystalline silicon layer 5A is an input terminal, and the polycrystalline silicon layer 5B is an optical output readout line. The optical readout line 5B is connected to an external load resistor R, and is connected to the ground potential V through the load resistor RL.
It is connected to ss.

The optical output is taken out as a voltage across the load resistor RL.゛As can be understood from Fig. 4, the transistor Q and the capacitance C
, photodiode Dh constitute one bit, and two bits constitute one pixel. Further, two bits are connected to one input terminal 5A. Therefore, one input terminal 7
When an address pulse is input to A, a 2-bit photocurrent is extracted.

As can be understood from the above description of the structure, the polycrystalline silicon layer 5 used as the wiring is provided on the pre-isolation insulating film 3 in the groove 4, so the upper surface of the epitaxial layer 2 and the polycrystalline silicon layer There is no difference in height between the top surface of 7 and the surface is flat. Therefore, the polycrystalline silicon layer 5 is
Since light is not blocked, the aperture ratio can be increased. Furthermore, since the groove 4 separating the bits is deep enough to penetrate the epitaxial layer 2 and reach the N+ type buried layer 1, the photocharge generated in each photodiode Dh does not flow into other bits. There is no. That is, since the photocharges generated in each bit are taken out as photocharges within that bit, it is possible to eliminate crosstalk between bits and improve the reliability of the solid-state imaging device.

Note that although this embodiment has described a solid-state imaging device configured by one-dimensionally arranging a plurality of bits, the solid-state imaging device may also be configured by arranging a plurality of bit strings in the above-mentioned -dimensional array in parallel. 9 In this embodiment, in order to increase the capacitance value of the capacitive element to which the address pulse is applied,
Although one pixel is made up of 2 bits, it may be made up of 1 bit I pixel.

Next, a method of manufacturing the solid-state imaging device of this embodiment will be described.

5, 7, 9, and 11 are plan views of pixels during the manufacturing process of the solid-state imaging device of this embodiment,
Figure 6 is Figure 5, Figure 8 is Figure 7, Figure 10 is Figure 9.
In the figure, FIG. 12 is a sectional view taken along the line AA in FIG. 11, respectively.

In the manufacturing method of the solid-state imaging device of this embodiment, first, the silicon oxide film 9 shown in FIGS.
A bit pattern resist mask 10 is further formed on the silicon oxide film 9 by oxidizing the surface of the silicon oxide film 2 . Next, the silicon oxide film 9 exposed from the resist mask 10 is removed by etching, and then the resist mask 10 is removed.

Next, the remaining silicon oxide 1119 is used as a mask.

Epitaxial layer 2 is formed by anisotropic dry etching.
As shown in FIGS. 7 and 8, grooves 4 reaching the buried layer 1 are formed by etching.

By this etching, the epitaxial layer 2 is patterned into a bit pattern.

Note that in FIGS. 7 and 8, the wall surface of the groove 4 is indicated. In the drawings used to explain the manufacturing process below, the wall surface of the groove 4 will be referred to as well.

After forming the trench 4, a silicon oxide film is buried in the trench 4 by, for example, CVD, and is formed to cover the top surface of the epitaxial layer 2. Then, the silicon oxide film is etched from the top surface by anisotropic etching to form the trench. The element isolation insulating film 3 is formed by leaving only the inside of the insulating film 4 . Note that the anisotropic etching is as shown in FIG.

After the upper surface of the epitaxial layer 2 is exposed, etching is further progressed to remove the element isolation insulating film 3 at the upper end of the trench 4. As explained in the description of the structure, this is to prevent a step from being formed between the polycrystalline silicon layer 5 provided on the element isolation insulator [3] and the epitaxial layer 2. Next, four p-type impurities such as boron (B) are added into the epitaxial layer 2 by thermal diffusion or the like to form a P"-type diffusion layer 7 as shown in FIGS. 9 and 10. In FIG. 9, in order to make it easier to understand the pattern of the P+ type diffusion layer 7, the P1 type diffusion layer 7 is
The lower epitaxial layer 2 of P is not shown.
After forming the + type diffusion layer 7, an N+ type polycrystalline silicon layer 5 is formed on the entire upper surface of the epitaxial layer 2 and the element isolation insulating film 3 by CVD or the like, and then the N+ type polycrystalline silicon layer 5 is The polycrystalline silicon M5 is etched from the top surface by directional dry etching to leave the polycrystalline silicon M5 only on the element isolation insulating film 3, as shown in FIGS. 11 and 12. The polycrystalline silicon layer 5 is etched until the top surface of the epitaxial layer 2 is exposed.
There should be no step difference between the epitaxial layer 2 and the polycrystalline silicon layer 5.8 Note that in FIG. 11, the elements below the polycrystalline silicon layer 5 are The isolation insulating film 3 is not shown. The subsequent manufacturing process will be explained using FIGS. 1 to 3. As described above, after forming the polycrystalline silicon layer 5 remaining on the element isolation insulating film 3, The polycrystalline silicon layer 5 is patterned by etching as shown in FIG. For example, a resist is used as an etching mask. Thereafter, annealing is performed to eliminate n-type impurities in the polycrystalline silicon layer S, such as phosphorus (
By diffusing P) into the epitaxial layer 2,
An N+ type dispersed layer 8 is formed. Thereafter, a silicon oxide film is deposited by CVD or the like on the polycrystalline silicon layer 5, epitaxial layer 2, and element isolation insulating film 3 to form a protective film 6.

As you can understand from the above explanation, N-type epitaxial! 2 to the N++ buried layer 1, and for this groove 4, an element isolation insulating film 3, a P+ type diffusion layer 7. Since each of the N+ type scattering layer 8N'' type polycrystalline silicon layer 5 is formed by self-line, there is no need for a mask alignment margin between them, so that the pixel and element isolation insulating film 3 can be miniaturized. It is possible, ie.

High integration can be achieved.

In the manufacturing method described above, the polycrystalline silicon layer 5 is used for the electrode or wiring of one pixel, but the polycrystalline silicon layer 5 is not necessarily limited to the polycrystalline silicon layer 5. A silicide layer may also be used. Even when the silicide layer is used as an electrode or wiring, n-containing substances such as phosphorus or arsenic are present in the silicide layer.
By containing type impurities, the N+ type scattering layer 7 can be formed by the same method as in the case of forming using the N' type polycrystalline silicon layer 5.

[Effects] As described above, according to the present invention, a polycrystalline silicon layer used as a pixel electrode or wiring is provided at the upper end of a trench in which an element isolation insulating film is provided.

Moreover, since the upper surface of the polycrystalline silicon layer is not higher than the upper surface of the epitaxial layer, the polycrystalline silicon layer does not block light, so that the aperture ratio can be increased.

In addition, the epitaxial layer is penetrated between bits, and N
++ Create a deep groove that reaches the buried layer.

By filling this deep groove with an insulating material and forming an insulating film for element isolation, the photocharge generated in the photodiode will not flow into other bits, eliminating crosstalk between bits and forming a solid-state The reliability of the imaging device can be improved.6 On the other hand, for the deep trenches reaching from the epitaxial layer to the N++ buried layer, there is no room for device isolation.

By forming each of the N+ type scattering layer P+ type diffusion layer and the polycrystalline silicon layer using self-line, there is no need for a mask alignment margin between them, so it is possible to reduce the fineness of the pixel and element isolation insulating films. It is possible to aim for

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

1 is a plan view of a pixel of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 4 is an equivalent circuit diagram of FIG. 1, which is a sectional view taken along section line B. 5, 7, 9, and 11 are plan views during the manufacturing process of a solid-state imaging device according to an embodiment of the present invention; FIG. 6 is a plan view of FIG. 5, and FIG. Figure 7 and Figure 10 are the 9th
In the figure, FIG. 12 is a sectional view taken along the line AA in FIG. 11, respectively. FIGS. 13 to 9516 are diagrams for explaining problems in conventional solid-state imaging devices. In the figure, 1... N++ buried layer, 2... N- type epitaxial layer, 3... Insulating film for element isolation, 4... Groove,
5.5A, 5B...N+ type polycrystalline silicon layer, 6...
・Protective film, 7...P+ type diffusion layer, 8...N+ type scattering layer 9...Silicon oxide film, 10...Resist mask, Q...Transistor, Dh...Photodiode , C... Capacitive element, RL... Load resistance.

Claims (1)

[Claims] (1) A separation groove for separating unit bits constituting a pixel is provided on the first conductivity type semiconductor substrate, an insulator is provided in the separation groove, and a conductor for wiring is provided above the insulator in the separation groove. a second conductivity type diffusion region is provided above the unit bit portion, and a first conductivity type high concentration diffusion region is provided in a region where the wiring material and the side surface of the unit bit portion are in contact with each other. A solid-state imaging device characterized in that the photocurrent generated from the photodiode formed by the semiconductor substrate and the second conductivity type diffusion region is extracted from the wiring conductor.