JP2005277155A - Semiconductor imaging device and method for controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging function simple to control and excellent in performance for a 1-transistor/1-pixel type semiconductor imaging device. <P>SOLUTION: A pixel is composed of a pixel transistor 25 which is a P-type FET and a photodiode 20, the well layer 4 of the pixel transistor 25 and the N-type well layer on the light-receiving side of the photodiode 20 are integratedly formed and electrically connected to each other, and the P-type well layer of the photodiode 20 is formed to surround the N-type well layers for the constitution of a floating well. The potential produced in the photodiode 20 is impressed on the pixel transistor 25 via the floating well, and the amount of light entering the photodiode 20 is determined by sensing changes in the threshold of the pixel transistor 25. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CMOS sensor type semiconductor imaging device having an imaging unit in which a plurality of pixels each constituted by one pixel transistor are integrated in a two-dimensional array, and a control method thereof.

Conventionally, a CMOS sensor type in which a photoelectric conversion element such as a photodiode and a pixel transistor are provided in a plurality of pixels provided in a two-dimensional array on a semiconductor chip, and a signal charge generated by the photoelectric conversion element is read by the pixel transistor. The semiconductor imaging device is known.
In such a semiconductor imaging device, a configuration in which a plurality of pixel transistors are provided for each pixel is generally used, and operations such as resetting, reading, and amplifying photoelectric conversion elements are performed by each pixel transistor. The larger the number of pixel transistors provided for each pixel, the larger the space for forming the pixel transistors, which limits the light receiving area of the photodiode and lowers the aperture ratio.

On the other hand, an image pickup apparatus in which one pixel transistor is provided for each pixel is also conventionally known (see, for example, Patent Documents 1 and 2).
This imaging device amplifies and reads out the signal charge of the photodiode by controlling the gate input and bias voltage of the pixel transistor, and resets it, and connects the capacitor to the gate and substrate of the pixel transistor. Thus, the transistor variation is suppressed.
JP-A-2-224480 JP-A-6-245150

However, in the semiconductor imaging device in which the pixel is configured by one pixel transistor as described above, it is not always easy to actually perform an appropriate imaging operation, and the pixel structure and control capable of realizing a good imaging function with simple control A method is required.
SUMMARY OF THE INVENTION An object of the present invention is to provide a 1-pixel 1-transistor type semiconductor image pickup device capable of realizing a good image pickup function with simple control and a control method therefor.

  In order to achieve the above-described object, a semiconductor imaging device of the present invention includes a second conductivity type drain and source formed on the surface of a first conductivity type well layer provided on a semiconductor substrate and spaced apart from each other. A pixel transistor having an intermediate gate, the drain connected to a power supply line, the gate connected to a word line, and the source connected to a vertical signal line; and a first transistor formed on the semiconductor substrate. A photoelectric conversion element including a conductive type well layer and a second conductive type well layer; and a first conductive type well layer of the pixel transistor and a first conductive type well layer of the photoelectric conversion element. Are electrically connected to each other, and a second conductivity type well layer of the photoelectric conversion element is provided in a state of surrounding the first conductivity type well layer, and floating by the well layer of the first conductivity type is provided. We Characterized by being configured to.

  The control method of the present invention includes a second conductivity type drain and source formed on the surface of a first conductivity type well layer provided on a semiconductor substrate and spaced apart from each other, and a gate provided therebetween. A pixel transistor having a drain connected to a power line, a gate connected to a word line, and a source connected to a vertical signal line; a first conductivity type well layer formed on the semiconductor substrate; A photoelectric conversion element composed of a two-conductivity type well layer, and the first conductivity type well layer of the pixel transistor and the first conductivity type well layer of the photoelectric conversion element are electrically connected. In addition, a semiconductor imaging device in which a second conductivity type well layer of the photoelectric conversion element is provided so as to surround the first conductivity type well layer, and a floating well is formed by the first conductivity type well layer. A driving method, the potential generated in the photoelectric conversion element is applied to the pixel transistor through the floating well, and detecting the amount of light incident from the change in the threshold of the pixel transistor to the photoelectric conversion element.

  According to the semiconductor imaging device and the control method thereof of the present invention, the first conductivity type well layer of one pixel transistor constituting the pixel cell is electrically connected to the first conductivity type well layer of the photoelectric conversion element. And a pixel structure in which the second conductivity type well layer of the photoelectric conversion element is provided so as to surround the first conductivity type well layer, and a floating well is formed by the first conductivity type well layer. By applying a potential generated in the photoelectric conversion element to the pixel transistor through the floating well, it becomes possible to detect the amount of light incident on the photoelectric conversion element from a change in the threshold value of the pixel transistor. There is an effect that it is possible to provide a one-pixel one-transistor type semiconductor imaging device that can be realized.

  In the embodiment of the present invention, a pixel cell is constituted by a pixel transistor and a photodiode using one P-type FET, and the N-type well layer of the pixel transistor and the N-type well layer on the light receiving portion side of the photodiode are integrated. Are formed and electrically connected, and a P-type well layer of the photodiode is provided so as to surround the N-type well layer, thereby forming a floating well by the N-type well layer, which is generated in the photodiode. The applied potential is applied to the pixel transistor through the floating well, and the amount of light incident on the photodiode is detected from the change in the threshold value of the pixel transistor.

FIG. 1 is an equivalent circuit diagram showing a configuration of a pixel cell of a semiconductor imaging device according to an embodiment of the present invention. 2 is a schematic cross-sectional view showing a stacked structure of the pixel cell shown in FIG. 1, and FIG. 3 is a schematic plan view showing an element arrangement (layout) of the pixel cell shown in FIG.
The semiconductor imaging device of this example has one photodiode 20 and pixel (cell) transistor 25 for each pixel.
The cell transistor 25 is a P-type FET formed on the semiconductor substrate 1 by a CMOS process. The drain 7 a is connected to the power supply line 11, the gate 6 is connected to the word line 23, and the source 7 b is connected to the vertical signal line 15. The word line 23 is connected to the first scanner 21, and the power line 11 is connected to the second scanner 22.
The vertical signal line 15 is connected to a signal detection circuit 29, which is connected to a timing control circuit (not shown) so that the operations of the scanners 21 and 22 and the pixel cells are controlled by this timing control circuit. It has become.

The cell transistor 25 has two impurity regions (second type (P type) semiconductors) formed on the surface of the first conductive type (N type) semiconductor well layer 4 formed on one main surface of the semiconductor substrate 1. A drain electrode 7a and a source electrode 7b) are formed apart from each other, and a gate electrode 6 is formed so as to face the well layer 4 between the impurity regions 7a and 7b with the insulating film 5 interposed therebetween.
Impurity region 7a is connected to wiring 11 by conductor 10 in connection hole 9 in upper layer film 12, impurity region 7b is connected to the same wiring layer as wiring 11 by conductor 10 in connection hole 9, and further connected hole 13 is connected to the upper wiring 15 by a conductive material 14.

The photodiode 20 is composed of two opposite conductivity type impurity regions (well layer 3 and well layer 4) in the semiconductor substrate 1, and the well of the cell transistor 25 and the well of the photodiode 20 are the common well layer 4. . The well layer 4 functions as a floating well for sending floating charges generated in the photodiode 20 to the cell transistor 25. A well layer 3 having a conductivity type opposite to that of the well layer 4 is formed so as to surround the lower portion of the well layer 4 and the measurement portion and to separate each pixel cell.
A thermal oxide film 2 for element isolation is formed on the upper surface of the semiconductor substrate 1. Further, a not-shown planarizing film or the like is disposed on the upper layer wiring 15, and further, a color filter, a microlens, or the like is disposed thereon.

In the pixel cell structure according to the present embodiment, the well of the cell transistor 25 and the well of the light receiving portion of the photodiode 20 are collectively ion-implanted by the same photoresist pattern forming the common well layer 4. It is formed with. Since the well of the cell transistor 25 and the well of the light receiving unit are common, the potential generated by the photodiode 20 is transmitted to the well of the cell transistor 25. For this reason, when light enters the light receiving portion of the photodiode 20 and the well potential changes, the threshold value of the cell transistor 25 changes, so that the current driving capability also changes. In this manner, the amount of light incident on each cell is identified by the signal detection circuit 29 as the characteristic of the cell transistor 25, and used as pixel data for each cell.
Further, since each pixel cell has only one transistor, the area of the pixel cell can be reduced. In addition, when the circuit is simplified, the number of wirings and the number of layers are reduced (specifically, the number of wirings is as few as three of a power supply line, a word line, and a vertical signal line). , Improve sensitivity.

Next, a method for manufacturing such an image pickup apparatus of this embodiment will be described.
4-6 is sectional drawing which shows the element structure in each process of the manufacturing method of this example.
First, a silicon oxide film is formed on the semiconductor substrate 1, a silicon nitride film is formed thereon, a photoresist is formed in a predetermined pattern so that there is no photoresist in the element isolation region, and the silicon nitride film is etched. To do. Then, after removing the photoresist and oxidizing the substrate surface, the thermal oxide film 2 is formed in the element isolation region using the silicon nitride film formed in the pattern as an oxidation mask. Thereafter, the silicon nitride film is removed by etching with phosphoric acid (FIG. 4A).
Next, a photoresist 26 is formed so as to open a region including the light receiving portion of the pixel cell and the cell transistor. Then, using the photoresist 26 as a mask, first conductivity type impurity ions are implanted to form the well layer 4, contacting the lower portion of the well layer 4, and the well layer 3 having a conductivity type opposite to that of the well layer 4 to the second layer. The conductive impurity ions are implanted (FIG. 4B).
Next, after removing the above-described photoresist 26, a photoresist 27 is patterned so as to open the periphery of the well layer 4 of each pixel cell so as to surround the side portion of the well layer 4 of the pixel cell. Impurities of the same conductivity type as the well layer 3 are implanted so as to connect the three (FIG. 4C).

  Next, after removing the photoresist 27 described above and etching the silicon oxide film on the active region, the surface of the semiconductor substrate is oxidized to form a gate oxide film 5 having a predetermined thickness. Then, for example, polysilicon is formed as a gate of the transistor, a desired impurity is doped in an appropriate amount, a photoresist is patterned in a predetermined layout, and the polysilicon is etched using the photoresist as a mask to form a gate electrode 6. . Then, impurity regions 7a and 7b to be the drain and source regions of the transistor are formed by ion implantation using the gate electrode 6 as a mask. Next, the impurity region is activated by applying an appropriate heat treatment step (FIG. 5D).

  Next, an interlayer insulating film 8 is formed on the surface of the substrate, the surface of the interlayer insulating film 8 is flattened, and a pattern for forming a contact hole is patterned with a photoresist. Then, using this photoresist as a mask, the interlayer insulating film 8 and the gate oxide film 5 are etched by RIE, and a contact hole 9 is opened. Next, after depositing a conductive material such as tungsten, the conductive material 10 such as tungsten is buried only in the contact hole by etch back or CMP. Thereafter, a wiring material such as aluminum or copper is formed and processed into a predetermined layout to form the wiring 11 (FIG. 5E).

  Next, after the interlayer insulating film 12 is formed on the surfaces of the interlayer insulating film 8 and the wiring 11 and the surface of the interlayer insulating film 12 is flattened, a contact hole forming pattern is patterned with a photoresist. Using the photoresist as a mask, the interlayer insulating film 12 is etched by RIE, and a contact hole 13 is opened on the wiring 11. Next, after depositing a conductive material such as tungsten, the conductive material 14 such as tungsten is buried only in the contact hole by etch back or CMP. Thereafter, a wiring material such as aluminum or copper is formed and processed into a predetermined layout to form the wiring 15 (FIG. 6F).

In the manufacturing method as described above, as an example of the conductivity type of the semiconductor substrate 1, the conductivity type of the well or drain / source, the semiconductor substrate 1 is N-type, the well layer 3 is P-type, the well layer 4 is N-type, the drain The source regions 7a and 7b can be P-type. Boron or the like is used as an impurity to be injected into the P-type well layer 3, and phosphorus or the like is used as an impurity to be injected into the N-type well layer 4. Boron, BF2, or the like is used for the P-type drain / source regions 7a and 7b.
Further, when the well layer 4 is formed in FIG. 4C, ions may be implanted for the purpose of forming a punch-through stopper and an impurity profile for adjusting a threshold value.

  Further, instead of the element arrangement of the pixel cell shown in FIG. 3, the light receiving portion (photodiode 20) and the cell transistor 25 may be separated by element isolation as shown in FIG. As a result, there is an advantage that the area of the light receiving portion is not changed due to misalignment at the time of impurity implantation of the source / drain 7a and 7b.

  FIG. 8 is a schematic plan view showing the element arrangement of the pixel cell when the word line 23 is formed of the third metal wiring layer. In this example, the first-layer metal pad connected from the gate electrode 6 is laid out so as to be separated from the power supply line 11. Since the word line is a third-layer metal wiring, the distance between the first-layer metal pad connected to the source 7b and the power supply line 11 can be reduced, so that there is an advantage that the cell area can be reduced.

Next, the control operation of the pixel cell in the present embodiment as described above will be described.
FIG. 9 is an equivalent circuit diagram showing an example in which 1-transistor pixel cells according to this embodiment are connected as a cell array of 3 columns × 2 rows, and FIG. 10 is a timing chart showing the operation timing of the pixel cells shown in FIG. is there.
As shown in FIG. 9, the pixel cells in the same row share word lines 33 and 37, power supply lines 34 and 38, and scanners 31, 32, 35, and 36, respectively. The pixel cells in the same column share the vertical signal lines 39 to 41.
In FIG. 10, when reading the cells in the first row, the word lines 33 and the power supply lines 34 of the cells other than the first row are set to 0V. Then, a Vcc potential (forward bias voltage) is applied to the scanner (1-2) 32 to reset the potential of the light receiving portion of the cell.
Next, a −Vcc potential (reverse bias voltage) is applied to the scanner (1-2) 32, and then a −Vcc potential is applied to the scanner (1-1) 31.
With this operation, the cell transistor 25 is turned on when the amount of charge generated in the light receiving portion is small. However, when the amount of charge generated in the light receiving portion is large, the well potential of the cell transistor 25 rises, so the threshold value becomes high, and the cell transistor 25 remains OFF. Since the threshold value changes according to the amount of charge generated in the light receiving unit, the ON time of the cell transistor and the output signal level change according to the amount of light incident on the light receiving unit, and the voltage output to the vertical signal lines 39 to 41 Is different. Therefore, the amount of received light can be detected by detecting the change in voltage.

Next, when reading the cells in the second row, the word lines 37 and the power supply lines 38 of the cells other than the second row are set to 0V. A Vcc potential is applied to the scanner (2-2) 36 to reset the potential of the light receiving portion of the cell. Next, a -Vcc potential is applied to the scanner (2-2) 36, and then a -Vcc potential is applied to the scanner (2-1) 35. Since the threshold value changes according to the amount of charge generated in the light receiving unit, the ON time of the cell transistor and the output signal level change according to the amount of light incident on the light receiving unit, and the voltage output to the vertical signal lines 39 to 41 Is different. Therefore, the amount of received light can be detected by detecting the change in voltage.
Thereafter, all pixels in the cell array can be read out by reading out the cells in the next row in the same manner.
It should be noted that the specific voltage values and the like used here are merely examples and can be changed as appropriate.

With the configuration of the present embodiment as described above, the following effects can be obtained.
(1) In the pixel cell structure of this embodiment, a pixel cell of a one-transistor type CMOS sensor can be realized by applying the well potential generated in the light receiving portion to the well of the cell transistor, thereby reducing the pixel area. be able to.
(2) Since the well of the light receiving portion and the well of the cell transistor are formed by the same patterning and the same impurity implantation, it can be realized without complicating the manufacturing process.
(3) No wiring is required between the well of the light receiving portion of the photodiode and the well of the cell transistor, and there are only three wirings of the power supply line, the word line, and the vertical signal line in the pixel cell, and the node Since there is no wiring connecting between them, the area occupied by the wiring is small. Therefore, the aperture ratio in the pixel cell can be increased.
(4) The potential generated in the photodiode is applied to the cell transistor through the floating well (well layer 4), and the incident light quantity of the photodiode is detected from the change in the output signal caused by the change in the threshold value of the cell transistor. Therefore, accurate light quantity detection can be performed with a simple element structure.
Specifically, a predetermined forward bias voltage is applied to the drain of the cell transistor to deplete the photodiode, the signal charge of the photodiode is reset, and then a predetermined reverse bias voltage is applied to the drain of the cell transistor. Subsequently, by applying a drive voltage corresponding to the reverse bias voltage to the gate of the cell transistor, it is possible to detect a source signal that appropriately reflects the change in the threshold value of the cell transistor, and to accurately detect each pixel. realizable.

1 is an equivalent circuit diagram illustrating a configuration of a pixel cell of a semiconductor imaging device according to Embodiment 1 of the present invention. It is sectional drawing which shows the element structure of the pixel cell of the semiconductor imaging device shown in FIG. It is a top view which shows the element arrangement | positioning of the pixel cell of the semiconductor imaging device shown in FIG. It is sectional drawing which shows the element structure in each process of the manufacturing method of the semiconductor imaging device shown in FIG. It is sectional drawing which shows the element structure in each process of the manufacturing method of the semiconductor imaging device shown in FIG. It is sectional drawing which shows the element structure in each process of the manufacturing method of the semiconductor imaging device shown in FIG. It is a top view which shows the other example of element arrangement | positioning of the pixel cell of the semiconductor imaging device shown in FIG. It is a top view which shows the other example of the element arrangement | positioning of the pixel cell of the semiconductor imaging device shown in FIG. FIG. 2 is an equivalent circuit diagram showing an example in which a plurality of pixel cells of the semiconductor imaging device shown in FIG. 1 are connected. 10 is a timing chart showing an example of the operation of the circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3, 4 ... Well layer, 20 ... Photodiode, 25 ... Cell transistor, 11 ... Power supply line, 15 ... Vertical signal line, 23 ... Word line.

Claims (5)

A drain and a source of a second conductivity type formed on the surface of a well layer of a first conductivity type provided on a semiconductor substrate and spaced apart from each other, and a gate provided in the middle, the drain being a power line A pixel transistor having a gate connected to a word line and a source connected to a vertical signal line;
A photoelectric conversion element comprising a first conductivity type well layer and a second conductivity type well layer formed on the semiconductor substrate;
The first conductivity type well layer of the pixel transistor and the first conductivity type well layer of the photoelectric conversion element are electrically connected, and the photoelectric transistor is surrounded by the first conductivity type well layer. A second conductivity type well layer of the conversion element is provided, and a floating well is formed by the first conductivity type well layer;
A semiconductor imaging device.   2. The semiconductor imaging device according to claim 1, wherein the first conductivity type well layer of the pixel transistor and the first conductivity type well layer of the photoelectric conversion element are formed by the same patterning and the same impurity implantation. apparatus.   2. The semiconductor imaging device according to claim 1, wherein the first conductivity type well layer is an N-type well layer, and the pixel transistor is a P-type field effect transistor. A drain and a source of a second conductivity type formed on the surface of a well layer of a first conductivity type provided on a semiconductor substrate and spaced apart from each other, and a gate provided in the middle, the drain being a power line A pixel transistor having a gate connected to a word line and a source connected to a vertical signal line;
A photoelectric conversion element comprising a first conductivity type well layer and a second conductivity type well layer formed on the semiconductor substrate;
The first conductivity type well layer of the pixel transistor and the first conductivity type well layer of the photoelectric conversion element are electrically connected, and the photoelectric transistor is surrounded by the first conductivity type well layer. A method of driving a semiconductor imaging device, wherein a second conductivity type well layer of a conversion element is provided, and a floating well is formed by the first conductivity type well layer,
Applying a potential generated in the photoelectric conversion element to the pixel transistor through the floating well, and detecting an incident light amount to the photoelectric conversion element from a change in a threshold value of the pixel transistor;
A method for controlling a semiconductor imaging device. A predetermined forward bias voltage is applied to the drain of the pixel transistor to deplete the photoelectric conversion element, the signal charge of the photoelectric conversion element is reset, and then a predetermined reverse bias voltage is applied to the drain of the pixel transistor. Subsequently, a change in signal level output from the source of the pixel transistor is detected by applying a drive voltage corresponding to the reverse bias voltage to the gate of the pixel transistor.
The method of controlling a semiconductor imaging device according to claim 4.

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