JPS62151947A - Memory address tracing system - Google Patents

Abstract

PURPOSE:To easily debug a software by tracing including an operand address and displaying the presence or absence of the operand address by a flat bit when there is the operand address in an instruction by an instruction fetching address. CONSTITUTION:When there is an operand address in an instruction by an instruction fetching address, a flag bit 3a is set, and the instruction fetching address is accommodated in a stack memory 2 for an instruction fetching address. Into the address of a stack memory 3 for the operand address corresponding to the stack memory address to accommodate the instruction fetching address, the operand address is accommodated. Namely, the presence or absence of the operand address can be displayed by the flag bit 3a. Thus, it can be identified easily and without fail whether or not there is the aperand in the instruction, and debugging can be facilitated.

Description

[Detailed Description of the Invention] [Summary] In addition to tracing instruction fetch addresses in a specified range, if there is an operand address in an instruction based on the instruction fetch address, tracing includes that operand address. The flag bit indicates the presence or absence of an operand address, making software debugging easier.

[Industrial application field]

The present invention relates to a memory address tracing method for tracing access addresses to main memory.

A memory address tracing method is known that facilitates debugging by tracing a predetermined range of memory addresses using the trace function, and when the trace stops, checking the history of each instruction from the memory address at that time. There is.

[Conventional technology]

The trace function is an effective function for debugging. For example, each time an instruction is executed, the instruction fetch address, instruction code, register contents, memory contents, etc. are written to the stack memory, and the program is At that point, go back in time from the execution of the instruction at the access address at that time,
Read the contents of the stack memory and display it on a CRT (cathode ray tube)
The information is displayed on a display device or printed out using a printer, and the history of each command execution is tracked. The memory address tracing method using such a trace function stores the instruction fetch address within a specified range in the stack memory and traces it.In order to trace the operand address along with the instruction fetch address, When there is no operand address, writing a fixed bit pattern is adopted.

[Problem that the invention seeks to solve]

In the conventional example described above, when there is no operand address in an instruction, a certain bit pattern is written, but no matter what pattern is adopted, it is impossible to reliably determine the presence or absence of an operand address. Because it is difficult,
When debugging, it is necessary to check the type of instruction, which has the disadvantage of increasing the time required for debugging.

An object of the present invention is to facilitate identification of the presence or absence of an operand address, thereby facilitating debugging.

[Means for solving problems]

The memory address tracing method of the present invention uses flag bits to indicate the presence or absence of an operand address, and will be explained with reference to FIG.

A stack memory is connected to the memory address bus of the main memory 1, and is composed of a stack memory L;l:, a stack memory 2 for instruction fetch addresses, and a stack memory 3 for operand addresses, and a flag bit 3a in the stack memory 3 for operand addresses. If there is an operand address in the instruction using the instruction fetch address, flag bit 3a is set and the instruction fetch address is stored in the instruction fetch address stack memory 2.
At the same time, the operand address is stored at the address in the operand address stack memory 3 corresponding to the stack memory address where the instruction fetch address is stored.

[Effect]

Since the presence or absence of an operand address can be indicated by the flag bit 3a, it becomes possible to reliably and easily identify whether or not an operand address exists in an instruction, making debugging easier.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a schematic block diagram of an embodiment of the present invention, and 11
．． 12 is a central processing unit (cco, cc.

), 13.14 is the main memory (MM o + MMl
), 15.16 is stack memory, 17 to 20 are memory address buses, and 21.22 is memory address register (
MAR), 23.25 is a stack memory for instruction fetch addresses (STKA), and 24.26 is a stack memory for operand addresses (STKB). Flag bits (not shown) are provided in the operand address stack memories 24 and 26.

A case is shown in which a redundant configuration is used with the central processing unit 1L12 and the main memory 13゜14, and when the active system is configured with an O system consisting of the central processing unit 11 and the main memory 13, the memory address set in the memory address register 21 The main memories 13 and 14 are accessed, and in the case of data writing, the same data is written to the same address, and in the case of data reading, it is read from the active main memory 13. Regardless of the current or standby configuration, when the main memory 13 of the 0 system is accessed by the central processing unit 11 of the O system, it is traced by the stack memory 15, and the main memory 14 of the 1 system is accessed by the central processing unit 11 of the 1 system. When accessed by device 12, it is traced by stack memory 16.

If the instruction fetch address is within the specified range, it is written to the instruction fetch address stack memory 23, 25, and if there is an operand address in the instruction by the instruction fetch address, it is written to the operand address stack memory 23.25. It sets the flag bits of 24 and 26 and writes the operand address.

FIG. 3 is a block diagram of the stack memory according to the embodiment of the present invention, in which 31 is a stack memory for instruction fetch addresses (STKA), 32 is a stack memory for operand addresses (STKB), and 33 is a stack pointer (
SPNT), 34 is a control unit, 35 to 43 are AND circuits, 44 to 48 are flip-flops for holding signals, 49.
50 is a D flip-flop (1) that operates on a first clock signal (not shown), and 51 to 53 are D flip-flops that operate on a second clock signal (not shown) that has a different phase from the first clock signal. (II).

Also, D0° to D23 are data bus data, PRQ is an operand request signal, IRQ is an instruction fetch request signal, and A
6 o -A 23 is the address signal of the address bus, A
DMT is a trap instruction signal, lR35 is an instruction end instruction signal, IR3 is a next instruction start instruction signal, R/W is a read/write signal, FFG5 is a flip-flop group designation signal, WE is a write enable signal, and RDSG is a read data select signal. 5PNTG is a stack pointer gate signal, 5PNTI is a stack pointer increment signal.

The control unit 34 receives the address signal A via the D flip-flop 52. 0 and each of the aforementioned signals ADMT.

lR35, IR3, R/W, FFG5, etc. are added, and the above-mentioned signals WE and RDSG are added to each part.

It outputs WDSG, 5PNTG, and 5PNTT.

The stack memories 31, 32 can be used as a flip-flop group (FFG), and a designation signal FFG5 specifies whether to use them as the stack memories 31, 32 or as a normal flip-flop group. . Stack memory 31.32
When used as an address terminal A, the address signal from the stack pointer 33 is used as an address terminal A. -I□ and the data added to the data terminal 110o-zs,
It is written by the write enable signal WE or read from the data terminal I/Oo-zz.

This stack pointer 33 sets the initial setting data applied via the data bus according to the output signal of the D flip-flop 53 operated by a second clock signal (not shown), and receives an increment signal 5 from the control section 34.
The stack memory 31 .
Address signals are applied to each of the 32 address terminals An-+t.

A read data select gate is constituted by AND circuits 35 to 37 and the like, and is controlled by a read data select gate signal RDSG from the control section 34, and data read from the stack memories 31 and 32 is sent to the data bus. A write data select gate is constituted by AND circuits 38, 39, 40.41, etc., and is controlled by a write data select gate signal WDSG from the control section 34, and write data is added to the stack memory 31.32.

Address signal Δ of the address bus. . ~A Z 3 is the instruction fetch address signal, and the instruction fetch request signal IRQ
-A (When set in the D flip-flop 49, the instruction fetch address signal is outputted via the AND circuit 43, and stacked via the flip-flops 46 to 48, the AND circuit 41 constituting the write data select tote, etc.) It is added to the data terminal I10°-23 of the memory 31, and from the stack pointer 33 to the address terminal A o -
An instruction fetch address signal is written to stack memory 31 according to the address signal applied to I2.

If the instruction based on this instruction fetch address does not include operand memory access, the operand request signal PR
Since Q becomes "0", the AND circuit 42 remains closed, and the AND circuit 39 . All “0” output via OR circuit
The signal becomes an all "1" signal and is applied to the data terminal 1/Oo-z3 of the stack memory 32.

At that time, the address terminal A of the stack memory 32. -82
The address signal applied to address terminal A of the stack memory 31. Since it is the same as the address signal added to -1°, all "1"s are written to the address of the stack memory IJ32 that is the same as the stack memory 31 to which the instruction fetch address signal is written.

That is, all "1"s are written including the flag bit.

In addition, when operand memory access is included, the operand request signal PRQ becomes "1" and the D flip-flop 5
1 is opened to the AND circuit 42, so the operand address signal via the address bus is output from the AND circuit 42, and the flip-flop 45. It is added to the stack memory 32 via an AND circuit 39 and the like. At this time, the operand request signal PRQ is sent to the D flip-flop 50.
, becomes a flag bit via the flip-flop 44,
By being inverted by the inverter, it is written into the stack memory 32 as a flag bit of "0".

FIG. 4 is an explanatory diagram of address collection, in which an instruction fetch address signal is added as write data to the stack memory 5TKA via the address buffer l-13F.
The stack memory STKB has an address buffer P.
-An operand address signal is added as write data via BF. For example, since the EX instruction does not generate an operand address, the EX instruction address is written to the stack memory 5TKA, but the EX instruction address is written to the stack memory S
All "1"s including flag bits are written to TKB.

Also, an operand address does not occur in the address of an EXN instruction, but the EXNXN instruction address and operand address are stored in the stack memory 5TKA.
At the same time as the XN instruction address is written, all "1"s including the flag bit are written to the stack memory STKB, and the EXN instruction destination instruction address is written to the stack memory STKΔ, and the EXN instruction destination instruction The operand address of is written to the stack memory 5TKB, and the flag bit becomes "0". Also, if there is one EXNKXN, the EXNK instruction address is stack memory 5TKA.
The operand address a2 is also written to the stack memory 5TKB. The EXNK instruction destination instruction address and the operand address of the EXNK instruction destination instruction are written to stack memories 5TKA and 5TKB, respectively.

When the addresses of such stack memories 5TKA and 5TKB are 0000 to IFFF, respectively, when used as a flip-flop group FFG, consecutive addresses are assigned as shown in FIG.
Internal data will be written using addresses from oo to 3FFF.

FIG. 6 is an explanatory diagram of the sample control register (SCR), where IF indicates instruction fetch, PF indicates operand fetch, and PS indicates operand store. This register instructs to start or stop the operation, the start address of the address range is specified by the sample match start address register (SMSR), and the end address of the address range is specified by the sample match end address register (SMER). Ru.

7A and 7B show operation flowchart 1.
This is about the case of preemption control of instructions. At the start of memory address tracing, the FFG initialization is first performed. That is, the Fritsop flop groove FFG is stored in the stack memory STK8.

The initial settings are made to have a 5TKB configuration, the start address of the address range is specified using the sample match start address register 5M5H, the end address of the address range is specified using the sample match end address register SMER, and the stack memory is specified using the stack pointer 5PNT. Specify the start address of 5TKA and 5TKB.

Next, perform SCR setting (■). That is, the contents of the sample control register SCR (see FIG. 6) are set. 231 of this register SCR. 22″′.

■ Determine whether the 224 bits are "ul", "0", or "1". That is, trap start ("1"), trap selection (
“0”) and 1”) (sixth
(see figure). If this condition is not met, the memory address trace operation is stopped and the process ends.

In addition, in the case of this condition, whether the memory access is a MM access, that is, a memory access, or whether the memory access is an instruction fetch IF
2), or whether it is an operand fetch PF or an operand store PS. If there is no memory access, the process moves to step 0. In the case of operand fetch PF or operand store PS, the contents of memory address buffer MAB should be set to operand address buffer P-BF ((MAB)→P-BF), and the 223 bits of operand address buffer P-BF should be set to “0”. Then, the process proceeds to the MM access identification step (2).That is, the flag bit is set to "0" to indicate that there is an operand address.

In the case of instruction fetch IF, instruction fetch request IRQ
Determine whether JIF is a jump instruction fetch JIF or a normal instruction fetch IF. illr! In the case of a normal instruction fetch IF, the process moves to the next step (2), and in the case of a jump instruction fetch JTF, the next instruction trap instruction flag ADMTFI is set to "0", and the process moves to the next step (3). That is, even if the next instruction trap instruction flag ADMTFI is 1'' indicating a trump instruction, since the jump instruction causes a transition to another instruction, the trap instruction is canceled as 0''. In this step (2), the contents of B to memory address buffer M are sequentially transferred to instruction address buffer I-T3F] ((M
AR)-T-BF 1).

Next, it is determined whether or not the trap instruction signal ADMT is within the trap range, and if it is a trap instruction, step ■
If the instruction is a trap instruction, the contents of the instruction address buffer 1-BFI are transferred to the next instruction address buffer T-B.
Seven steps [(1-BFI)-1-BF2) are made to F2, and the next instruction trap instruction flag ADMTFI is set to 1'' [phase].

Then, it is determined whether or not it is the instruction end instruction signal IR3S. If it is not an instruction end instruction, the process moves to step (2), and if it is an instruction end instruction, the process moves to step @ in FIG. 7B. This step @ is the current instruction trap instruction flag A
This is to determine whether DMTF2 is “1” or “0”. If it is “0”, it moves to step [phase] and goes to “1”.
”, the contents of the current instruction address buffer l-BF3 are written to the stack memory 5TKA, and the contents of the operand address buffer P-BF are written to the stack memory 5TKB ((I-BF3)→5TKA.

(P-BF)→5TKB)@. That is, a write address is designated by stack pointer 5PNT, an instruction fetch address signal is written to stack memory 5TKA, and an operand address is written to stack memory 5TKB. At that time, “0” indicates that there is an operand address.
The flag bits of will also be written.

Upon completion of writing to stack memories 5TKA and 5TKB, the contents of stack pointer 5PNT are incremented by 4-1 ( (
SPNT) +1 → 5PNT) o Next, it is determined whether the next instruction trap instruction flag ADMTFI is "1" or "0", and if it is "1", the next instruction start instruction signal IR3 is determined in the step [phase ], and if it is "0", the current instruction trap instruction flag ADMTF2 is set to "0" and the process moves to step [phase].

When the next instruction start instruction signal IR3 is identified in step [phase], the contents of the next instruction address buffer ■-BF2 are set to the current instruction address pazza 1-BF3, and all "1" are set to the operand address buffer P-BF2. Cent to BF ((1-BF2) → l-BF3. a 11”
l”→P-BFJ @l.If it is not the next instruction start instruction signal, set the current instruction tramp instruction flag ADMTF2 to “
0” [phase] and move to step ①.

Next, the next instruction trap instruction flag ADMTFI is “1”
or “0” [phase].

If it is "0", the process moves to step (2) in FIG. 7A. If it is “1”, the current instruction trap instruction flag AD
Set MTF2 to 1''. Then, trap instruction signal A
It is determined whether it is DMT or not. If it is not a trap instruction, the next instruction trap instruction flag ADMTFI is set to "0" [phase] and the process moves to step (2). Further, in the case of a trap instruction, the process moves to step (3).

The flag bit of the operand address stack memory 5TKB is shown as 0'' indicating that the operand address is present, but it is of course possible to set it as 1.Also, the flag bit is not limited to the above-mentioned embodiment. However, various additions and changes can be made.

〔Effect of the invention〕

As explained above, in the present invention, when there is an operand address in an instruction based on an instruction fetch address, the flag bit 3a is set, the instruction fetch address is stored in the stack memory (STKA) 2, and the operand address is Since it is stored in the stack memory (STKB) 3 and the presence or absence of an operand address can be easily identified, there is no need to check the type of instruction during debugging. Therefore, there is an advantage that rough 1 to wear debugging is facilitated.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a schematic block diagram of an embodiment of the invention, Fig. 3 is a block diagram of a stack memory of an embodiment of the invention, and Fig. 4 is an explanatory diagram of address collection. , FIG. 5 is an explanatory diagram of the flip-flop group 1. Figure 6 is an explanatory diagram of the sample controller I roll register, Figure 7
Figures A and 7B are operational flowcharts. 1 is main memory, 2 is stack memory for instruction fetch address, 3 is stack memory for operand address,
3a is a flag bit, 11.12 is a central processing unit (CC)
O, CC+), 13. 14 is the main memory (M
Mo, MM+), 23. 25.31 is the stack memory (STKA) for instruction fetch address, 2
4, 26. 32 is the stack memory (STKB) for operand addresses, 33 is the stack pointer (SPNT
), 34 is a control section.

Claims (1)

[Claims] A method for tracing access addresses to a main memory (1), comprising a stack memory (2) for instruction fetch addresses and a stack memory (3) for operand addresses; A flag bit (3a) is provided in the stack memory (3) to indicate the presence or absence of an operand address, and when there is an operand address in the instruction based on the instruction fetch address, the flag bit (3) is set to indicate the presence or absence of the instruction fetch address. is stored in the instruction fetch address stack memory (2), and the operand address is stored in the operand address stack memory (3).