JPS6214731Y2 - - Google Patents
Info
- Publication number
- JPS6214731Y2 JPS6214731Y2 JP1979122575U JP12257579U JPS6214731Y2 JP S6214731 Y2 JPS6214731 Y2 JP S6214731Y2 JP 1979122575 U JP1979122575 U JP 1979122575U JP 12257579 U JP12257579 U JP 12257579U JP S6214731 Y2 JPS6214731 Y2 JP S6214731Y2
- Authority
- JP
- Japan
- Prior art keywords
- frequency power
- circuit
- power amplifier
- low frequency
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011159 matrix material Substances 0.000 claims description 4
- 230000003321 amplification Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案は、低周波電力増幅器のアイドリング電
流制御装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an idling current control device for a low frequency power amplifier.
低周波電力増幅器は、出力段の電力増幅用トラ
ンジスタに流すアイドリング電流（無信号時に於
ける電力増幅用トランジスタのコレクタ電流）の
大小によりＡ級、AB級、Ｂ級に分けられ、夫々
効率、性能の面で特徴がある。例えばＡ級の場合
歪（クロスオーバー歪）が生じない利点はあるが
第１図イに示す様に常時出力段の増幅用トランジ
スタに大きなアイドリング電流（Iid）が流れる
ため、無駄な電力損失が大きく効率が悪いという
欠点がある。又、Ｂ級の場合、第１図ロに示す様
にアイドリング電流は流れないから効率は良い
が、電力増幅用トランジスタがスイツチング動作
するので、どうしても歪が生じる欠点があつた。 Low-frequency power amplifiers are classified into class A, class AB, and class B depending on the magnitude of the idling current (collector current of the power amplification transistor when there is no signal) flowing through the power amplification transistor in the output stage, and each class has different efficiency and performance. It is distinctive in terms of. For example, class A has the advantage of not causing distortion (crossover distortion), but as shown in Figure 1A, a large idling current (Iid) constantly flows through the amplification transistor in the output stage, resulting in a large amount of wasted power loss. The drawback is that it is inefficient. In the case of class B, as shown in FIG. 1B, the efficiency is good because no idling current flows, but the power amplification transistor performs a switching operation, which inevitably causes distortion.
本考案は斯る点に鑑み、効率はＢ級に近い高効
率で且つ効率の良いＡ級動作を行なわせる様にし
た低周波電力増幅器のアイドリング電流制御装置
を提供せんとするもので、以下本考案の一実施例
を第２図〜第４図に従い説明する。 In view of this, the present invention aims to provide an idling current control device for a low frequency power amplifier that has high efficiency close to class B and is capable of performing efficient class A operation. An embodiment of the invention will be described with reference to FIGS. 2 to 4.
Q1，Q1′及びQ2，Q2′は低周波電力増幅器１を
構成する互いにダーリントン接続された電力増幅
用トランジスタ、２は電力増幅器１の各前段側ト
ランジスタQ1，Q2の入力側（ベース側）に設け
られたバイアス回路、R1は該バイアス回路を構
成する抵抗、３は低周波電力増幅器１の出力端子
で、該出力端子にはスピーカー（図示せず）が接
続されている。又該出力端子３と、バイアス回路
２との間には、低周波電力増幅器１の出力電圧の
振幅に応じた直流電流を発生してこれをバイアス
回路２に加え、低周波電力増幅器１のバイアス値
を可変させるバイアス制御回路４が設けられてい
る。該バイアス制御回路４は、バツフア増幅器
５、互いに逆方向接続された一対の整流用ダイオ
ードD1，D2にて構成される整流回路６、位相反
転回路（インバータ）７，８、ダイオードD3，
D4，D5，D6にて構成されるダイオードマトリツ
クス回路９、バツフア増幅器１０，１１等にて構
成されている。C1，C2は位相反転回路７，８の
入力端子間に直列接続したコンデンサで、そ
の接続点１２は接地されている。R2，R3，R4は
各バツフア増幅器５，１０，１１の一方の入力端
子と出力端子間に接続された抵抗である。そして
バツフア増幅器５の他方の入力端子が電力増幅器
１の出力端子３に接続され、バツフア増幅器１
０，１１の出力端子１３，１４が低周波電力増幅
器１のバイアス回路２を構成する抵抗R1の一端
及び他端に夫々接続されている。 Q 1 , Q 1 ′ and Q 2 , Q 2 ′ are mutually Darlington-connected power amplification transistors that constitute the low-frequency power amplifier 1, and 2 is the input side of each front-stage transistor Q 1 and Q 2 of the power amplifier 1. (on the base side), R1 is a resistor that constitutes the bias circuit, 3 is an output terminal of the low frequency power amplifier 1, and a speaker (not shown) is connected to the output terminal. . Further, between the output terminal 3 and the bias circuit 2, a DC current corresponding to the amplitude of the output voltage of the low frequency power amplifier 1 is generated and applied to the bias circuit 2, so as to bias the low frequency power amplifier 1. A bias control circuit 4 that varies the value is provided. The bias control circuit 4 includes a buffer amplifier 5, a rectifier circuit 6 composed of a pair of rectifier diodes D 1 and D 2 connected in opposite directions, a phase inversion circuit (inverter) 7 and 8, and a diode D 3 .
It is composed of a diode matrix circuit 9 composed of D 4 , D 5 and D 6 , buffer amplifiers 10 and 11, and the like. C 1 and C 2 are capacitors connected in series between the input terminals of the phase inversion circuits 7 and 8, and their connection point 12 is grounded. R 2 , R 3 , and R 4 are resistors connected between one input terminal and output terminal of each buffer amplifier 5, 10, and 11. The other input terminal of the buffer amplifier 5 is connected to the output terminal 3 of the power amplifier 1.
Output terminals 13 and 14 of 0 and 11 are connected to one end and the other end of a resistor R 1 constituting the bias circuit 2 of the low frequency power amplifier 1, respectively.
斯様に構成してなる低周波電力増幅器のアイド
リング電流制御装置の動作について次に説明す
る。 The operation of the idling current control device for a low frequency power amplifier constructed in this manner will be described next.
低周波電力増幅器１の出力端子３からバツフア
増幅器５を経た入力信号〔第３図Ａ〕は、ダイオ
ードD1，D2にて整流するのであるが、この時ダ
イオードD1，D2のスイツチングノイズが低周波
電力増幅器１側へ逆流しないようにバツフア増幅
器５を設けている。そしてダイオードD1，D2に
て第３図Ａの入力信号の振幅を＋側と−側に分け
て整流を行なわせ、ダイオードD1，D2の出力端
子に夫々第３図Ｂ，Ｃの様な波形の直流信号
を得る。 The input signal [Fig. 3A] that passes from the output terminal 3 of the low frequency power amplifier 1 to the buffer amplifier 5 is rectified by the diodes D 1 and D 2 , and at this time, the switching of the diodes D 1 and D 2 A buffer amplifier 5 is provided to prevent noise from flowing back to the low frequency power amplifier 1 side. Then, the amplitude of the input signal shown in Figure 3A is divided into the + side and the - side by the diodes D1 and D2 and rectified. Obtain DC signals with various waveforms.
しかし、このままでは、例えば低周波電力増幅
器１の出力端子３からバツフア増幅器５に＋側の
信号のみが入つた瞬間であれば、＋側即ちダイオ
ードD1の出力端子には整流出力が現われる
が、−側即ちダイオードD2の出力端子には整流
出力が現われない。従つてこの時低周波電力増幅
器１のトランジスタQ1′，Q2′が対称動作をせず、
歪が発生する。このため、位相反転回路７，８を
設け、ダイオードマトリツクス回路９にて、ダイ
オードD1の出力端子に現われる整流出力と位
相反転回路８の出力端子に現われる出力とを、
又ダイオードD2の出力端子に現われる整流出
力と位相反転回路７の出力端子に現われる出力
とを夫々足し合わせ、ダイオードマトリツクス回
路９の出力端子に夫々第３図Ｆ，Ｇに示すよ
うな波形の信号を得ている。 However, as it is, if only the + side signal enters the buffer amplifier 5 from the output terminal 3 of the low frequency power amplifier 1, for example, a rectified output will appear on the + side, that is, at the output terminal of the diode D1 . No rectified output appears on the - side, that is, at the output terminal of diode D2 . Therefore, at this time, the transistors Q 1 ′ and Q 2 ′ of the low frequency power amplifier 1 do not operate symmetrically,
Distortion occurs. For this purpose, phase inversion circuits 7 and 8 are provided, and a diode matrix circuit 9 converts the rectified output appearing at the output terminal of the diode D1 and the output appearing at the output terminal of the phase inversion circuit 8.
Furthermore, the rectified output appearing at the output terminal of the diode D2 and the output appearing at the output terminal of the phase inversion circuit 7 are added together, and the waveforms shown in FIG. 3F and G are outputted to the output terminal of the diode matrix circuit 9, respectively. I'm getting a signal.
之等の信号は、低周波電力増幅器１の出力端子
３からバツフア増幅器５に＋側の信号又は−側の
信号のみが入つた瞬間でも対称的に現われ、出力
端子３からの信号の振幅に応じた直流出力となつ
ている。そして夫々の直流出力をバツフア増幅器
１０，１１で増幅し、バイアス回路２の各端子即
ち抵抗R1の一端及び他端に夫々印加することに
より低周波電力増幅器１のアイドリング電流を、
低周波電力増幅器１の出力信号の振幅に応じて変
化させ、第４図に示す様に、トランジスタQ1′，
Q2′にはコレクタ電流Icのピーク値の半分のアイ
ドリング電流が流れる様にしている。そしてこの
時低周波電力増幅器１のトランジスタQ1′，Q2′は
Ａ級動作しており、いずれもカツトオフにならな
いので、歪も生じない。従つて第２図の低周波電
力増幅器１は、Ｂ級に近い高効率で而も歪率の良
いＡ級動作を行なう。 These signals appear symmetrically even at the moment when only the + side signal or the - side signal enters the buffer amplifier 5 from the output terminal 3 of the low frequency power amplifier 1, and depending on the amplitude of the signal from the output terminal 3. It is a direct current output. The idling current of the low frequency power amplifier 1 is then amplified by buffer amplifiers 10 and 11 and applied to each terminal of the bias circuit 2, that is, one end and the other end of the resistor R1 , respectively.
The amplitude of the output signal of the low frequency power amplifier 1 is changed according to the amplitude, and as shown in FIG .
An idling current that is half the peak value of the collector current Ic is made to flow through Q 2 '. At this time, the transistors Q 1 ' and Q 2 ' of the low frequency power amplifier 1 operate in class A operation, and neither of them is cut off, so that no distortion occurs. Therefore, the low frequency power amplifier 1 shown in FIG. 2 performs class A operation with high efficiency close to class B and a good distortion rate.
以上の様に、本考案に依れば、低周波電力増幅
器の出力信号の振幅に応じて低周波電力増幅器の
バイアス値を可変させ、低周波電力増幅器の出力
信号が大振幅であつても小振幅であつても夫々の
振幅に応じたアイドリング電流を流す様にしたの
で、低周波電力増幅器は無駄な電力損失がなくな
り、Ｂ級に近い高効率で動作し、而もＡ級動作す
るので、歪率もよい。 As described above, according to the present invention, the bias value of the low-frequency power amplifier is varied according to the amplitude of the output signal of the low-frequency power amplifier, and even if the output signal of the low-frequency power amplifier has a large amplitude, the bias value is small. Since the idling current is made to flow according to the amplitude of each amplitude, the low frequency power amplifier eliminates unnecessary power loss, operates at high efficiency close to class B, and still operates as class A. The distortion rate is also good.
尚、信号レベルに応じてバイアスを制御する技
術は実開昭52−21754号にも開示されているが本
願考案は＋側又は−側の信号が入力された瞬間に
於いてもバイアス制御回路からは対称的なバイア
ス制御信号が出力される為、一対の出力トランジ
スタは常に対称的な動作を為すこととなり、歪み
の発生が抑えられる。 Note that the technique of controlling the bias according to the signal level is also disclosed in Utility Model Application Laid-open No. 52-21754, but the present invention does not control the bias from the bias control circuit even at the moment when a positive or negative signal is input. Since a symmetrical bias control signal is outputted, the pair of output transistors always operate symmetrically, suppressing the occurrence of distortion.
第１図イ，ロはＡ級動作及びＢ級動作する低周
波電力増幅用トランジスタのコレクタ電流とアイ
ドリング電流との関係を示す波形図、第２図は本
考案に係る低周波電力増幅器のアイドリング電流
制御装置を示す回路図、第３図Ａ，Ｂ，Ｃ，Ｄ，
Ｅ，Ｆ，Ｇは、第２図の各点に於ける波形図、第
４図は第２図の回路を用いた場合の低周波電力増
幅用トランジスタのコレクタ電流とアイドリング
電流との関係を示す波形図である。
１……低周波電力増幅器、Q1′，Q2′……低周波
電力増幅用トランジスタ、２……バイアス回路、
３……出力端子、４……バイアス制御回路、６…
…整流回路。
Figures 1A and 1B are waveform diagrams showing the relationship between the collector current and idling current of low-frequency power amplification transistors operating in class A and class B operation, and Figure 2 shows the idling current of the low-frequency power amplifier according to the present invention. Circuit diagram showing the control device, Figure 3 A, B, C, D,
E, F, and G are waveform diagrams at each point in Figure 2, and Figure 4 shows the relationship between the collector current and idling current of the low-frequency power amplification transistor when the circuit in Figure 2 is used. FIG. 1...Low frequency power amplifier, Q1 ', Q2 '...Transistor for low frequency power amplification, 2...Bias circuit,
3... Output terminal, 4... Bias control circuit, 6...
...rectifier circuit.
Claims (1)
力増幅器のバイアス回路との間に、前記出力端
子からの信号を整流する整流回路を有し、該整
流回路の直流出力を前記バイアス回路に加えて
前記低周波電力増幅器のバイアス値を可変させ
るバイアス制御回路を設け、該バイアス制御回
路を前記整流回路の正負の夫々の出力を反転す
る位相反転回路と、前記整流回路及び前記位相
反転回路より出力される正出力同志及び負出力
同志の組合せ信号を出力するダイオードマトリ
ツクス回路より構成し、以つて前記低周波電力
増幅器には前記出力端子からの信号の振幅に応
じた大きさのアイドリング電流が流れる様にし
たことを特徴とする低周波電力増幅器のアイド
リング電流制御装置。 (2) 低周波電力増幅器は、Ａ級動作を行なうこと
を特徴とする実用新案登録請求の範囲第１項記
載の低周波電力増幅器のアイドリング電流制御
装置。[Claims for Utility Model Registration] (1) A rectifier circuit for rectifying the signal from the output terminal is provided between the output terminal of the low-frequency power amplifier and the bias circuit of the low-frequency power amplifier, and the rectifier circuit rectifies the signal from the output terminal. a bias control circuit that applies a DC output of the circuit to the bias circuit to vary a bias value of the low frequency power amplifier; and a phase inversion circuit that inverts the positive and negative outputs of the rectifier circuit; It is composed of a diode matrix circuit that outputs a combined signal of positive outputs and negative outputs outputted from the rectifying circuit and the phase inverting circuit, and the low frequency power amplifier is configured to control the amplitude of the signal from the output terminal. An idling current control device for a low frequency power amplifier, characterized in that an idling current of a magnitude corresponding to the current flows. (2) The idling current control device for a low frequency power amplifier according to claim 1, wherein the low frequency power amplifier performs class A operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979122575U JPS6214731Y2 (en) | 1979-09-04 | 1979-09-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979122575U JPS6214731Y2 (en) | 1979-09-04 | 1979-09-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5639723U JPS5639723U (en) | 1981-04-14 |
| JPS6214731Y2 true JPS6214731Y2 (en) | 1987-04-15 |
Family
ID=29354623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979122575U Expired JPS6214731Y2 (en) | 1979-09-04 | 1979-09-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214731Y2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856644U (en) * | 1981-10-15 | 1983-04-16 | 市光工業株式会社 | Automotive interior light |
| JPS5875132U (en) * | 1981-11-17 | 1983-05-20 | 日産自動車株式会社 | Vehicle lighting system |
| JP4805170B2 (en) * | 2004-12-27 | 2011-11-02 | 株式会社ダイヘン | High frequency power supply |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5221754B2 (en) * | 1972-09-18 | 1977-06-13 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5221754U (en) * | 1975-08-04 | 1977-02-16 |
-
1979
- 1979-09-04 JP JP1979122575U patent/JPS6214731Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5221754B2 (en) * | 1972-09-18 | 1977-06-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5639723U (en) | 1981-04-14 |
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